the attached patch adds SHA1 support for VIA PadLock engine.
Did VIA publish documentation for new instructions on their web-site? If
not and you have it, can you send a copy to me?
There are several design decisions that I may need to explain:
The xsha1 instruction always finalizes the MD
Andy Polyakov wrote:
The xsha1 instruction always finalizes the MD computation,
That kind of sucks...
Hopefully the next version of the CPU will have a new hashing
instruction that will finalize only on request. I was already in touch
with the CPU architects, explained them what problems
