: 4.22 ( 31Kops/s)
over_0565_8_0565 = L1: 10.76 L2: 9.69 M: 7.86 ( 62.79%) HT: 6.18 VT:
6.11 R: 5.97 RT: 3.48 ( 28Kops/s)
Thanks,
Nemanja Lukic
-Original Message-
From: Søren Sandmann [mailto:sandm...@cs.au.dk]
Sent: Tuesday, September 25, 2012 6:23 AM
To: Lukic, Nemanja
Cc
Any comments on this patch?
Kind regards,
Nemanja Lukic
Nemanja Lukic nlu...@mips.com wrote:
Added optimizations for several OVER fast paths:
- over__n_
- over__n_0565
- over_0565_n_0565
- over__8_
- over__8_0565
- over_0565_8_0565
Benchmark results (lowlevel-blt
Hi Soren,
I added more explanation in the commit message for that commit.
Sorry for the late reply. If you think that anything is missing in the commit
message, please tell me, and I'll update it.
Thanks,
Nemanja Lukic
-Original Message-
From:
Hi Siarhei,
Your comments for the bilinear commit are truly worth a lot more investigation,
and you did made a strong point that these optimizations should be revisited.
But, for now, these tweaks do need much time to implement, and may also
influence not only bilinear commit.
Since I do plan
, \alpha, \scratch1
+precrq.qb.ph\top, \alpha, \scratch1
.endm
#endif //PIXMAN_MIPS_DSPR2_ASM_H
-Original Message-
From: Siarhei Siamashka [mailto:siarhei.siamas...@gmail.com]
Sent: Friday, May 11, 2012 10:55 AM
To: Lukic, Nemanja
Cc: pixman@lists.freedesktop.org
Hi Siarhei,
You are right, 74k core is out-of-order dual-issue core (LS+ALU).
Using byte load instructions instead of the ANDI/EXT is nice tweak to try, with
potential big performance improvement.
I'll benchmark this, and upload a new patch (combined with the better-commented
commit for the fix
Sure, I'll put more info in the commit message and upload the patch again.
Thanks,
Nemanja Lukic
-Original Message-
From: Søren Sandmann [mailto:sandm...@cs.au.dk]
Sent: Thursday, May 10, 2012 7:47 PM
To: Lukic, Nemanja
Cc: pixman@lists.freedesktop.org; nemanja.lu...@rt-rk.com
Subject
;
Src value was inverted, which is wrong. I fixed this. I'll push new patch that
fixes this regression.
Thanks,
Nemanja Lukic
-Original Message-
From: Siarhei Siamashka [mailto:siarhei.siamas...@gmail.com]
Sent: Tuesday, May 08, 2012 1:35 AM
To: Lukic, Nemanja
Cc: pixman
Cc: Lukic, Nemanja; pixman@lists.freedesktop.org; nemanja.lu...@rt-rk.com
Subject: Re: [Pixman] [PATCH] MIPS: DSPr2: Added over_n_8_ and
over_n_8_0565 fast paths.
Siarhei Siamashka siarhei.siamas...@gmail.com writes:
+ /* a1 = src */
+ lbu t0, 0(a2
PM
To: Søren Sandmann
Cc: Lukic, Nemanja; pixman@lists.freedesktop.org; nemanja.lu...@rt-rk.com
Subject: Re: [Pixman] [PATCH] MIPS: DSPr2: Added over_n___ca and
over_n__0565_ca fast paths.
On Mon, Mar 12, 2012 at 10:48 PM, Søren Sandmann sandm...@cs.au.dk wrote:
Nemanja Lukic nlu
cache line size.
Thanks,
Nemanja Lukic
-Original Message-
From: Siarhei Siamashka [mailto:siarhei.siamas...@gmail.com]
Sent: Thursday, February 16, 2012 4:18 PM
To: Søren Sandmann
Cc: Lukic, Nemanja; pixman@lists.freedesktop.org
Subject: Re: [Pixman] [PATCH] MIPS: DSPr2: Basic
DDR2/DDR3 memory chips, and thus influence overall peak memory bandwidth.
Thanks,
Nemanja Lukic
-Original Message-
From: Siarhei Siamashka [mailto:siarhei.siamas...@gmail.com]
Sent: Thursday, February 16, 2012 5:21 PM
To: Lukic, Nemanja
Cc: pixman@lists.freedesktop.org; nemanja.lu...@rt
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