ocation/deallocation in the GC?
Or any other suggestions are much appreciated. Thank you.
Regards,
Logan
On Mon, Jan 29, 2024 at 6:51 PM Logan Chien
wrote:
> Hi CF,
>
> Thank you for your reply.
>
> >> I also ran test_ll_random.py with `--repeat=2 --random-seed=1234`
&
ast/slow paths)
5. realloc_frame
Regards,
Logan
On Sun, Feb 18, 2024 at 11:06 PM Armin Rigo wrote:
> Hi Logan,
>
> On Mon, 19 Feb 2024 at 05:02, Logan Chien
> wrote:
> > 2890 | OP_GC_INCREASE_ROOT_STACK_DEPTH(l_v498959, /*
> nothing */);
>
>
will try to figure
out the failing guard op first.
Regards,
Logan
On Mon, Feb 19, 2024 at 10:05 PM Armin Rigo wrote:
> Hi Logan,
>
> On Tue, 20 Feb 2024 at 05:08, Logan Chien
> wrote:
> > > This should just be #defined to do nothing with Boehm, maybe in
> rpytho
that I have to debug this the hard way.
Let's see if I can find more leads or not. Thank you.
Regards,
Logan
On Fri, Feb 16, 2024 at 1:38 AM Armin Rigo wrote:
> Hi Logan,
>
> On Fri, 16 Feb 2024 at 07:46, Logan Chien
> wrote:
> > pypy_module_cpyext.c:125333:80: error:
wrote:
> Hi Logan,
>
> On Tue, 9 Jan 2024 at 04:01, Logan Chien
> wrote:
> > Currently, I only target RV64 IMAD:
> >
> > I - Base instruction set
> > M - Integer multiplication
> > A - Atomic (used by call_release_gil)
> > D - Double precision f
t
> > all, but can you tell me what kind of setup does one need for testing
> > it? Are you using real hardware or emulation?
> >
> > The approach of starting with tests and getting translation done later
> > is very much what we have done in the past.
> >
&g
for the correctness?
2. How do we measure the performance? Do we have a command line that can
run all benchmarks?
Thank you in advance.
Regards,
Logan
p.s. All changes are at: https://github.com/loganchien/pypy/tree/rv64
On Mon, Jan 15, 2024 at 8:54 PM Logan Chien
wrote:
> Hi Maciej,
>
>
Best,
> Maciej
>
> On Wed, 10 Jan 2024 at 08:39, Logan Chien
> wrote:
> >
> > Hi Armin,
> >
> > > About the V extension, I'm not sure it would be helpful; do you plan
> > > to use it in the same way as our x86-64 vector extension support?
Hi,
I forgot to include the link in my previous email.
If you want to have a look on my prototype, you can find it here:
https://github.com/loganchien/pypy/tree/rv64
Thanks.
Regards,
Logan
On Sun, Jan 7, 2024 at 5:18 PM Logan Chien
wrote:
> Hi all,
>
> I would like to contribute
Hi all,
I would like to contribute a RISC-V 64 JIT backend for RPython. I have
made some progress at the end of 2023.
## Status
My prototype can pass the test cases below:
* test_runner.py
* test_basic.py and almost all test_ajit.py related tests (except
test_rvmprof.py)
*
sery fast path) (untriaged)
* Test Suite: pypyjit tests
* test_jitlogparser -- (untriaged)
* test_micronumpy -- (untriaged)
I also ran test_ll_random.py with `--repeat=2 --random-seed=1234` and
all test are passing.
Regards,
Logan
On Mon, Jan 22, 2024 at 10:19 PM Logan Chien
wrote:
t; default (e.g. whole night) to see if they find issues
>
> Best,
> Maciej Fijalkowski
>
> On Tue, 16 Jan 2024 at 07:02, Logan Chien
> wrote:
> >
> > Hi,
> >
> > I have good news: the RISC-V backend can pass as many unit tests as the
> AArch64 back
Hi CF,
Thank you for your reply.
>> I also ran test_ll_random.py with `--repeat=2 --random-seed=1234`
>> and all test are passing.
>
> How long does that take, in wall clock time? I think for the other
> backends we kept it running for a bunch of days after the last crash
> occurred.
It
Hi Matti,
Thank you for your information. I will try these this weekend.
Regards,
Logan
On Tue, Jan 16, 2024, 12:52 AM Matti Picus wrote:
> On 16/1/24 07:02, Logan Chien wrote:
>
> > Hi,
> >
> > I have good news: the RISC-V backend can pass as many unit tests as
>
Hi Armin,
Thank you for the reply. I'll check (1) the config, (2) the frontend code
that emits guard_not_invalidated, and (3) the actual performance on HW this
weekend.
Regards,
Logan
On Thu, Feb 29, 2024 at 4:45 AM Armin Rigo wrote:
> Hi Logan,
>
> On Thu, 29 Feb 2024 at 08:37, Lo
try to run it on the
real board this weekend.
On Wed, Feb 21, 2024 at 9:57 PM Logan Chien
wrote:
> Hi Armin,
>
> Thank you for the reply.
>
> Luckily, I found the bug. It was a bug in my write barrier card marking
> implementation. I misunderstood what AArch64 MVN instruction meant w
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