Signed-off-by: Blue Swirl blauwir...@gmail.com
---
tests/rtc-test.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/tests/rtc-test.c b/tests/rtc-test.c
index 983a980..f23ac3a 100644
--- a/tests/rtc-test.c
+++ b/tests/rtc-test.c
@@ -240,6 +240,22 @@ static void
On Fri, Apr 13, 2012 at 01:12:11PM +1000, David Gibson wrote:
On Thu, Apr 12, 2012 at 01:14:06PM +0300, Michael S. Tsirkin wrote:
On Thu, Apr 12, 2012 at 03:36:35PM +1000, David Gibson wrote:
[snip]
Good catch!
Unfortunately I find the approach a bit convoluted.
It also looks like
On 04/14/2012 05:48 PM, Michael Tokarev wrote:
On 14.04.2012 18:32, Michael Tokarev wrote:
On 14.04.2012 18:17, Michael Tokarev wrote:
Something in between 0.15 and 1.0 releases of qemu broke
all NetBSD PCI functions. This is visible in the lack of
any network devices in a NetBSD guest,
On Sat, Apr 14, 2012 at 07:15:31PM +0400, Michael Tokarev wrote:
Ping?
Its been 4 months ago, and NetBSD still can't be booted in qemu...
I understand this can be done differently, but the patch in
question changed behavour and it caused a visible regression,
so let's fix this regression
On Wed, Apr 11, 2012 at 10:10 PM, Anthony Liguori anth...@codemonkey.ws wrote:
On 04/11/2012 02:08 PM, Paolo Bonzini wrote:
Il 11/04/2012 19:25, Anthony Liguori ha scritto:
Off the top of my head: issues with v5:
polluting global namespace, must scope names
appropriately with vmxnet_
On 04/15/2012 12:11 PM, Michael S. Tsirkin wrote:
On Sat, Apr 14, 2012 at 07:15:31PM +0400, Michael Tokarev wrote:
Ping?
Its been 4 months ago, and NetBSD still can't be booted in qemu...
I understand this can be done differently, but the patch in
question changed behavour and it
On 04/12/2012 09:32 PM, Gerhard Wiesinger wrote:
Hello,
I'm having problems with recents kernels and qemu-kvm with a DOS VM:
TD286
System: Bad selector: 0007
System: Bad selector: 0D87
System: Bad selector: 001F
System: Bad selector: 0007
GP at 0020 21D4 EC 0DC4
Error 269 loading
On Mon, Apr 02, 2012 at 02:17:36PM +1000, David Gibson wrote:
Currently the pseries PCI code uses a somewhat strange scheme of PCI irq
allocation - one per slot up to a maximum that's greater than the usual 4.
This scheme more or less worked, because we were able to tell the guest the
irq
On Mon, Apr 02, 2012 at 02:17:35PM +1000, David Gibson wrote:
On the pseries platform, access to PCI config space is via RTAS calls(
which go to the hypervisor) rather than MMIO. This means we don't use
the same code path as nearly everyone else which goes through pci_host.c
and we're missing
On 4/14/12, Hervé Poussineau hpous...@reactos.org wrote:
Hi,
Patches 1 to 3 implement the pc87312 Super I/O chip.
Nice. It looks pretty similar to the SuperIO chip used in Ultra-5.
We could re-use it in our sun4u machine.
Blue, what do you think?
This patch has
been tested on PReP emulation
On Sun, Apr 15, 2012 at 01:03:57PM +0300, Michael S. Tsirkin wrote:
On Mon, Apr 02, 2012 at 02:17:36PM +1000, David Gibson wrote:
Currently the pseries PCI code uses a somewhat strange scheme of PCI irq
allocation - one per slot up to a maximum that's greater than the usual 4.
This scheme
On Sun, Apr 15, 2012 at 10:50, Artyom Tarasenko atar4q...@gmail.com wrote:
On 4/14/12, Hervé Poussineau hpous...@reactos.org wrote:
Hi,
Patches 1 to 3 implement the pc87312 Super I/O chip.
Nice. It looks pretty similar to the SuperIO chip used in Ultra-5.
We could re-use it in our sun4u
On Sun, Apr 15, 2012 at 09:47:47PM +1000, David Gibson wrote:
On Sun, Apr 15, 2012 at 01:03:57PM +0300, Michael S. Tsirkin wrote:
On Mon, Apr 02, 2012 at 02:17:36PM +1000, David Gibson wrote:
Currently the pseries PCI code uses a somewhat strange scheme of PCI irq
allocation - one per
Great! :)
Nice to see a new release out.
Please make a notice about the release on the front page of the seabios website.
On Sun, Apr 15, 2012 at 4:48 AM, Kevin O'Connor ke...@koconnor.net wrote:
The 1.7.0 version of SeaBIOS has now been released. For more
information on the release, please
Public bug reported:
The full error is attached.
Fixed by using downgrading to 0bcd08b3522e4feffe3111e7c8145f62d32cc1fb
Did some regression testing and found that this commit is the problem:
dec9c2d4306d7b4f8482ac42dc468ed2a61d is the first bad commit
commit
** Attachment added: log
https://bugs.launchpad.net/bugs/982321/+attachment/3071027/+files/SLidNn8F.txt
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/982321
Title:
User mode arm qemu segfault
This patchseries refactors the target-arm handling of coprocessor
registers so that you define each register with a struct (and
possibly some read/write/reset functions), rather than having
huge nested switch statements in get_cp15()/set_cp15().
My main aim here was to get rid of the
All the uses of ARM_CPUID() to vary behaviour have now been
removed, so we can delete the ARM_CPUID_* macros now.
The one exception is the TI915T/925T, because of its odd behaviour
where the MIDR value can be changed at runtime.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
Convert the (dummy) generic timer cp15 implementation.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 23 +++
1 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c61e0de..620e652
Am 15.04.2012 15:34, schrieb Serge Schneider:
Public bug reported:
The full error is attached.
Fixed by using downgrading to 0bcd08b3522e4feffe3111e7c8145f62d32cc1fb
Did some regression testing and found that this commit is the problem:
dec9c2d4306d7b4f8482ac42dc468ed2a61d is the
** Description changed:
The full error is attached.
- Fixed by using downgrading to 0bcd08b3522e4feffe3111e7c8145f62d32cc1fb
+ Fixed by downgrading to 0bcd08b3522e4feffe3111e7c8145f62d32cc1fb
Did some regression testing and found that this commit is the problem:
Convert the coprocessor access functions for the pxa2xx PIC to the
arm_cp_reginfo scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/pxa2xx_pic.c | 53 +++--
1 files changed, 31 insertions(+), 22 deletions(-)
diff --git
These patches add support for w64 hosts.
Patch 01 was already sent. It is needed for debugging of QEMU on w64.
The patches can also be pulled from
git://qemu.weilnetz.de/qemu.git w64
I tested all resulting 64 bit binaries by calling them without arguments
(so only the
Instead of type casts to long, w64 needs type casts to intptr_t.
For other hosts, this changes nothing.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
cpu-all.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpu-all.h b/cpu-all.h
index 4512518..58420be 100644
---
Variable physaddr is a host address which should be represented by
data type 'uintptr_t'.
This is needed for w64 and changes nothing for other hosts.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
softmmu_header.h |9 +++--
1 files changed, 3 insertions(+), 6 deletions(-)
diff --git
Convert the cp15 crn=7 registers to the new scheme.
Note that to do this we have to distinguish some registers
used on the ARM9 and ARM10 from some which are ARM1176
only. This is because the old code returned a value of 0
but always set the Z flag (by clearing env-ZF, since we
store the Z flag in
Convert the THUMB2EE cp14 registers TEECR and TEEHBR to
use arm_cp_reginfo.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c| 55 +--
target-arm/helper.h|2 -
target-arm/translate.c | 66
Convert the cp15 crn=0 crm={1,2} features registers to
the new cp reg framework.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c| 14 ---
target-arm/cpu.h|2 -
target-arm/helper.c | 62 --
3 files
Am 15.04.2012 16:13, schrieb Stefan Weil:
w64 requires uintptr_t.
Signed-off-by: Stefan Weils...@weilnetz.de
---
softmmu_header.h |6 +++---
softmmu_template.h | 20
2 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/softmmu_header.h
Convert the PXA2xx cp14 perf registers from old-style
coprocessor hooks to the new scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/pxa2xx.c | 142 +-
1 files changed, 61 insertions(+), 81 deletions(-)
diff --git
All the users of cpu_arm_set_cp_io have been converted, so we
can remove it and the infrastructure it used.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.h | 10
target-arm/helper.c| 54
For QOM'ified CPUs we cannot g_free() CPUArchState, we must
object_delete() the object it is embedded into.
Should fix LP#982321 (invalid free() while executing pacman w/qemu-arm).
Reported-by: Serge Schneider se...@xecdesign.com
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Peter Maydell
Convert the MMU fault status and MPU access permission cp15
registers to the new scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 188 +--
1 files changed, 107 insertions(+), 81 deletions(-)
diff --git
The MinGW-w64 compiler allows __attribute__((aligned (32)).
Signed-off-by: Stefan Weil s...@weilnetz.de
---
exec.c |3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index 3dda2ca..6d10595 100644
--- a/exec.c
+++ b/exec.c
@@ -93,8 +93,7 @@ spinlock_t
Remove the no-longer-used CPUARMState c0_cachetype field.
Although this was a constant register we had it in our
migration state. Drop this (with resulting version bump)
because for ARM currently we prefer cleaner migration
code and have not stabilised migration format yet.
Signed-off-by: Peter
This changes nothing for other hosts.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
target-mips/op_helper.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index bca1d70..5627447 100644
--- a/target-mips/op_helper.c
Convert the PXA2xx CLKCFG and PWRMODE cp14 registers to the
new arm_cp_reginfo scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
hw/pxa2xx.c | 171 --
1 files changed, 71 insertions(+), 100 deletions(-)
diff --git
Convert the final ID registers to the new cp15 scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c|2 -
target-arm/helper.c | 111 +--
2 files changed, 63 insertions(+), 50 deletions(-)
diff --git
On 04/15/2012 10:13 AM, Stefan Weil wrote:
Not all i386 / x86_64 hosts use ELF.
Ask the compiler whether ELF is used.
On w64, gdb crashes when ELF_HOST_MACHINE is defined.
Cc: Richard Henderson r...@twiddle.net
Cc: Blue Swirl blauwir...@gmail.com
Signed-off-by: Stefan Weil
Convert the cp15 crn=2 registers (MMU page table control,
MPU cache control) to the new scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c|1 -
target-arm/helper.c | 88 +++
2 files changed, 33
w64 uses the registers rcx, rdx, r8 and r9 for function arguments,
so it needs a different declaration of tcg_target_call_iarg_regs.
rax, rcx, rdx, r8, r9, r10 and r11 may be changed by function calls.
rbx, rbp, rdi, rsi, r12, r13, r14 and r15 remain unchanged by function calls.
Signed-off-by:
Convert the v7 performance monitor cp15 registers to
the new scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c |4 -
target-arm/helper.c| 277 +++-
target-arm/translate.c | 26 +-
3 files changed,
We RAZ/WI the entire block of crn=10 registers. Note that this
actually covers not just the implementation-defined TLB
lockdown registers but also a number of v7 VMSA memory
attribute registers which we would need to implement to
support TEX remap. We retain the previous QEMU behaviour
in this
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/core-dc232b.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/core-dc232b.c b/target-xtensa/core-dc232b.c
index 7c03835..804fdef 100644
---
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
target-xtensa/core-fsf.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/core-fsf.c b/target-xtensa/core-fsf.c
index c11d970..e36b0de 100644
--- a/target-xtensa/core-fsf.c
+++
This is Diamond 233L Standard Core Rev.C (LE), implemented through
linux/gdb overlay.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target|1 +
target-xtensa/core-dc233c.c| 55
target-xtensa/core-dc233c/core-isa.h | 475
Add new function register_cp_regs_for_features() as a place to
register coprocessor registers dependent on feature flags.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h |1 +
target-arm/cpu.c |2 ++
target-arm/helper.c | 11 +++
3 files
Am 15.04.2012 17:12, schrieb Max Filippov:
This is Diamond 233L Standard Core Rev.C (LE), implemented through
linux/gdb overlay.
Signed-off-by: Max Filippov jcmvb...@gmail.com
---
Makefile.target|1 +
target-xtensa/core-dc233c.c| 55
Convert the cp15 crn=1 registers to the new scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu-qom.h |1 +
target-arm/cpu.c |7 ++-
target-arm/helper.c | 129 +-
3 files changed, 61 insertions(+), 76
The default definition of setjmp which is implemented in MinGW-w64
cannot be used with programs like QEMU which call longjmp from
code without structured exception handling (SEH).
This code therefore disables stack unwinding.
We could also implement SEH for QEMU's generated JIT code, but
that is
This is needed for w64. It changes nothing for other hosts.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
disas.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/disas.c b/disas.c
index 4f2c4e4..27071c3 100644
--- a/disas.c
+++ b/disas.c
@@ -268,7 +268,7 @@ void
Portable printing of dev_offset (data type off_t) needs a type cast.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
nbd.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/nbd.c b/nbd.c
index 567e94e..406e555 100644
--- a/nbd.c
+++ b/nbd.c
@@ -813,7 +813,7 @@ static void
For w64, some entries need 'uintptr_t' instead of 'unsigned long'.
For other host systems, both data types are identical, so nothing changes.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
cpu-defs.h | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/cpu-defs.h
Am 14.04.2012 02:14, schrieb Andreas Färber:
Hello David,
This series merges my PowerPC QOM'ification v2 series with your
TCG/KVM limitations patch. The finalizer is dropped for now, and
cpu_ppc_close() drop has already been applied.
If I don't hear objections I'm going to apply this
Convert the cp15 crn=6 registers to the new scheme.
Note that this includes some minor tidyup: drop an unnecessary
underdecoding of op2 on OMAPCP cores, and only implement the
pre-v6 c6,c0,0,1 IFAR on the 1026 and not on the other ARMv5
cores, which didn't have it.
Signed-off-by: Peter Maydell
Am 15.04.2012 16:13, schrieb Stefan Weil:
This changes nothing for other hosts.
Cc: Alexander Graf ag...@suse.de
Signed-off-by: Stefan Weil s...@weilnetz.de
---
target-ppc/translate_init.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
(Had you used
Initial infrastructure for data-driven registration of
coprocessor register implementations.
We still fall back to the old-style switch statements pending
complete conversion of all existing registers.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c | 34
Not all i386 / x86_64 hosts use ELF.
Ask the compiler whether ELF is used.
On w64, gdb crashes when ELF_HOST_MACHINE is defined.
Cc: Richard Henderson r...@twiddle.net
Cc: Blue Swirl blauwir...@gmail.com
Signed-off-by: Stefan Weil s...@weilnetz.de
---
tcg/i386/tcg-target.c |6 +-
1
Convert the MPIDR to the new cp15 register scheme.
This includes giving it its own feature bit rather
than doing a CPUID value check.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c|2 ++
target-arm/cpu.h|1 +
target-arm/helper.c | 50
w64 requires uintptr_t.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
softmmu_header.h |6 +++---
softmmu_template.h | 20
2 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/softmmu_header.h b/softmmu_header.h
index edc7826..77c95dc 100644
---
Convert TLS registers to the new cp15 framework
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c| 19 +++
target-arm/translate.c | 58
2 files changed, 19 insertions(+), 58 deletions(-)
diff --git
There are now no uses of the old cp15 infrastructure,
so it can be deleted.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c| 39 ---
target-arm/helper.h|3 --
target-arm/translate.c | 59
Replace all type casts to 'long' or 'unsigned long' by 'intptr_t' or
'uintptr_t'.
For type casts which are only used to extract the lower bits of an address
or to modify those bits, signedness does not matter. There I always use
'uintptr_t'.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
This change is needed for w64, but also changes the code for other hosts.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
cpu-exec.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index d153f97..0344cd5 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
On 15 April 2012 15:39, Andreas Färber afaer...@suse.de wrote:
For QOM'ified CPUs we cannot g_free() CPUArchState, we must
object_delete() the object it is embedded into.
Should fix LP#982321 (invalid free() while executing pacman w/qemu-arm).
Reported-by: Serge Schneider se...@xecdesign.com
tb.time is a time value, but not necessarily of the same size as time_t:
while time_t is 64 bit for w64, tb.time still is 32 bit only.
Therefore we need en explicit conversion.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
savevm.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
Convert the various WFI and barrier instruction special cases to use
cp_reginfo infrastructure.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c| 42 +++
target-arm/translate.c | 51
Convert cp15 crn=9 registers (mostly cache lockdown) to the new scheme.
Note that this change makes OMAPCP cores RAZ/WI the whole c9 space. This is
a change from previous behaviour, but a return to the behaviour of commit
c3d2689d when OMAP1 support was first added -- subsequent commits have
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR,
and the ARM946 Trace Process Identifier Register).
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 61 ++-
1 files changed, 31 insertions(+), 30 deletions(-)
Convert the cp15 VA-PA translation registers (a subset of
the crn=7 regs) to the new scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 108 ++
1 files changed, 65 insertions(+), 43 deletions(-)
diff --git
Move the v6 optional block cache ops to the new cp15 framework.
This includes only providing them on the CPUs which implemented
them, rather than the previous blunderbuss approach of making
all MCRR instructions on all CPUs act as NOPs.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
The MinGW-w64 compiler complains about a non-void function
which does not return a value.
This is not true, but we can help the compiler to
see that by rewriting the code.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
block/raw-win32.c |6 ++
1 files changed, 2 insertions(+), 4
Patch submitted: http://patchwork.ozlabs.org/patch/152614/
Sorry and thanks for reporting!
** Changed in: qemu
Status: New = In Progress
** Changed in: qemu
Assignee: (unassigned) = Andreas Färber (afaerber)
--
You received this bug notification because you are a member of qemu-
w64 needs uintptr_t instead of unsigned long.
For other hosts, nothing changes.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
cpu-all.h |8
exec.c|6 +++---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/cpu-all.h b/cpu-all.h
index 58420be..f7d6867 100644
Convert cp15 MMU TLB control (crn=8) to new scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c | 63 ++
1 files changed, 43 insertions(+), 20 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
Convert the cp15 cache ID registers to the new scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c|2 -
target-arm/cpu.h|2 -
target-arm/helper.c | 61 +++---
3 files changed, 33 insertions(+), 32
Convert the cp14 debug registers (DBGDIDR, DBGDRAR, DBGDSAR) to the
cp_reginfo scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/helper.c| 25 +
target-arm/translate.c | 28
2 files changed, 25 insertions(+),
Convert the cp15 c3 register (MMU domain access control
or MPU write buffer control). NB that this is horribly
underdecoded for modern cores (should be crn=3,crm=0,
opc1=0,opc2=0) but this change preserves the existing
QEMU behaviour.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
Casting a pointer to an integer must use (DWORD_PTR) instead of (DWORD).
This also matches the definition of 'fd' (gint for w32, gint64 for w64).
Signed-off-by: Stefan Weil s...@weilnetz.de
---
main-loop.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/main-loop.c
This changes nothing for other hosts.
Cc: Alexander Graf ag...@suse.de
Signed-off-by: Stefan Weil s...@weilnetz.de
---
target-ppc/translate_init.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index
Convert the cp15 crn=15 (implementation specific) registers
to the new scheme.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/cpu.c| 40 ++-
target-arm/cpu.h|1 +
target-arm/helper.c | 202 ++-
3 files
Am 13.04.2012 14:00, schrieb Meador Inge:
On 04/13/2012 06:40 AM, Andreas Färber wrote:
Am 12.04.2012 19:24, schrieb Scott Wood:
On 04/12/2012 11:59 AM, Andreas Färber wrote:
Am 10.04.2012 22:04, schrieb Meador Inge:
commit f7aa558396dd0f6b7a2b22c05cb503c655854102 pulled the dcache and
On 04/09/2012 03:17 PM, Blue Swirl wrote:
Use uintptr_t instead of void * or unsigned long in
several op related functions, env-mem_io_pc and
GETPC() macro.
Signed-off-by: Blue Swirl blauwir...@gmail.com
Reviewed-by: Richard Henderson r...@twiddle.net
r~
As those defines are only used for w32,
they should be in the header file for w32.
All files which include slirp.h or qemu_socket.h also
include qemu-os-win32.h.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
qemu-os-win32.h | 26 ++
qemu_socket.h |6 --
This could also be done in arm-semi.c, but doing it here keeps more
w64 related code in one place.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
qemu-os-win32.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/qemu-os-win32.h b/qemu-os-win32.h
index 753679b..99e8423
Am 21.03.2012 20:20, schrieb Peter Maydell:
On 19 March 2012 22:57, Juan Quintela quint...@redhat.com wrote:
Signed-off-by: Juan Quintela quint...@redhat.com
---
target-ppc/machine.c |8
1 files changed, 0 insertions(+), 8 deletions(-)
Could we give this patch a more
The first patch is the same as before.
The second patch is not 100% optimal as we could anticipate for
example KVM/ARM or some future qtests which need BIOS or kernel, but
it works for now.
I tested the targets like this:
$ for f in obj-amd64/*-softmmu/qemu-system-*; do echo $f; ./$f -qtest
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
tests/rtc-test.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/tests/rtc-test.c b/tests/rtc-test.c
index 983a980..f23ac3a 100644
--- a/tests/rtc-test.c
+++ b/tests/rtc-test.c
@@ -240,6 +240,22 @@ static void
Add simple m48t59 qtests, enable test only for Sparc32
and Sparc64. On PPC, the device is behind PCI bus.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
tests/Makefile |5 +
tests/m48t59-test.c | 259 +++
2 files changed, 264
For QOM'ified CPUs we cannot g_free() CPUArchState, we must
object_delete() the object it is embedded into.
Fixes LP#982321 (invalid free() while executing pacman with qemu-arm).
Reported-by: Serge Schneider se...@xecdesign.com
Reported-by: Russell Keith Davis russ...@russelldavis.org
On Sun, Apr 15, 2012 at 14:13, Stefan Weil s...@weilnetz.de wrote:
This could also be done in arm-semi.c, but doing it here keeps more
w64 related code in one place.
This is just papering over the bug, it could show up with a different
OS. The right fix is to change arm-semi.c to prefix the
On Sun, Apr 15, 2012 at 14:13, Stefan Weil s...@weilnetz.de wrote:
The default definition of setjmp which is implemented in MinGW-w64
cannot be used with programs like QEMU which call longjmp from
code without structured exception handling (SEH).
We're currently compiling QEMU with -no-seh, is
On Sun, Apr 15, 2012 at 14:13, Stefan Weil s...@weilnetz.de wrote:
Variable physaddr is a host address which should be represented by
data type 'uintptr_t'.
As you note, the name is wrong and should be fixed, for example
'hostaddr' or 'raw_ptr' would be better. If you need to revisit the
Am 15.04.2012 19:02, schrieb Blue Swirl:
On Sun, Apr 15, 2012 at 14:13, Stefan Weil s...@weilnetz.de wrote:
The default definition of setjmp which is implemented in MinGW-w64
cannot be used with programs like QEMU which call longjmp from
code without structured exception handling (SEH).
We're
On Sun, Apr 15, 2012 at 14:13, Stefan Weil s...@weilnetz.de wrote:
The MinGW-w64 compiler complains about a non-void function
which does not return a value.
This is not true, but we can help the compiler to
see that by rewriting the code.
Signed-off-by: Stefan Weil s...@weilnetz.de
---
Am 15.04.2012 19:00, schrieb Blue Swirl:
On Sun, Apr 15, 2012 at 14:13, Stefan Weils...@weilnetz.de wrote:
This could also be done in arm-semi.c, but doing it here keeps more
w64 related code in one place.
This is just papering over the bug, it could show up with a different
OS. The right fix
On Sun, Apr 15, 2012 at 17:09, Stefan Weil s...@weilnetz.de wrote:
Am 15.04.2012 19:02, schrieb Blue Swirl:
On Sun, Apr 15, 2012 at 14:13, Stefan Weil s...@weilnetz.de wrote:
The default definition of setjmp which is implemented in MinGW-w64
cannot be used with programs like QEMU which call
Am 15.04.2012 19:13, schrieb Blue Swirl:
On Sun, Apr 15, 2012 at 14:13, Stefan Weils...@weilnetz.de wrote:
The MinGW-w64 compiler complains about a non-void function
which does not return a value.
This is not true, but we can help the compiler to
see that by rewriting the code.
Am 15.04.2012 12:16, schrieb Michael S. Tsirkin:
On Mon, Apr 02, 2012 at 02:17:35PM +1000, David Gibson wrote:
On the pseries platform, access to PCI config space is via RTAS calls(
which go to the hypervisor) rather than MMIO. This means we don't use
the same code path as nearly everyone
Am 04.04.2012 07:02, schrieb David Gibson:
PAPR virtual IO (VIO) devices require a unique, but otherwise arbitrary,
address used as a token to the hypercalls which manipulate them.
Currently the pseries machine code does an ok job of allocating these
addresses when the legacy -net nic /
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