On Wed, Apr 16, 2014 at 04:23:44PM +0200, Igor Mammedov wrote:
On Wed, 16 Apr 2014 16:59:25 +0800
Hu Tao hu...@cn.fujitsu.com wrote:
On Fri, Apr 04, 2014 at 03:36:38PM +0200, Igor Mammedov wrote:
initialize and map hotplug memory address space container
into guest's RAM address space.
On 04/16/2014 07:52 PM, Michael S. Tsirkin wrote:
On Wed, Apr 16, 2014 at 07:47:37PM +0200, Andreas Färber wrote:
Am 16.04.2014 19:40, schrieb Michael S. Tsirkin:
On Wed, Apr 16, 2014 at 06:48:08PM +0200, Andreas Färber wrote:
Am 16.04.2014 18:32, schrieb Alexander Graf:
On 16.04.14 16:44,
Andy Lutomirski l...@amacapital.net writes:
On Mon, Apr 14, 2014 at 1:15 AM, Markus Armbruster arm...@redhat.com wrote:
Peter Crosthwaite peter.crosthwa...@xilinx.com writes:
Hi Andy,
On Thu, Apr 10, 2014 at 5:55 AM, Andy Lutomirski l...@amacapital.net
wrote:
Currently, -M q35 boots
Andreas Färber afaer...@suse.de writes:
Am 16.04.2014 08:42, schrieb Markus Armbruster:
Peter Crosthwaite peter.crosthwa...@xilinx.com writes:
On Wed, Apr 16, 2014 at 2:16 AM, Andreas Färber afaer...@suse.de wrote:
Am 15.04.2014 04:21, schrieb Peter Crosthwaite:
So clients can set the top
Peter Crosthwaite peter.crosthwa...@xilinx.com writes:
On Wed, Apr 16, 2014 at 6:05 PM, Markus Armbruster arm...@redhat.com wrote:
Peter Crosthwaite peter.crosthwa...@xilinx.com writes:
Hi Markus,
This series introduces qemu_get_boot_opts(), in much the same way as
was done for
On Wed, 16 Apr 2014 20:32:07 +0300
Michael S. Tsirkin m...@redhat.com wrote:
On Wed, Apr 16, 2014 at 05:42:22PM +0100, Peter Maydell wrote:
On 16 April 2014 17:34, Michael S. Tsirkin m...@redhat.com wrote:
so it looks like virtio is currently compiled per-target.
So why isn't it
Qiao Nuohan qiaonuo...@cn.fujitsu.com writes:
The last version is here:
http://lists.nongnu.org/archive/html/qemu-devel/2014-04/msg00018.html
ChangLog:
Changes from v7 to v8:
1. add a patch to fix doc of dump-guest-memory
Qiao Nuohan (2):
HMP: fix doc of dump-guest-memory
HMP:
Am 17.04.2014 um 00:53 hat Max Reitz geschrieben:
On 16.04.2014 23:48, Max Reitz wrote:
On 16.04.2014 17:00, Kevin Wolf wrote:
Am 12.04.2014 um 20:57 hat Max Reitz geschrieben:
Implement progress output for the commit command by querying the
progress of the block job.
Signed-off-by: Max
On 17 April 2014 04:06, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
Hi Peter,
On Tue, Apr 15, 2014 at 1:17 PM, Peter Crosthwaite
Peter Crosthwaite (4):
util/fifo: Generalise naming scheme
util/fifo: Generalise for common integer widths
ssi: pl022: Send debug info to stderr
On Thu, Apr 17, 2014 at 08:54:12AM +0200, Greg Kurz wrote:
On Wed, 16 Apr 2014 20:32:07 +0300
Michael S. Tsirkin m...@redhat.com wrote:
On Wed, Apr 16, 2014 at 05:42:22PM +0100, Peter Maydell wrote:
On 16 April 2014 17:34, Michael S. Tsirkin m...@redhat.com wrote:
so it looks like
On 15 April 2014 05:15, Michael Roth mdr...@linux.vnet.ibm.com wrote:
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
fourth release candidate for the QEMU 2.0 release. This release is meant
for testing purposes and should not be used in a production
The last version is here:
http://lists.nongnu.org/archive/html/qemu-devel/2014-04/msg00018.html
ChangLog:
Changes from v7 to v8:
1. add a patch to fix doc of dump-guest-memory
Qiao Nuohan (2):
HMP: fix doc of dump-guest-memory
HMP: support specifying dump format for dump-guest-memory
Dumping guest memory is available to specify the dump format now. This patch
adds options '-z|-l|-s' to HMP command dump-guest-memory to specify dumping in
kdump-compression format, with zlib/lzo/snappy compression. And without these
options ELF format will be used.
The discussion about this
Signed-off-by: Qiao Nuohan qiaonuo...@cn.fujitsu.com
---
hmp-commands.hx | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/hmp-commands.hx b/hmp-commands.hx
index f3fc514..c242770 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -999,25 +999,26 @@ ETEXI
On 04/16/2014 04:51 PM, Qiao Nuohan wrote:
The last version is here:
http://lists.nongnu.org/archive/html/qemu-devel/2014-04/msg00018.html
ChangLog:
Changes from v7 to v8:
1. add a patch to fix doc of dump-guest-memory
Qiao Nuohan (2):
HMP: fix doc of dump-guest-memory
HMP: support
Am 17.04.2014 um 05:34 hat Fam Zheng geschrieben:
Signed-off-by: Fam Zheng f...@redhat.com
---
block/vmdk.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
Thanks, applied to the block branch.
@@ -1720,7 +1721,7 @@ static int vmdk_create(const char *filename,
On Mi, 2014-04-16 at 17:02 -0400, Gabriel L. Somlo wrote:
OK, so I have the legacy (field-by-field, types 0 and 1 only) code
back in, right next to the new aggregate-smbios-table-plus-entrypoint
code, tested and apparently working fine.
Before I get carried away with git rebase, do we still
Am 16.04.2014 um 23:36 hat Max Reitz geschrieben:
On 16.04.2014 03:34, Fam Zheng wrote:
bdrv_getlength could fail, check the return value before using it.
Return NULL and set errno if it fails. Callers are updated to handle
the error case.
Signed-off-by: Fam Zheng f...@redhat.com
---
On Thu, 04/17 09:29, Kevin Wolf wrote:
Am 17.04.2014 um 00:53 hat Max Reitz geschrieben:
On 16.04.2014 23:48, Max Reitz wrote:
On 16.04.2014 17:00, Kevin Wolf wrote:
Am 12.04.2014 um 20:57 hat Max Reitz geschrieben:
Implement progress output for the commit command by querying the
Hi, everyone
Any comments on this one ? This patch fixes
pretty serious performance issues on windows, it would be
great to have this in 2.0.0
On 04/15/2014 12:41 PM, Stanislav Vorobiov wrote:
From: Sangho Park sangho1206.p...@samsung.com
g_poll has a problem on windows when using
timeouts
On 17.04.14 05:13, Stuart Yoder wrote:
-Original Message-
From: Alexander Graf [mailto:ag...@suse.de]
Sent: Monday, April 14, 2014 6:01 AM
To: Yoder Stuart-B08248
Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org
Subject: Re: [PATCH 1/2] QEMU: PPC: specify PVRs for all e500 cores
On
Am 16.04.2014 um 15:25 hat John Eckersberg geschrieben:
Public bug reported:
In qemu_gluster_init, if the call to either glfs_set_volfile_server or
glfs_set_logging fails into the out case, glfs_fini is called without
having first calling glfs_init. This causes glfs_lock to spin forever
on
On Thu, 04/17 10:28, Kevin Wolf wrote:
Am 17.04.2014 um 05:34 hat Fam Zheng geschrieben:
Signed-off-by: Fam Zheng f...@redhat.com
---
block/vmdk.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
Thanks, applied to the block branch.
@@ -1720,7 +1721,7 @@ static
Signed-off-by: Fam Zheng f...@redhat.com
---
block/vmdk.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/block/vmdk.c b/block/vmdk.c
index 938a183..c761584 100644
--- a/block/vmdk.c
+++ b/block/vmdk.c
@@ -262,7 +262,7 @@ static uint32_t
On 2 April 2014 13:47, Peter Maydell peter.mayd...@linaro.org wrote:
On 2 April 2014 13:11, Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
Like others, I have been carrying this change locally. Good to see it up!
Why are you all booting raw Images anyway (just out of curiosity)?
Given
Am 17.04.2014 um 11:39 hat Fam Zheng geschrieben:
Signed-off-by: Fam Zheng f...@redhat.com
---
block/vmdk.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/block/vmdk.c b/block/vmdk.c
index 938a183..c761584 100644
--- a/block/vmdk.c
+++ b/block/vmdk.c
@@
On Thu, 17 Apr 2014 09:46:28 +1000
Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
On Fri, Apr 4, 2014 at 11:36 PM, Igor Mammedov imamm...@redhat.com wrote:
Adds get_hotplug_handler() method to machine, and
makes bus-less device to use it during hotplug
as a means to discover hotplug
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
To bring it up to date with styling guidelines.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
2e837af80a18216c21e73241032e048f39d78b99.1396503037.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
From: Beniamino Galvani b.galv...@gmail.com
Signed-off-by: Beniamino Galvani b.galv...@gmail.com
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id: 1395771730-16882-7-git-send-email-b.galv...@gmail.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Change the DB_PRINT macro over to a regular if() rather than
conditional compilation to give constant compile testing of formats.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Phys must respond to address 0 by specification. Implement.
Signed-off-by: Nathan Rossi nathan.ro...@xilinx.com
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
This switch logic should not fall through. Fix.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
74147b4c017c904364955cc73107f90e6ac8ba74.1396326389.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
Implement the AArch64 RVBAR register, which indicates the reset
address. Since the reset address is implementation defined and
usually configurable by setting config signals in hardware, we
also provide a QOM property so it can be set at board level if
necessary.
Signed-off-by: Peter Maydell
Implement the AArch64 address translation operations.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/cpu.h| 3 +--
target-arm/helper.c | 53 -
2 files
From: Chen Gang gang.chen.5...@gmail.com
Clean up useless 'break' statement after 'return' statement.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
target-arm/gdbstub64.c |
Implement the AArch64 view of the ACTLR (auxiliary control
register). Note that QEMU internally tends to call this
AUXCR for historical reasons.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/helper.c | 3 ++-
1
Move arm_log_exception() into internals.h so we can use it from
helper-a64.c for the AArch64 exception entry code.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/helper.c| 31 ---
Currently cpu.h defines a mixture of functions and types needed by
the rest of QEMU and those needed only by files within target-arm/.
Split the latter out into a new header so they aren't needlessly
exposed further than required.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by:
From: Rob Herring rob.herr...@linaro.org
Implement exception handling for AArch64 EL1. Exceptions from AArch64 or
AArch32 EL0 are supported.
Signed-off-by: Rob Herring rob.herr...@linaro.org
[PMM: fixed minor style nits; updated to match changes in
previous patches; added some of the simpler
Implement AArch64 view of the CONTEXTIDR register.
We tighten up the condition when we flush the TLB on a CONTEXTIDR
write to avoid needlessly flushing the TLB every time on a 64
bit system (and also on a 32 bit system using LPAE, as a bonus).
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
From: Rob Herring rob.herr...@linaro.org
Implement AArch64 views of ESR_EL1 and FAR_EL1, and make the 32 bit
DFSR, DFAR, IFAR share state with them as architecturally specified.
The IFSR doesn't share state with any AArch64 register visible at EL1,
so just rename the state field without widening
For system mode, we may have a 64 bit CPU which is currently executing
in AArch32 state; if we're dumping CPU state to the logs we should
therefore show the correct state for the current execution state,
rather than hardwiring it based on the type of the CPU. For consistency
with how we handle
The ARM946 model currently uses the c5_data and c5_insn fields in the CPU
state struct to store the contents of its access permission registers.
This is confusing and a good source of bugs because for all the MMU-based
CPUs those fields are fault status and fault address registers, which
behave
The Cortex-A15's CBAR register is actually read-only (unlike that
of the Cortex-A9). Correct our model to match the hardware.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/cpu.c | 2 +-
1 file changed, 1
Suppress the ID_AA64DFR0_EL1 PMUVer field, even if the CPU specific
value claims that it exists. QEMU doesn't currently implement it,
and not advertising it prevents the guest from trying to use it
and getting UNDEFs on unimplemented registers.
Signed-off-by: Peter Maydell
The current A32/T32 decoder bases its is VFP/Neon enabled? check
on the FPSCR.EN bit. This is correct if EL1 is AArch32, but for
an AArch64 EL1 the logic is different: it must act as if FPSCR.EN
is always set. Instead, trapping must happen according to CPACR
bits for cp10/cp11; these cover all of
Because unallocated encodings generate different exception syndrome
information from traps due to FP being disabled, we can't do a single
is fp access disabled check at a high level in the decode tree.
To help in catching bugs where the access check was forgotten in some
code path, we set this
From: Rob Herring rob.herr...@linaro.org
Set up the required syndrome information when we detect an MMU fault.
Signed-off-by: Rob Herring rob.herr...@linaro.org
[PMM: split out from exception handling patch, tweaked to bring
in line with how we create other kinds of syndrome information]
From: Beniamino Galvani b.galv...@gmail.com
This patch implements proper updating of the vector register which
should hold, according to the A10 user manual, the vector address for
the interrupt currently active on the CPU IRQ input.
Interrupt priority is not implemented at the moment and thus
-rc3 release (2014-04-14 17:45:11 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140417
for you to fetch changes up to 123218cff73573c646af89dfa36662713498fcd0:
target-arm: A64: fix unallocated test of scalar SQXTUN
From: Rob Herring rob.herr...@linaro.org
Add support for v8 page table walks. This supports stage 1 translations
for 4KB, 16KB and 64KB page sizes starting with 0 or 1 level.
Signed-off-by: Rob Herring rob.herr...@linaro.org
[PMM: fix style nits, fold in 16/64K page support patch, use
For ARMv8 there are two changes to the MVFR media feature registers:
* there is a new MVFR2 which is accessible from 32 bit code
* 64 bit code accesses these via the usual sysreg instructions
rather than with a floating-point specific instruction
Implement this.
Signed-off-by: Peter Maydell
Add new helpers exception_with_syndrome (for generating an exception
with syndrome information) and exception_uncategorized (for generating
an exception with Unknown or Uncategorized Reason, which have a syndrome
register value of zero), and use them to generate the correct syndrome
information
Implement the DAIF system register which is a view of the
DAIF bits in PSTATE. To avoid needing a readfn, we widen
the daif field in CPUARMState to uint64_t.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/cpu.h
Implement handling for the AArch64 SP_EL0 system register.
This holds the EL0 stack pointer, and is only accessible when
it's not being used as the stack pointer, ie when we're in EL1
and EL1 is using its own stack pointer. We also provide a
definition of the SP_EL1 register; this isn't guest
For AArch32 exceptions, the only information provided about
the cause of an exception is the individual exception type (data
abort, undef, etc), which we store in cs-exception_index. For
AArch64, the CPU provides much more detail about the cause of
the exception, which can be found in the syndrome
For exceptions taken to AArch64, if a coprocessor/system register
access fails due to a trap or enable bit then the syndrome information
must include details of the failing instruction (crn/crm/opc1/opc2
fields, etc). Make the decoder construct the syndrome information
at translate time so it can
For the A64 instruction set, the only FP/Neon disable trap
is the CPACR FPEN bits, which may indicate enabled, disabled
or disabled for EL0. Add a bit to the AArch64 tb flags indicating
whether FP/Neon access is currently enabled and make the decoder
emit code to raise exceptions on use of FP/Neon
On Thu, Apr 17, 2014 at 11:27:52AM +0200, Kevin Wolf wrote:
Am 16.04.2014 um 15:25 hat John Eckersberg geschrieben:
Public bug reported:
In qemu_gluster_init, if the call to either glfs_set_volfile_server or
glfs_set_logging fails into the out case, glfs_fini is called without
having
Implement the auxiliary fault status registers AFSR0_EL1 and
AFSR1_EL1. These are present on v7 and later, and have IMPDEF
behaviour; we choose to RAZ/WI for all cores.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
On Wed, 16 Apr 2014 13:32:43 +0200
Alexander Graf ag...@suse.de wrote:
On 14.04.14 18:48, Cornelia Huck wrote:
From: Christian Borntraeger borntrae...@de.ibm.com
We also need to sync guest breaking event address and program parameter
register for migration support.
Signed-off-by:
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
The smlald (and probably smlsld) instruction was doing incorrect sign
extensions of the operands amongst 64bit result calculation. The
instruction psuedo-code is:
operand2 = if m_swap then ROR(R[m],16) else R[m];
product1 = SInt(R[n]15:0) *
Implement the DC ZVA instruction, which clears a block of memory.
The fast path obtains a pointer to the underlying RAM via the TCG TLB
data structure so we can do a direct memset(), with fallback to a
simple byte-store loop in the slow path.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
The AArch64 usermode 'any' CPU type was accidentally specified
with the ARM_FEATURE_THUMB2EE bit set. This is incorrect since
ARMv8 removes Thumb2EE completely. Since we never implemented
Thumb2EE anyway having the feature bit set was fairly harmless
for user-mode, but the correct thing is to not
From: Beniamino Galvani b.galv...@gmail.com
The model was generating interrupts for all enabled timers after the
expiration of one of them. Avoid this by passing explicitly the timer
index to the callback function.
Signed-off-by: Beniamino Galvani b.galv...@gmail.com
Reviewed-by: Li Guang
From: Beniamino Galvani b.galv...@gmail.com
The pending register is read-only and the value returned upon a read
reflects the state of irq input pins (interrupts are level triggered).
This patch implements such behaviour.
Signed-off-by: Beniamino Galvani b.galv...@gmail.com
Reviewed-by: Li Guang
Implement a subset of the Cortex-A57's implementation defined system
registers. We provide RAZ/WI or reads-as-constant/writes-ignored
implementations of the various control and syndrome reigsters.
We do not implement registers which provide direct access to and
manipulation of the L1 cache, since
Am 11.04.2014 07:41, schrieb Alistair Francis:
On Thu, Apr 10, 2014 at 11:48 PM, Alexander Graf ag...@suse.de wrote:
On 10.04.14 15:26, Peter Crosthwaite wrote:
On Thu, Apr 10, 2014 at 1:33 AM, Eric Auger eric.au...@linaro.org wrote:
Initial attempts to convince QEMU to create a memory mapped
Implement the ISR_EL1 register. This is actually present in
ARMv7 as well but was previously unimplemented. It is a
read-only register that indicates whether interrupts are
currently pending.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite
Add Cortex-A57 processor.
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Acked-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/cpu64.c | 43 +++
1 file changed, 43 insertions(+)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
In ARMv8 the 32 bit coprocessor ID register space is tidied up to
remove the wildcarded aliases of the MIDR and the RAZ behaviour
for the unassigned space where crm = 3..7. Make sure we don't
expose thes wildcards for v8 cores. This means we need to have
a specific implementation for REVIDR, an
Kevin Wolf (3):
block: Add errp to bdrv_new()
block: Catch duplicate IDs in bdrv_new()
qemu-iotests: Check common namespace for id and node-name
block.c| 19 +--
block/iscsi.c | 4 ++-
block/vvfat.c | 3 +-
blockdev.c
This patch adds an errp parameter to bdrv_new() and updates all its
callers. The next patch will make use of this in order to check for
duplicate IDs. Most of the callers know that their ID is fine, so they
can simply assert that there is no error.
Behaviour doesn't change with this patch yet as
From: Beniamino Galvani b.galv...@gmail.com
This implements the prescaler and source fields of the timer control
register. The source for each timer can be selected among 4 clock
inputs whose frequencies are set through model properties.
Signed-off-by: Beniamino Galvani b.galv...@gmail.com
Since commit f298d071, block devices added with blockdev-add don't have
a QemuOpts around in dinfo-opts. Consequently, we can't rely any more
on QemuOpts catching duplicate IDs for block devices.
This patch add a new check for duplicate IDs to bdrv_new(), and moves the
existing check that the ID
A name that is taken by an ID can't be taken by a node-name at the same
time. Check that conflicts are correctly detected.
Signed-off-by: Kevin Wolf kw...@redhat.com
---
tests/qemu-iotests/087 | 52 ++
tests/qemu-iotests/087.out | 5 +
2 files
Signed-off-by: Fam Zheng f...@redhat.com
---
v2: PRIx32 - SCNx32. (Kevin)
Signed-off-by: Fam Zheng f...@redhat.com
---
block/vmdk.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/block/vmdk.c b/block/vmdk.c
index 938a183..06a1f9f 100644
--- a/block/vmdk.c
+++
The Cortex-A57, like most of the other ARM cores, has a CBAR
register which defines the base address of the per-CPU
peripherals. However it has a 64-bit view as well as a
32-bit view; expand the QOM reset-cbar property from UINT32
to UINT64 so this can be specified, and implement the
32-bit and
Implement the AArch64 SPSR_EL1. For compatibility with how KVM
handles SPSRs and with the architectural mapping between AArch32
and AArch64, we put this in the banked_spsr[] array in the slot
that is used for SVC in AArch32. This means we need to extend the
array from uint32_t to uint64_t, which
From: Beniamino Galvani b.galv...@gmail.com
Convert the interrupt generation logic to the use of level triggered
interrupts.
Signed-off-by: Beniamino Galvani b.galv...@gmail.com
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
Am 17.04.2014 08:20, schrieb Hannes Reinecke:
On 04/16/2014 07:52 PM, Michael S. Tsirkin wrote:
On Wed, Apr 16, 2014 at 07:47:37PM +0200, Andreas Färber wrote:
Am 16.04.2014 19:40, schrieb Michael S. Tsirkin:
On Wed, Apr 16, 2014 at 06:48:08PM +0200, Andreas Färber wrote:
Am 16.04.2014 18:32,
Add the AArch64 ELR_EL1 register.
Note that this does not live in env-cp15: for KVM migration
compatibility we need to migrate it separately rather than
as part of the system registers, because the KVM-to-userspace
interface puts it in the struct kvm_regs rather than making
them visible via the
On 04/17/2014 01:29 AM, Kevin Wolf wrote:
Okay, now I have a better reason than Meh, I don't like it (which
is always a very bad reason, of course), being the following: As
mirror_run() is actually made for mirroring from an active block
device, some sectors may be marked dirty during the
From: Beniamino Galvani b.galv...@gmail.com
The irq line status must be updated after writes to the INT_CTL and
INT_STA registers.
Signed-off-by: Beniamino Galvani b.galv...@gmail.com
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
Message-id:
On 04/17/2014 05:53 AM, Kevin Wolf wrote:
This patch adds an errp parameter to bdrv_new() and updates all its
callers. The next patch will make use of this in order to check for
duplicate IDs. Most of the callers know that their ID is fine, so they
can simply assert that there is no error.
On 04/16/2014 09:40 AM, Andy Lutomirski wrote:
USB has always been off by default, at least for the boards I'm familiar
with, due to the USB emulation's non-trivial CPU use.
There's no such thing as a Q35 board without USB in the physical world.
Can't stop us from making a virtual one, of
On 04/17/2014 04:43 AM, Fam Zheng wrote:
Signed-off-by: Fam Zheng f...@redhat.com
---
v2: PRIx32 - SCNx32. (Kevin)
Signed-off-by: Fam Zheng f...@redhat.com
---
+++ b/block/vmdk.c
@@ -262,7 +262,7 @@ static uint32_t vmdk_read_cid(BlockDriverState *bs, int
parent)
p_name =
From: Peter Crosthwaite peter.crosthwa...@xilinx.com
Near total rewrite of this device model. It is stylistically
obsolete, has numerous coverity fails and is not up to date with latest
Xilinx documentation. Fix.
The registers are flattened into a single array. This greatly simplifies
the MMIO
The AArch64 implementation of the set_pc method needs to be updated to
handle the possibility that the CPU is in AArch32 mode; otherwise there
are weird crashes when doing interprocessing in system emulation mode
when an interrupt occurs and we fail to resynchronize the 32-bit PC
with the TB we
On Wed, 16 Apr 2014 17:42:22 +0100
Peter Maydell peter.mayd...@linaro.org wrote:
On 16 April 2014 17:34, Michael S. Tsirkin m...@redhat.com wrote:
so it looks like virtio is currently compiled per-target.
So why isn't it reasonable to keep it per-target for
purpose of this enhancement?
On Thu, 17 Apr 2014 11:00:26 +0300
Michael S. Tsirkin m...@redhat.com wrote:
On Thu, Apr 17, 2014 at 08:54:12AM +0200, Greg Kurz wrote:
On Wed, 16 Apr 2014 20:32:07 +0300
Michael S. Tsirkin m...@redhat.com wrote:
On Wed, Apr 16, 2014 at 05:42:22PM +0100, Peter Maydell wrote:
On 16
All the AArch32 ID registers are visible from AArch64
(in addition to the AArch64-specific ID_AA64* registers).
Signed-off-by: Peter Maydell peter.mayd...@linaro.org
Reviewed-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
target-arm/helper.c | 73
From: Alex Bennée alex.ben...@linaro.org
The test for the U bit was incorrectly inverted in the scalar case of SQXTUN.
This doesn't affect the vector case as the U bit is used to select XTN(2).
Reported-by: Hao Liu hao@arm.com
Signed-off-by: Alex Bennée alex.ben...@linaro.org
Reviewed-by:
Am 17.04.2014 um 14:11 hat Eric Blake geschrieben:
On 04/17/2014 05:53 AM, Kevin Wolf wrote:
This patch adds an errp parameter to bdrv_new() and updates all its
callers. The next patch will make use of this in order to check for
duplicate IDs. Most of the callers know that their ID is fine,
On Mon, 14 Apr 2014 19:22:11 -0700
Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
For consistency with other devices and completeness of system device
tree.
Signed-off-by: Peter Crosthwaite peter.crosthwa...@xilinx.com
---
hw/arm/xilinx_zynq.c | 19 ++-
1 file
On Thu, 17 Apr 2014 14:17:37 +0800
Hu Tao hu...@cn.fujitsu.com wrote:
max ram shouldn't exceed unused memory range above 4g
(UINT64_MAX - 0x1 - above_4g_mem_size), that is:
max_ram is not amount of RAM after initial RAM, but rather
RAM limit including initial RAM.
There should be
From: Gonglei arei.gong...@huawei.com
According to the PS/2 Mouse/Keyboard Protocol, the keyboard outupt buffer size
is 16 bytes. And the PS2_QUEUE_SIZE 256 was introduced in Qemu from the very
beginning.
When I started a redhat5.6 32bit guest, meanwhile tapped the keyboard as
quickly as
On Thu, Apr 17, 2014 at 10:50 PM, Igor Mammedov imamm...@redhat.com wrote:
On Mon, 14 Apr 2014 19:22:11 -0700
Peter Crosthwaite peter.crosthwa...@xilinx.com wrote:
For consistency with other devices and completeness of system device
tree.
Signed-off-by: Peter Crosthwaite
On 04/17/2014 06:02 AM, Peter Maydell wrote:
On 2 April 2014 13:47, Peter Maydell peter.mayd...@linaro.org wrote:
On 2 April 2014 13:11, Peter Crosthwaite peter.crosthwa...@xilinx.com
wrote:
Like others, I have been carrying this change locally. Good to see it up!
Why are you all booting
This makes adding more message types cleaner.
Signed-off-by: Huw Davies h...@codeweavers.com
---
linux-user/syscall.c | 51 +--
1 file changed, 33 insertions(+), 18 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index
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