[Qemu-devel] [PATCH] target/ppc: rewrite f[n]m[add, sub] using float64_muladd

Use the softfloat api for fused multiply-add. As we are using the fused multiply-add, the intermediate result for setting VXISI is not available. Signed-off-by: Nikunj A Dadhania --- target/ppc/fpu_helper.c | 201 +++- 1

Re: [Qemu-devel] [PATCH v2] intel_iommu: check misordered init when realize

On 03/01/2017 06:14 AM, Jason Wang wrote: On 2017年03月01日 11:23, Michael S. Tsirkin wrote: On Wed, Mar 01, 2017 at 10:36:35AM +0800, Peter Xu wrote: On Tue, Feb 28, 2017 at 04:42:25PM +0200, Marcel Apfelbaum wrote: On 02/24/2017 06:29 AM, Peter Xu wrote: Intel vIOMMU devices are created

Re: [Qemu-devel] [RFC Design Doc v3] Enable Shared Virtual Memory feature in pass-through scenarios

> From: Konrad Rzeszutek Wilk [mailto:konrad.w...@oracle.com] > Sent: Wednesday, March 01, 2017 6:07 AM > > On Wed, Nov 30, 2016 at 08:49:24AM +, Liu, Yi L wrote: > > What's changed from v2: > > a) Detailed feature description > > b) refine description in "Address translation in virtual SVM"

Re: [Qemu-devel] [PATCH v2 24/24] keyval: Support lists

Eric Blake writes: > On 02/28/2017 03:27 PM, Markus Armbruster wrote: >> Additionally permit non-negative integers as key components. A >> dictionary's keys must either be all integers or none. If all keys >> are integers, convert the dictionary to a list. The set of keys

[Qemu-devel] [PATCH qemu v2] exec, kvm, target-ppc: Move getrampagesize() to common code

getrampagesize() returns the largest supported page size and mainly used to know if huge pages are enabled. However is implemented in target-ppc/kvm.c and not available in TCG or other architectures. This renames and moves gethugepagesize() to mmap-alloc.c where fd-based analog of it is already

[Qemu-devel] [PULL 50/50] Add PowerPC 32-bit guest memory dump support

From: Mike Nawrocki This patch extends support for the `dump-guest-memory` command to the 32-bit PowerPC architecture. It relies on the assumption that a 64-bit guest will not dump a 32-bit core file (and vice versa). [dwg: I suspect this patch won't cover all

[Qemu-devel] [PULL 41/50] ppc/xics: use the QOM interface to grab an ICP

From: Cédric Le Goater Also introduce a xics_icp_get() helper to simplify the changes. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/xics.c | 32 ++--

Re: [Qemu-devel] [RFC PATCH v2 08/12] spapr: Only setup HTP if necessary.

On Tue, 2017-02-28 at 14:19 +1100, David Gibson wrote: > On Tue, Feb 28, 2017 at 01:25:17PM +1100, Suraj Jitindar Singh wrote: > > > > On Tue, 2017-02-28 at 11:28 +1100, David Gibson wrote: > > > > > > s/HTP/HPT/ in subject line. > > > > > > > > > On Thu, Feb 23, 2017 at 05:00:01PM +1100, Sam

[Qemu-devel] [PULL 36/50] ppc/xics: remove the XICS list of ICS

From: Cédric Le Goater This is not used anymore. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Signed-off-by: David Gibson --- hw/intc/xics.c| 8 hw/ppc/spapr.c| 1 -

[Qemu-devel] [PULL 35/50] ppc/xics: register the reset handler of ICS objects

From: Cédric Le Goater The reset of the ICS objects is currently handled by XICS but this can be done for each individual ICS. This also reduces the use of the XICS list of ICS. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson

[Qemu-devel] [PULL 49/50] ppc/xics: rename 'ICPState *' variables to 'icp'

From: Cédric Le Goater 'ICPState *' variables are currently named 'ss'. This is confusing, so let's give them an appropriate name: 'icp'. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/xics.c | 154

[Qemu-devel] [PULL 37/50] ppc/xics: extend the QOM interface to handle ICPs

From: Cédric Le Goater Let's add two new handlers for ICPs. One is to get an ICP object from a server number and a second is to resend the irqs when needed. The icp_resend() handler is a temporary workaround needed by the ics-simple post_load() handler. It will be removed when

[Qemu-devel] [PULL 43/50] ppc/xics: register the reset handler of ICP objects

From: Cédric Le Goater The reset of the ICP objects is currently handled by XICS but this can be done for each individual ICP. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/xics.c | 18 --

[Qemu-devel] [PULL 48/50] ppc/xics: move InterruptStatsProvider to the sPAPR machine

From: Cédric Le Goater It provides a better monitor output of the ICP and ICS objects, else the objects are printed out of order. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/xics.c| 20

[Qemu-devel] [PULL 40/50] ppc/xics: move the cpu_setup() handler under the ICPState class

From: Cédric Le Goater The cpu_setup() handler is currently under the XICSState class but it really belongs under ICPState as it is setting up an individual vCPU. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 46/50] ppc/xics: remove the XICSState classes

From: Cédric Le Goater The XICSState classes are not used anymore. They have now been fully deprecated by the XICSFabric QOM interface. Do the cleanups. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson --- hw/intc/xics.c

[Qemu-devel] [PULL 27/50] ppc/xics: remove set_nr_servers() handler from XICSStateClass

From: Cédric Le Goater Today, the ICP (Interrupt Controller Presenter) objects are created by the 'nr_servers' property handler of the XICS object and a class handler. They are realized in the XICS object realize routine. Let's simplify the process by creating the ICP objects

[Qemu-devel] [PULL 26/50] ppc/xics: remove set_nr_irqs() handler from XICSStateClass

From: Cédric Le Goater Today, the ICS (Interrupt Controller Source) object is created and realized by the init and realize routines of the XICS object, but some of the parameters are only known at the machine level. These parameters are passed from the sPAPR machine to the ICS

[Qemu-devel] [PULL 47/50] ppc/xics: move ics-simple post_load under the machine

From: Cédric Le Goater The ICS object uses a post_load() handler which is implicitly relying on the fact that the internal state of the ICS and ICP objects has been restored but this is not guaranteed. So, let's move the code under the post_load() handler of the machine where we

[Qemu-devel] [PULL 38/50] ppc/xics: move kernel_xics_fd out of KVMXICSState

From: Cédric Le Goater The kernel ICP file descriptor is the only reason behind the KVMXICSState class and it's in the way of more cleanups. Let's make it a static for the moment and move forward. If this is problem, we could use an attribute under the sPAPR machine later on.

[Qemu-devel] [PULL 31/50] ppc/xics: use the QOM interface under the sPAPR machine

From: Cédric Le Goater Add 'ics_get' and 'ics_resend' handlers to the sPAPR machine. These are relatively simple for a single ICS. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Signed-off-by: David Gibson

[Qemu-devel] [PULL 45/50] ppc/xics: export the XICS init routines

From: Cédric Le Goater There is nothing left related to the XICS object in the realize functions of the KVMXICSState and XICSState class. So adapt the interfaces to call these routines directly from the sPAPR machine init sequence. Signed-off-by: Cédric Le Goater

[Qemu-devel] [PULL 12/50] target/ppc: Eliminate htab_base and htab_mask variables

CPUPPCState includes fields htab_base and htab_mask which store the base address (GPA) and size (as a mask) of the guest's hashed page table (HPT). These are set when the SDR1 register is updated. Keeping these in sync with the SDR1 is actually a little bit fiddly, and probably not useful for

[Qemu-devel] [PULL 22/50] target/ppc: add ov32 flag in divide operations

From: Nikunj A Dadhania Add helper_div_compute_ov() in the int_helper for updating the overflow flags. For Divide Word: SO, OV, and OV32 bits reflects overflow of the 32-bit result For Divide DoubleWord: SO, OV, and OV32 bits reflects overflow of the 64-bit result

[Qemu-devel] [PULL 42/50] ppc/xics: simplify spapr_dt_xics() interface

From: Cédric Le Goater spapr_dt_xics() only needs the number of servers to build the device tree nodes. Let's change the routine interface to reflect that. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 39/50] ppc/xics: simplify the cpu_setup() handler

From: Cédric Le Goater The cpu_setup() handler currently takes a 'XICSState *' argument to grab the kernel ICP file descriptor. This interface can be simplified by using the 'xics' backlink of the ICP object. This change is also required by subsequent patches which makes use of

[Qemu-devel] [PULL 13/50] target/ppc: Manage external HPT via virtual hypervisor

The pseries machine type implements the behaviour of a PAPR compliant hypervisor, without actually executing such a hypervisor on the virtual CPU. To do this we need some hooks in the CPU code to make hypervisor facilities get redirected to the machine instead of emulated internally. For

[Qemu-devel] [PULL 28/50] ppc/xics: store the ICS object under the sPAPR machine

From: Cédric Le Goater A list of ICS objects was introduced under the XICS object for the PowerNV machine but, for the sPAPR machine, it brings extra complexity as there is only a single ICS. To simplify the code, let's add the ICS pointer under the sPAPR machine and try to reduce

[Qemu-devel] [PULL 29/50] ppc/xics: add an InterruptStatsProvider interface to ICS and ICP objects

From: Cédric Le Goater This is, again, to reduce the use of the list of ICS objects. Let's make each individual ICS and ICP object an InterruptStatsProvider and remove this same interface from XICSState. The InterruptStatsProvider will be moved at the machine level after the XICS

[Qemu-devel] [PULL 44/50] ppc/xics: move the ICP array under the sPAPR machine

From: Cédric Le Goater This is the last step to remove the XICSState abstraction and have the machine hold all the objects related to interrupts : ICSs and ICPs. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson ---

[Qemu-devel] [PULL 25/50] xics: XICS should not be a SysBusDevice

Currently xics - the component of the IBM POWER interrupt controller representing the overall interrupt fabric / architecture is represented as a descendent of SysBusDevice. However, this is not really correct - the xics presents nothing in MMIO space so it should be an "unattached" device in the

[Qemu-devel] [PULL 24/50] spapr/pci: populate PCI DT in reverse order

From: Greg Kurz Since commit 1d2d974244c6 "spapr_pci: enumerate and add PCI device tree", QEMU populates the PCI device tree in the opposite order compared to SLOF. Before 1d2d974244c6: Populating /pci@8002000 00 (D) : 1af4 1000

[Qemu-devel] [PULL 21/50] target/ppc: add ov32 flag for multiply low insns

From: Nikunj A Dadhania For Multiply Word: SO, OV, and OV32 bits reflects overflow of the 32-bit result For Multiply DoubleWord: SO, OV, and OV32 bits reflects overflow of the 64-bit result Signed-off-by: Nikunj A Dadhania Reviewed-by:

[Qemu-devel] [PULL 33/50] ppc/xics: use the QOM interface to resend irqs

From: Cédric Le Goater Also change the ICPState 'xics' backlink to be a XICSFabric, this removes the need of using qdev_get_machine() to get the QOM interface in some of the routines. Signed-off-by: Cédric Le Goater Signed-off-by: David Gibson

[Qemu-devel] [PULL 34/50] ppc/xics: remove xics_find_source()

From: Cédric Le Goater It is not used anymore now that we have the QOM interface for XICS. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Signed-off-by: David Gibson --- hw/intc/xics.c

[Qemu-devel] [PULL 23/50] target/ppc: add mcrxrx instruction

From: Nikunj A Dadhania mcrxrx: Move to CR from XER Extended Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 23

[Qemu-devel] [PULL 11/50] target/ppc: Cleanup HPTE accessors for 64-bit hash MMU

Accesses to the hashed page table (HPT) are complicated by the fact that the HPT could be in one of three places: 1) Within guest memory - when we're emulating a full guest CPU at the hardware level (e.g. powernv, mac99, g3beige) 2) Within qemu, but outside guest memory - when we're

[Qemu-devel] [PULL 32/50] ppc/xics: use the QOM interface to get irqs

From: Cédric Le Goater Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson Signed-off-by: David Gibson --- hw/intc/xics.c | 5 +++-- hw/ppc/spapr_events.c | 6 +++---

[Qemu-devel] [PULL 15/50] target/ppc: Correct SDR1 masking

SDR_64_HTABORG, which indicates the bits of the SDR1 register to use for the base of a 64-bit machine's hashed page table (HPT) isn't correct. It includes the top 46 bits of the register, but in fact the top 4 bits must be zero (according to the ISA v2.07). No actual implementation has supported

[Qemu-devel] [PULL 07/50] target/ppc: Fix KVM-HV HPTE accessors

When a 'pseries' guest is running with KVM-HV, the guest's hashed page table (HPT) is stored within the host kernel, so it is not directly accessible to qemu. Most of the time, qemu doesn't need to access it: we're using the hardware MMU, and KVM itself implements the guest hypercalls for

[Qemu-devel] [PULL 30/50] ppc/xics: introduce a XICSFabric QOM interface to handle ICSs

From: Cédric Le Goater This interface provides two simple handlers. One is to get an ICS (Interrupt Source Controller) object from an irq number and a second to resend the irqs when needed. Signed-off-by: Cédric Le Goater Reviewed-by: David Gibson

[Qemu-devel] [PULL 19/50] target/ppc: update overflow flags for add/sub

From: Nikunj A Dadhania * SO and OV reflects overflow of the 64-bit result in 64-bit mode and overflow of the low-order 32-bit result in 32-bit mode * OV32 reflects overflow of the low-order 32-bit independent of the mode Signed-off-by: Nikunj A Dadhania

[Qemu-devel] [PULL 16/50] target/ppc: support for 32-bit carry and overflow

From: Nikunj A Dadhania POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags and corresponding defines. Moreover, CA32 is updated when CA is updated and OV32 is updated when OV is updated. Arithmetic instructions: * Addition and Substractions:

[Qemu-devel] [PULL 20/50] target/ppc: use tcg ops for neg instruction

From: Nikunj A Dadhania Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 5 - 1 file changed, 4 insertions(+), 1

[Qemu-devel] [PULL 17/50] target/ppc: update ca32 in arithmetic add

From: Nikunj A Dadhania Adds routine to compute ca32 - gen_op_arith_compute_ca32 For 64-bit mode use the compute ca32 routine. While for 32-bit mode, CA and CA32 will have same value. Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard

[Qemu-devel] [PULL 14/50] target/ppc: Remove the function ppc_hash64_set_sdr1()

From: Suraj Jitindar Singh The function ppc_hash64_set_sdr1 basically checked the htabsize and set an error if it was too big, otherwise it just stored the value in SPR_SDR1. Given that the only function which calls ppc_hash64_set_sdr1() is ppc_store_sdr1(), why not

[Qemu-devel] [PULL 03/50] PCI: add missing classes in pci_ids.h to build device tree

From: Laurent Vivier To allow QEMU to add PCI entries in device tree, we must have a more exhaustive list of PCI class IDs. This patch synchronizes as much as possible with pci_ids.h and add some missing IDs from SLOF. Signed-off-by: Laurent Vivier

[Qemu-devel] [PULL 04/50] spapr: generate DT node names

From: Laurent Vivier When DT node names for PCI devices are generated by SLOF, they are generated according to the type of the device (for instance, ethernet for virtio-net-pci device). Node name for hotplugged devices is generated by QEMU. This patch adds the mechanic to

[Qemu-devel] [PULL 09/50] target/ppc: Merge cpu_ppc_set_vhyp() with cpu_ppc_set_papr()

cpu_ppc_set_papr() sets up various aspects of CPU state for use with PAPR paravirtualized guests. However, it doesn't set the virtual hypervisor, so callers must also call cpu_ppc_set_vhyp() so that PAPR hypercalls are handled properly. This is a bit silly, so fold setting the virtual hypervisor

[Qemu-devel] [PULL 08/50] pseries: Minor cleanups to HPT management hypercalls

* Standardize on 'ptex' instead of 'pte_index' for HPTE index variables for consistency and brevity * Avoid variables named 'index'; shadowing index(3) from libc can lead to surprising bugs if the variable is removed, because compiler errors might not appear for remaining references *

[Qemu-devel] [PULL 18/50] target/ppc: update ca32 in arithmetic substract

From: Nikunj A Dadhania Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 11 ++- 1 file changed, 10

[Qemu-devel] [PULL 00/50] ppc-for-2.9 queue 20170301

The following changes since commit e7c83a885f865128ae3cf1946f8cb538b63cbfba: vhost-user: delay vhost_user_stop (2017-02-28 19:11:15 +) are available in the git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.9-20170301 for you to fetch changes up to

[Qemu-devel] [PULL 10/50] target/ppc: SDR1 is a hypervisor resource

At present the SDR1 register - the base of the system's hashed page table (HPT) - is represented as an SPR with supervisor read and write permission. However, on CPUs which have a hypervisor mode, the SDR1 is a hypervisor only resource. Change the permission checking on the SPR to reflect this.

[Qemu-devel] [PULL 06/50] sysemu: support up to 1024 vCPUs

From: Greg Kurz Some systems can already provide more than 255 hardware threads. Bumping the QEMU limit to 1024 seems reasonable: - it has no visible overhead in top; - the limit itself has no effect on hot paths. Cc: Greg Kurz

[Qemu-devel] [PULL 01/50] target/ppc: move cpu_[read, write]_xer to cpu.c

From: Nikunj A Dadhania Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/Makefile.objs | 1 + target/ppc/cpu.c | 36

[Qemu-devel] [PULL 02/50] target/ppc: optimize gen_write_xer()

From: Nikunj A Dadhania Signed-off-by: Nikunj A Dadhania Reviewed-by: Richard Henderson Signed-off-by: David Gibson --- target/ppc/translate.c | 9 +++-- 1 file changed, 3 insertions(+),

[Qemu-devel] [PULL 05/50] target/ppc: introduce helper_update_ov_legacy

From: Nikunj A Dadhania Removes duplicate code and will be useful for consolidating flags Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/int_helper.c | 34

Re: [Qemu-devel] [PATCH v2 15/21] char-udp: flush as much buffer as possible

On 02/27/2017 10:41 AM, Marc-André Lureau wrote: Instead of flushing the buffer byte by byte, call qemu_chr_be_write() with as much byte possible accepted by the front-end. Factor out buffer flushing in a common function udp_chr_flush_buffer(). Signed-off-by: Marc-André Lureau

Re: [Qemu-devel] [PATCH v2 10/21] char: useless NULL check

On 02/27/2017 10:41 AM, Marc-André Lureau wrote: g_strdup(NULL) returns NULL already. Signed-off-by: Marc-André Lureau Reviewed-by: Philippe Mathieu-Daudé --- chardev/char.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Qemu-devel] [PATCH v2] intel_iommu: check misordered init when realize

On 2017年03月01日 11:23, Michael S. Tsirkin wrote: On Wed, Mar 01, 2017 at 10:36:35AM +0800, Peter Xu wrote: On Tue, Feb 28, 2017 at 04:42:25PM +0200, Marcel Apfelbaum wrote: On 02/24/2017 06:29 AM, Peter Xu wrote: Intel vIOMMU devices are created with "-device" parameter, while here actually

[Qemu-devel] [PATCH] virtio: unbreak virtio-pci with IOMMU after caching ring translations

Commit c611c76417f5 ("virtio: add MemoryListener to cache ring translations") registers a memory listener to dma_as. This may not work when IOMMU is enabled: dma_as(bus_master_as) were initialized in pcibus_machine_done() after virtio_realize(). This will cause a segfault. Fixing this by using

Re: [Qemu-devel] [PATCH qemu 1/2] exec, kvm, target-ppc: Move getrampagesize() to common code

On Wed, Mar 01, 2017 at 12:06:14PM +1100, David Gibson wrote: > On Tue, Feb 28, 2017 at 07:12:53PM +1100, Alexey Kardashevskiy wrote: > > On 10/02/17 11:41, David Gibson wrote: > > > On Thu, Feb 09, 2017 at 12:48:19PM +0100, Paolo Bonzini wrote: > > >> > > >> > > >> On 09/02/2017 06:43, Alexey

Re: [Qemu-devel] [PATCH] spapr_pci: allow control of BAR alignment through SLOF

On Tue, Feb 28, 2017 at 06:56:47PM -0600, Michael Roth wrote: > In certain cases, such as PCI-passthrough with VFIO, we cannot offload > MMIO accesses to KVM unless the BAR alignment matches the host. This > patch, in conjunction with a separately submitted patch for SLOF > which allows for

Re: [Qemu-devel] [PATCH v3 2/6] replication: add shared-disk and shared-disk-id options

On 2017/2/28 1:10, Stefan Hajnoczi wrote: On Fri, Jan 20, 2017 at 11:47:56AM +0800, zhanghailiang wrote: @@ -119,12 +136,31 @@ static int replication_open(BlockDriverState *bs, QDict *options, "The option mode's value should be primary or secondary"); goto fail;

Re: [Qemu-devel] [PATCH v2] intel_iommu: check misordered init when realize

On Wed, Mar 01, 2017 at 10:36:35AM +0800, Peter Xu wrote: > On Tue, Feb 28, 2017 at 04:42:25PM +0200, Marcel Apfelbaum wrote: > > On 02/24/2017 06:29 AM, Peter Xu wrote: > > >Intel vIOMMU devices are created with "-device" parameter, while here > > >actually we need to make sure the dmar device be

Re: [Qemu-devel] [PATCH v2] memory: Introduce DEVICE_HOST_ENDIAN for ram device

on 2017/3/1 8:35, David Gibson wrote: On Tue, Feb 28, 2017 at 06:12:56PM +0800, Yongji Xie wrote: on 2017/2/28 8:41, David Gibson wrote: On Mon, Feb 27, 2017 at 12:52:44PM +0800, Yongji Xie wrote: At the moment ram device's memory regions are DEVICE_NATIVE_ENDIAN. It's incorrect. This

Re: [Qemu-devel] [PATCH v3 1/6] docs/block-replication: Add description for shared-disk case

On 2017/2/28 0:46, Stefan Hajnoczi wrote: On Fri, Jan 20, 2017 at 11:47:55AM +0800, zhanghailiang wrote: +Secondary: + -drive if=none,driver=qcow2,file.filename=/mnt/ramfs/hidden_disk.img,id=hidden_disk0,\ +backing.driver=raw,backing.file.filename=1.raw \ + -drive

Re: [Qemu-devel] [PATCH v2 1/3] block: implement bdrv_snapshot_goto for blkreplay

On 02/28/2017 04:55 AM, Pavel Dovgalyuk wrote: [meta-comment] > This patch enables making snapshots with blkreplay used in > block devices. > This function is required to make bdrv_snapshot_goto without > calling .bdrv_open which is not implemented. > > v2: updated commit message The v2

Re: [Qemu-devel] [PATCH v2 01/21] char: remove qemu_chr_be_generic_open

On 02/27/2017 07:41 AM, Marc-André Lureau wrote: > The function simply alias and hides the real event function. s/alias/aliases/ > > Signed-off-by: Marc-André Lureau > --- > include/sysemu/char.h | 1 - > chardev/char-pty.c| 2 +- > chardev/char-socket.c |

Re: [Qemu-devel] [PATCH 1/2] makefile: merge GENERATED_HEADERS & GENERATED_SOURCES variables

On 02/28/2017 06:29 AM, Daniel P. Berrange wrote: > The only functional difference between the GENERATED_HEADERS > and GENERATED_SOURCES variables is that 'Makefile' has a > dependancy on GENERATED_HEADERS, causing generated header files s/dependancy/dependency/ > to be created immediatey at the

Re: [Qemu-devel] [PATCH v2] intel_iommu: check misordered init when realize

On Tue, Feb 28, 2017 at 04:42:25PM +0200, Marcel Apfelbaum wrote: > On 02/24/2017 06:29 AM, Peter Xu wrote: > >Intel vIOMMU devices are created with "-device" parameter, while here > >actually we need to make sure the dmar device be created before other > >PCI devices (like vfio-pci) so that we

Re: [Qemu-devel] [PATCH] Add PowerPC 32-bit guest memory dump support

On Tue, Feb 28, 2017 at 08:32:17AM -0500, Mike Nawrocki wrote: > Signed-off-by: Mike Nawrocki > > Sorry, I was only testing against the ppc-softmmu and ppc64-softmmu targets. > I've now validated that this compiles against the following targets: >

Re: [Qemu-devel] [Qemu-ppc] [PATCH] linux-user: fill target sigcontext struct accordingly

On Tue, Feb 28, 2017 at 11:22:54AM +0100, Laurent Vivier wrote: > Le 28/02/2017 à 02:09, David Gibson a écrit : > > On Wed, Feb 01, 2017 at 09:43:57PM +0100, Laurent Vivier wrote: > >> Le 31/01/2017 à 23:05, Jose Ricardo Ziviani a écrit : > >>> A segfault is noticed when an emulated program uses

Re: [Qemu-devel] [Qemu-ppc] [PATCH] spapr/pci: populate PCI DT in reverse order

On Mon, Feb 27, 2017 at 11:20:16PM +0100, Greg Kurz wrote: > David, > > Any chances to have this in 2.9 ? Yes. I've put it in my tree and I'm hoping to send a pull request shortly. Actually, I was hoping to send it yesterday, but hit a bug during testing which I'm now chasing. > > On Wed, 22

Re: [Qemu-devel] using fdt_setprop() to set properties to empty values

On Wed, Mar 01, 2017 at 11:16:02AM +1100, David Gibson wrote: > On Mon, Feb 27, 2017 at 10:11:57AM +, Peter Maydell wrote: > > On 27 February 2017 at 01:05, David Gibson > > wrote: > > > On Fri, Feb 24, 2017 at 10:35:35AM +, Peter Maydell wrote: > > >> On 24

Re: [Qemu-devel] [PATCH qemu 1/2] exec, kvm, target-ppc: Move getrampagesize() to common code

On Tue, Feb 28, 2017 at 07:12:53PM +1100, Alexey Kardashevskiy wrote: > On 10/02/17 11:41, David Gibson wrote: > > On Thu, Feb 09, 2017 at 12:48:19PM +0100, Paolo Bonzini wrote: > >> > >> > >> On 09/02/2017 06:43, Alexey Kardashevskiy wrote: > >>> On 03/01/17 10:34, David Gibson wrote: > On

Re: [Qemu-devel] [PATCH v2] memory: Introduce DEVICE_HOST_ENDIAN for ram device

On Tue, Feb 28, 2017 at 06:12:56PM +0800, Yongji Xie wrote: > on 2017/2/28 8:41, David Gibson wrote: > > > On Mon, Feb 27, 2017 at 12:52:44PM +0800, Yongji Xie wrote: > > > At the moment ram device's memory regions are DEVICE_NATIVE_ENDIAN. It's > > > incorrect. This memory region is backed by a

Re: [Qemu-devel] using fdt_setprop() to set properties to empty values

On Mon, Feb 27, 2017 at 10:11:57AM +, Peter Maydell wrote: > On 27 February 2017 at 01:05, David Gibson > wrote: > > On Fri, Feb 24, 2017 at 10:35:35AM +, Peter Maydell wrote: > >> On 24 February 2017 at 00:16, David Gibson > >>

Re: [Qemu-devel] [RFC 00/13] Live memory snapshot based on userfaultfd

On 2017/3/1 0:14, Andrea Arcangeli wrote: Hello, On Tue, Feb 28, 2017 at 09:48:26AM +0800, Hailiang Zhang wrote: Yes, for current implementing of live snapshot, it supports tcg, but does not support kvm mode, the reason i have mentioned above, if you try to implement it, i think you need to

[Qemu-devel] [Bug 1591611] Re: chroot using qemu-x86_64-static fails on ppc64el

** Changed in: qemu Status: In Progress => Fix Committed ** Changed in: qemu Assignee: Timothy Pearson (kb9vqf) => pranith (bobby-prani) -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

Re: [Qemu-devel] [PATCH 1/2] ide: core: add cleanup function

Hello John, Paolo, 2017-03-01 8:47 GMT+08:00 John Snow : > > > On 02/09/2017 02:04 AM, Li Qiang wrote: > > As the pci ahci can be hotplug and unplug, in the ahci unrealize > > function it should free all the resource once allocated in the > > realized function. This patch adds

[Qemu-devel] [PATCH] spapr_pci: allow control of BAR alignment through SLOF

In certain cases, such as PCI-passthrough with VFIO, we cannot offload MMIO accesses to KVM unless the BAR alignment matches the host. This patch, in conjunction with a separately submitted patch for SLOF which allows for control of this via the device-tree, allows us to set this alignment via

Re: [Qemu-devel] [PATCH 1/2] ide: core: add cleanup function

On 02/09/2017 02:04 AM, Li Qiang wrote: > As the pci ahci can be hotplug and unplug, in the ahci unrealize > function it should free all the resource once allocated in the > realized function. This patch adds two cleanup function. > So, the peculiarities of the current arrangement of QDEV

Re: [Qemu-devel] [PATCH 2/2] ide: ahci: call cleanup function in ahci unit

On 02/28/2017 07:35 PM, John Snow wrote: > > > On 02/09/2017 02:04 AM, Li Qiang wrote: >> This can avoid memory leak when hotunplug the ahci device. >> >> Signed-off-by: Li Qiang >> --- >> hw/ide/ahci.c | 8 >> 1 file changed, 8 insertions(+) >> >> diff --git

Re: [Qemu-devel] [PATCH 2/2] ide: ahci: call cleanup function in ahci unit

On 02/09/2017 02:04 AM, Li Qiang wrote: > This can avoid memory leak when hotunplug the ahci device. > > Signed-off-by: Li Qiang > --- > hw/ide/ahci.c | 8 > 1 file changed, 8 insertions(+) > > diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c > index 3c19bda..56f68a8

Re: [Qemu-devel] [PULL] TCG queued patch

On Tue, Feb 28, 2017 at 4:33 PM, Richard Henderson wrote: > Only one this week. Pranith didn't mention which compiler version, > but I can imagine gcc7 or clang warning of such a thing. > I apologize for missing this information in the patch. The warning was from clang master.

Re: [Qemu-devel] how can i join and start?

On 02/28/2017 03:52 PM, Jyoti Panwar wrote: > how can i started?? coding in this organisation. Here's some useful links: http://wiki.qemu-project.org/Contribute/SubmitAPatch http://wiki.qemu-project.org/BiteSizedTasks My general advice (not just for this list, but any project): subscribe to the

Re: [Qemu-devel] [PATCH v2 00/30] Various memory leak fixes

On 02/27/2017 05:04 AM, Marc-André Lureau wrote: > Hi > > On Tue, Feb 21, 2017 at 6:27 PM Marc-André Lureau < > marcandre.lur...@redhat.com> wrote: > >> After this series removing a few memory leaks, make check with ASAN >> enabled gives a "clean" run with x86_64-softmmu target (there are >>

Re: [Qemu-devel] [PATCH v2 29/30] tests: fix virtio-blk-test leaks

On 02/21/2017 08:14 AM, Marc-André Lureau wrote: > Use qvirtio_pci_device_find_slot() to avoid leaking the non-hp > device. Add assert() to avoid further leaks in the future. > > Use qvirtio_pci_device_free() to correctly free QVirtioPCIDevice. Yep, the hunk I mentioned in 28/30 probably belongs

Re: [Qemu-devel] [PATCH v2 28/30] tests: add specialized device_find function

On 02/21/2017 08:14 AM, Marc-André Lureau wrote: > Allows to specify which slot to look for the device. "Allow[s] to ${verb}" is not idiomatic; it's missing a subject. But "Allows $subject to" (as in "allows someone to" or "allows me to") is wordy, compared to just saying "Allows ${verb}ing".

Re: [Qemu-devel] [PATCH] Adding support for LPD and LPDG instructions

On 02/28/2017 11:01 PM, Eric Bischoff wrote: From: Eric Bischoff LPD = LOAD PAIR DISJOINT Fourth patch --- target/s390x/insn-data.def | 4 ++- target/s390x/translate.c | 63 ++ 2 files changed, 66 insertions(+), 1 deletion(-)

Re: [Qemu-devel] [PATCH v2 17/30] tests: fix tco-test leaks

On 02/21/2017 08:14 AM, Marc-André Lureau wrote: > Spotted by ASAN. > > Signed-off-by: Marc-André Lureau > --- > tests/tco-test.c | 35 +-- > 1 file changed, 21 insertions(+), 14 deletions(-) > Reviewed-by: Eric Blake

Re: [Qemu-devel] [PATCH v2 09/30] tests: fix vhost-user-test leaks

On 02/21/2017 08:14 AM, Marc-André Lureau wrote: > Spotted by ASAN. > > Signed-off-by: Marc-André Lureau > --- > tests/libqos/virtio-pci.h | 2 ++ > tests/libqos/virtio-pci.c | 6 ++ > tests/vhost-user-test.c | 11 +++ > 3 files changed, 15

Re: [Qemu-devel] [PATCH v2 08/30] tests: fix q35-test leaks

On 02/21/2017 08:14 AM, Marc-André Lureau wrote: > Spotted by ASAN. > > Signed-off-by: Marc-André Lureau > --- > tests/q35-test.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/tests/q35-test.c b/tests/q35-test.c > index 763fe3d6ae..e010d781e7 100644 >

Re: [Qemu-devel] [PATCH v2 24/24] keyval: Support lists

On 02/28/2017 03:27 PM, Markus Armbruster wrote: > Additionally permit non-negative integers as key components. A > dictionary's keys must either be all integers or none. If all keys > are integers, convert the dictionary to a list. The set of keys must > be [0,N]. > > +static void

Re: [Qemu-devel] [PATCH 0/2] misc aarch64 fixes for Windows

> From: no-re...@patchew.org [mailto:no-re...@patchew.org] > Sent: Tuesday, 28 February 2017 14:13 > > Hi, > > This series failed build test on s390x host. Please find the details below. [..] > /var/tmp/patchew-tester-tmp-64adnjjr/src/target/arm/helper.c:931:23: > error: ‘pmreg_access_ccntr’

Re: [Qemu-devel] [PATCH 2/2] target/arm: lie more convincingly about memory attributes in PAR_EL1

On 28 February 2017 at 21:58, Andrew Baumann wrote: > On a successful long-descriptor translation, PAR_EL1 bits 56:63 are > expected to report the memory attributes of the page. However, the > page table walker (get_phys_addr()) does not currently retrieve these >

Re: [Qemu-devel] [PATCH v8 1/2] block/vxhs.c: Add support for a new block device type called "vxhs"

On Mon, Feb 27, 2017 at 1:22 AM, Daniel P. Berrange wrote: > On Fri, Feb 24, 2017 at 03:30:21PM -0800, ashish mittal wrote: >> Thanks! >> >> I hope the following is in line with what you suggested - > > Yes, that looks suitable for password auth > Thanks! >> >> We will error

Re: [Qemu-devel] [PULL 0/1] seabios: update to 1.10.2 release

On 28 February 2017 at 21:34, John Snow wrote: > > > On 02/28/2017 01:24 PM, Gerd Hoffmann wrote: >> On Di, 2017-02-28 at 11:48 -0500, John Snow wrote: >>> >>> On 02/28/2017 04:06 AM, Gerd Hoffmann wrote: Hi, Here comes the seabios update for qemu 2.9, the

[Qemu-devel] [PULL 24/24] keyval: Support lists

Additionally permit non-negative integers as key components. A dictionary's keys must either be all integers or none. If all keys are integers, convert the dictionary to a list. The set of keys must be [0,N]. Examples: * list.1=goner,list.0=null,list.1=eins,list.2=zwei is equivalent to JSON

  1   2   3   4   5   6   7   8   >