[Qemu-devel] [PATCH qemu] vfio-pci: Remove unused fields from VFIOMSIXInfo

Signed-off-by: Alexey Kardashevskiy --- hw/vfio/pci.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index c5e168e..06dcf99 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -93,8 +93,6 @@ typedef struct VFIOMSIXInfo { uint16_t entries;

[Qemu-devel] [PATCH] x86/cpu: Enable new SSE/AVX/AVX512 cpu features

Intel IceLake cpu has added new cpu features,AVX512_VBMI2/GFNI/ VAES/VPCLMULQDQ/AVX512_VNNI/AVX512_BITALG. Those new cpu features need expose to guest VM. The bit definition: CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512_VBMI2 CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES

Re: [Qemu-devel] [PATCH] iotests: fix 075 and 078

Dne 22.11.2017 v 01:16 John Snow napsal(a): > Both of these tests are for formats which now stipulate that they are > read-only. Adjust the tests to match. > > Signed-off-by: John Snow > --- > tests/qemu-iotests/075 | 18 +- > tests/qemu-iotests/078 | 14

[Qemu-devel] [PATCH] Remove MemoryRegionSection check code from sparc_cpu_get_phys_page_debug()

This code is preventing the MMU debug code from displaying virtual mappings of IO devices (anything that is not located in the RAM). Before this patch, Qemu would output 0x (-1) as the physical address corresponding to a IO device virtual address. With this patch the intended

[Qemu-devel] [Bug 1733720] Re: raspi2 with multiple CPU's #1

Sorry again, "MPIDR" Gotta learn to type! -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1733720 Title: raspi2 with multiple CPU's #1 Status in QEMU: Invalid Bug description: Greetings, I

[Qemu-devel] [Bug 1733720] Re: raspi2 with multiple CPU's #1

NOT A BUG Reviewed the code and found the problem. asm volatile("mrc p15, 0, %[id], c0, c0, 0 @ read MIDR\n\t" ... I miscopied the code above; MIDR should have been MIPDR ( 5 ) I now get: Linux:armv7l: ~/Downloads/RaspiTest/BareBones >>> ./qemu.sh 0H312ello, kernel World! Sorry about the

[Qemu-devel] [PATCH qemu] vfio: Allow configuration without INTx

On some platforms INTx may not be enabled on a KVM host (one such example is IBM pHyp hypervisor and this is intentional). However the PCI_INTERRUPT_PIN is not 0 so QEMU tries initializing INTx, fails as (!vdev->pdev->irq) in the VFIO's vfio_intx_enable() and this is a fatal error. This adds a

[Qemu-devel] [PATCH qemu] vfio/spapr: Allow fallback to SPAPR TCE IOMMU v1

The vfio_iommu_spapr_tce driver always advertises v1 and v2 IOMMU support, however PR KVM (a special version of KVM designed to work in a paravirtualized system; these days used for nested virtualizaion) only supports the "pseries" platform which does not support v2. Since there is no way to

Re: [Qemu-devel] [PATCH v2 4/7] s390x/pci: rework PCI STORE BLOCK

在 2017/11/22 上午2:07, Pierre Morel 写道: On 21/11/2017 11:42, Cornelia Huck wrote: On Thu, 16 Nov 2017 18:51:52 +0100 Pierre Morel wrote: Enhance the fault detection. Fixup the precedence to check the destination path existance before checking for the source

[Qemu-devel] Why qemu with kvm enabled can boot kernel even if identity page map is not set correctly?

Hi all. Firstly, sorry if it's the wrong place to ask such a question! In the early stages of boot process, kernel need identity mapped page setup when switching gdt [https://github.com/torvalds/linux/blob/ed30b147e1f6e396e70a52dbb6c7d66befedd786/arch/x86/kernel/head_64.S#L133-L137] as code

[Qemu-devel] [Bug 1733720] [NEW] raspi2 with multiple CPU's #1

Public bug reported: Greetings, I am running a small program for raspi2 (from http://wiki.osdev.org/ARM_RaspberryPi_Tutorial_C). This code writes "Hello World", but the output ir repeated 4 times. My thought was that this is emulating a 4 cpu core system. However, when I check the MPIDR

Re: [Qemu-devel] [PATCH 00/12] Add MVME3100 PPC SBC

On 11/21/2017 10:12 PM, David Gibson wrote: ... > I've applied several patches from this series to ppc-for-2.12, others > I've commented on. If you could address the comments and rebase > what's left on ppc-for-2.12, that would be great. Will do. signature.asc Description: OpenPGP digital

Re: [Qemu-devel] [PATCH 03/12] e500: note possible bug with host bridge

On 11/21/2017 09:46 PM, David Gibson wrote: > On Sun, Nov 19, 2017 at 09:24:11PM -0600, Michael Davidsaver wrote: >> Signed-off-by: Michael Davidsaver > > I'm not sure if you're saying you think there is a hardware bug which > we're faithfully emulating, or a software bug.

[Qemu-devel] [PULL 3/3] ppc: fix VTB migration

From: Laurent Vivier Migration of a system under stress (for example, with "stress-ng --numa 2") triggers on the destination some kernel watchdog messages like: NMI watchdog: BUG: soft lockup - CPU#0 stuck for 3489660870s! NMI watchdog: BUG: soft lockup - CPU#1 stuck for

[Qemu-devel] [PULL 2/3] spapr: Implement bug in spapr-vty device to be compatible with PowerVM

The spapr-vty device implements the PAPR defined virtual console, which is also implemented by IBM's proprietary PowerVM hypervisor. PowerVM's implementation has a bug where it inserts an extra \0 after every \r going to the guest. Because of that Linux's guest side driver has a workaround which

[Qemu-devel] [PULL 0/3] ppc-for-2.11 queue 20171122

The following changes since commit a15d835f00dce270fd3194e83d9910f4b5b44ac0: Update version for v2.11.0-rc2 release (2017-11-21 17:50:36 +) are available in the Git repository at: git://github.com/dgibson/qemu.git tags/ppc-for-2.11-20171122 for you to fetch changes up to

[Qemu-devel] [PULL 1/3] hw/ppc/spapr: Fix virtio-scsi bootindex handling for LUNs >= 256

From: Thomas Huth LUNs >= 256 have to be encoded with the so-called "flat space addressing method" for virtio-scsi, where an additional bit has to be set. SLOF already took care of this with the following commit:

Re: [Qemu-devel] [PATCH 08/12] e500: add mpc8540 i2c controller to ccsr

On Sun, Nov 19, 2017 at 09:24:16PM -0600, Michael Davidsaver wrote: > Signed-off-by: Michael Davidsaver You're adding what seems to be a fairly specific device to the general e500 init - this again suggests that it should be split, putting creation of devices under control

Re: [Qemu-devel] [PATCH 09/12] nvram: add AT24Cx i2c eeprom

On Sun, Nov 19, 2017 at 09:24:17PM -0600, Michael Davidsaver wrote: > Signed-off-by: Michael Davidsaver Applied to ppc-for-2.12. > --- > hw/nvram/Makefile.objs | 1 + > hw/nvram/eeprom_at24c.c | 205 > > 2 files

Re: [Qemu-devel] [PATCH 00/12] Add MVME3100 PPC SBC

On Sun, Nov 19, 2017 at 09:24:08PM -0600, Michael Davidsaver wrote: > This series adds simulation of MVME3100 powerpc SBCs, originally from > Motorola, > and now sold by Artesyn[1]. There are two variants differing in CPU > speed and memory size. > > I've been working on this sporadically for

Re: [Qemu-devel] [PATCH 01/12] e500: add board config options

On Sun, Nov 19, 2017 at 09:24:09PM -0600, Michael Davidsaver wrote: > allow board code to skip common NIC and guest image setup > and configure decrementor frequency. > Existing boards unchanged. > > Signed-off-by: Michael Davidsaver So, it's spelled "decrementer". Other

Re: [Qemu-devel] [PATCH 06/12] i2c: add mpc8540 i2c controller

On Sun, Nov 19, 2017 at 09:24:14PM -0600, Michael Davidsaver wrote: > Signed-off-by: Michael Davidsaver I can't speak to the accuracy of the emulation, but it's presumably better than nothing at all. Therefore, applied to ppc-for-2.12. > --- > hw/i2c/Makefile.objs | 1

Re: [Qemu-devel] [PATCH 02/12] e500: consolidate mpc8540 guts with e500-ccsr

On Sun, Nov 19, 2017 at 09:24:10PM -0600, Michael Davidsaver wrote: > Preparation for adding more MPC control > registers. > > Use e500 SVR to enable part specific registers. > Only the mpc8544 reset register at present. > > Expose CCSR as SysBusDevice region to eliminate > e500-ccsr.h. > >

Re: [Qemu-devel] [PATCH 04/12] e500: additional CCSR registers

On Sun, Nov 19, 2017 at 09:24:12PM -0600, Michael Davidsaver wrote: > Add CCSRBAR to allow CCSR region to be relocated. > Guest memory size introspection. > Dummy RAM error controls. > Guest clock introspection. > > Signed-off-by: Michael Davidsaver Looks fine from the

Re: [Qemu-devel] [PATCH 05/12] e500: name openpic and pci host bridge

On Sun, Nov 19, 2017 at 09:24:13PM -0600, Michael Davidsaver wrote: > Signed-off-by: Michael Davidsaver Applied to ppc-for-2.12. > --- > hw/ppc/e500.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c > index

Re: [Qemu-devel] [PATCH 03/12] e500: note possible bug with host bridge

On Sun, Nov 19, 2017 at 09:24:11PM -0600, Michael Davidsaver wrote: > Signed-off-by: Michael Davidsaver I'm not sure if you're saying you think there is a hardware bug which we're faithfully emulating, or a software bug. > --- > hw/pci-host/ppce500.c | 3 +++ > 1 file

Re: [Qemu-devel] [PATCH 10/12] timer: add ds1375 RTC

On Sun, Nov 19, 2017 at 09:24:18PM -0600, Michael Davidsaver wrote: > only basic functionality implemented (read time and sram). > no set time or alarms. > > Signed-off-by: Michael Davidsaver I know there about a zillion different Dallas/Maxim sram/rtc chips, many of

Re: [Qemu-devel] [ANNOUNCE] QEMU 2.11.0-rc2 is now available

Quoting Christian Borntraeger (2017-11-21 15:38:32) > forgot to cc qemu-devel > > On 11/21/2017 10:37 PM, Christian Borntraeger wrote: > > a quick heads up . Rc2 now triggers > > +qemu-img: block/block-backend.c:2088: blk_root_drained_end: Assertion > > `blk->quiesce_counter' failed. > > for

Re: [Qemu-devel] [PATCH for-2.12 v3 2/3] spapr/rtas: fix reboot of a a SMP TCG guest

On Mon, Nov 20, 2017 at 11:03:46AM +0100, Cédric Le Goater wrote: > Just like for hot unplug CPUs, when a guest is rebooted, the secondary > CPUs can be awaken by the decrementer and start entering SLOF at the > same time the boot CPU is. > > To be safe, let's disable on the secondaries all the

Re: [Qemu-devel] [PATCH for-2.12 v3 1/3] spapr/rtas: disable the decrementer interrupt when a CPU is unplugged

On Mon, Nov 20, 2017 at 11:03:45AM +0100, Cédric Le Goater wrote: > When a CPU is stopped with the 'stop-self' RTAS call, its state > 'halted' is switched to 1 and, in this case, the MSR is not taken into > account anymore in the cpu_has_work() routine. Only the pending > hardware interrupts are

[Qemu-devel] [PATCH v4 3/4] hw/block: Use errp directly rather than local_err

Cc: John Snow Cc: Kevin Wolf Cc: Max Reitz Cc: Keith Busch Cc: Stefan Hajnoczi Cc: "Michael S. Tsirkin" Cc: Paolo Bonzini Cc: Gerd Hoffmann

[Qemu-devel] [PATCH v4 4/4] dev-storage: Fix the unusual function name

The function name of usb_msd_{realize,unrealize}_*, usb_msd_class_initfn_* are unusual. Rename it to usb_msd_*_{realize,unrealize}, usb_msd_class_*_initfn. Cc: Gerd Hoffmann Signed-off-by: Mao Zhongyi Reviewed-by: Philippe Mathieu-Daudé

[Qemu-devel] [PATCH v4 2/4] hw/block: Fix the return type

When the function no success value to transmit, it usually make the function return void. It has turned out not to be a success, because it means that the extra local_err variable and error_propagate() will be needed. It leads to cumbersome code, therefore, transmit success/ failure in the return

[Qemu-devel] [PATCH v4 0/4] Convert to realize and improve error handling

This series mainly implements the conversions of ide, floppy and nvme device to realize. Add some error handling messages and remove the local variable local_err, use errp to propagate the error directly. Also fix the unusual function name. v4: -rebased it on top of block-next branch v3:

[Qemu-devel] [PATCH v4 1/4] hw/block/nvme: Convert to realize

Convert nvme_init() to realize and rename it to nvme_realize(). Cc: John Snow Cc: Keith Busch Cc: Kevin Wolf Cc: Max Reitz Cc: Markus Armbruster Signed-off-by: Mao Zhongyi

Re: [Qemu-devel] [PATCH v5 1/4] vhost-user: add new vhost user messages to support virtio config space

> -Original Message- > From: Michael S. Tsirkin [mailto:m...@redhat.com] > Sent: Tuesday, November 21, 2017 4:45 AM > To: Stefan Hajnoczi > Cc: Liu, Changpeng ; qemu-devel@nongnu.org; > pbonz...@redhat.com; marcandre.lur...@redhat.com;

Re: [Qemu-devel] [PATCH v5 1/4] vhost-user: add new vhost user messages to support virtio config space

> -Original Message- > From: Stefan Hajnoczi [mailto:stefa...@gmail.com] > Sent: Tuesday, November 21, 2017 12:27 AM > To: Liu, Changpeng > Cc: qemu-devel@nongnu.org; pbonz...@redhat.com; m...@redhat.com; > marcandre.lur...@redhat.com; fel...@nutanix.com;

Re: [Qemu-devel] [PATCH qemu] fdc: Exit if ISA controller does not support DMA

On 07/11/17 11:58, John Snow wrote: > > > On 10/26/2017 02:46 AM, Alexey Kardashevskiy wrote: >> A "powernv" machine type defines an ISA bus but it does not add any DMA >> controller to it so it is possible to hit assert(fdctrl->dma) by >> adding "-machine powernv -device isa-fdc". >> >> This

Re: [Qemu-devel] [PATCH v5 1/4] vhost-user: add new vhost user messages to support virtio config space

> -Original Message- > From: Paolo Bonzini [mailto:pbonz...@redhat.com] > Sent: Tuesday, November 21, 2017 8:16 AM > To: Michael S. Tsirkin ; Stefan Hajnoczi > Cc: Liu, Changpeng ; qemu-devel@nongnu.org; >

Re: [Qemu-devel] [PATCH v3 0/6] Convert to realize and improve error handling

Hi, Kevin On 11/10/2017 10:25 PM, Kevin Wolf wrote: Am 19.09.2017 um 01:59 hat John Snow geschrieben: On 09/18/2017 10:05 AM, Mao Zhongyi wrote: This series mainly implements the conversions of ide, floppy and nvme device to realize. Add some error handling messages and remove the local

Re: [Qemu-devel] [PATCH] iotests: fix 075 and 078

On 11/21/2017 06:16 PM, John Snow wrote: > Both of these tests are for formats which now stipulate that they are > read-only. Adjust the tests to match. > > Signed-off-by: John Snow > --- > tests/qemu-iotests/075 | 18 +- > tests/qemu-iotests/078 | 14

Re: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations

Hi, This series failed build test on s390x host. Please find the details below. Subject: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Type: series Message-id: 20171121212534.5177-1-richard.hender...@linaro.org === TEST SCRIPT BEGIN === #!/bin/bash # Testing script will be

[Qemu-devel] [PATCH] iotests: fix 075 and 078

Both of these tests are for formats which now stipulate that they are read-only. Adjust the tests to match. Signed-off-by: John Snow --- tests/qemu-iotests/075 | 18 +- tests/qemu-iotests/078 | 14 +++--- 2 files changed, 16 insertions(+), 16

Re: [Qemu-devel] [Qemu-block] segfault in parallel blockjobs (iotest 30)

CC Jeff Cody ... who may or may not be preoccupied with Thanksgiving travel now. Convenient URL for reading past replies: https://lists.nongnu.org/archive/html/qemu-devel/2017-11/msg03844.html On 11/21/2017 10:31 AM, Alberto Garcia wrote: > On Tue 21 Nov 2017 04:18:13 PM CET, Anton Nefedov

Re: [Qemu-devel] [PATCH for-2.12 0/4] qmp dirty bitmap API

On 11/21/2017 12:23 PM, Kevin Wolf wrote: > Am 17.11.2017 um 22:35 hat John Snow geschrieben: > usage is like this: > > 1. we have dirty bitmap bitmap0 for incremental backup. > > 2. prepare image fleecing (create temporary image with backing=our_disk) > 3. in qmp

[Qemu-devel] qemu-iotest 059 vmdk failure

The last sub-test in 059, which uses an AFL fuzzer image to test for how a large L1 table of a specific size is handled has a slight regression. Previously, QEMU expects -EFBIG to come out the vmdk_open call. Now, we get -EINVAL. Not too ominous. Now, QEMU actually allocates the L1 table (1.6GB)

Re: [Qemu-devel] [PATCH] ppc: fix VTB migration

On Tue, Nov 21, 2017 at 09:16:43PM +0100, Laurent Vivier wrote: > Migration of a system under stress (for example, with > "stress-ng --numa 2") triggers on the destination > some kernel watchdog messages like: > > NMI watchdog: BUG: soft lockup - CPU#0 stuck for 3489660870s! > NMI watchdog: BUG:

Re: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations

Hi, This series failed automatic build test. Please find the testing commands and their output below. If you have docker installed, you can probably reproduce it locally. Subject: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Type: series Message-id:

Re: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations

Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations Type: series Message-id: 20171121212534.5177-1-richard.hender...@linaro.org === TEST SCRIPT BEGIN === #!/bin/bash BASE=base n=1

[Qemu-devel] qemu iotest 020 failing for vmdk after 2b7731938d9

Commit 2b7731938d9 adds a blkdebug driver test for failing commits, but the vmdk driver doesn't appear to appreciate this format: +_qemu_img_wrapper create -f vmdk -b "json:{'driver': 'raw', + 'file': { + 'driver': 'blkdebug', +

[Qemu-devel] [PATCH v6 21/26] tcg: Add generic vector ops for multiplication

Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 5 + tcg/i386/tcg-target.h| 1 + tcg/tcg-op-gvec.h| 2 ++ tcg/tcg-op.h | 1 + tcg/tcg-opc.h| 1 + tcg/tcg.h| 1 +

Re: [Qemu-devel] [ANNOUNCE] QEMU 2.11.0-rc2 is now available

forgot to cc qemu-devel On 11/21/2017 10:37 PM, Christian Borntraeger wrote: > a quick heads up . Rc2 now triggers > +qemu-img: block/block-backend.c:2088: blk_root_drained_end: Assertion > `blk->quiesce_counter' failed. > for several qemu iotests. > > I have not looked into any details. >

[Qemu-devel] [PATCH v6 18/26] tcg: Add generic vector ops for comparisons

Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 30 +++ tcg/i386/tcg-target.h| 1 + tcg/tcg-op-gvec.h| 4 + tcg/tcg-op.h | 3 + tcg/tcg-opc.h| 2 + tcg/tcg.h|

[Qemu-devel] [PATCH] hw/input/hid: Fix some wrong hid usage mappings.

There are some wrong hid usage mapping in hid_usage_keys table. It can be confirmed with "sendkey" command in monitor and verify the behavior in guest OS. This CL fixed some wrong hid usage mapping for these keys: kp_equals kp_comma audiomute volumedown volumeup power There still are some wrong

[Qemu-devel] [PATCH v6 17/26] target/arm: Use vector infrastructure for aa64 constant shifts

Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 386 ++--- tcg/tcg-op-gvec.c | 18 ++- tcg/tcg-op-vec.c | 9 +- 3 files changed, 351 insertions(+), 62 deletions(-) diff --git

[Qemu-devel] [PATCH v6 23/26] tcg: Add generic vector ops for extension

Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 8 +++ tcg/i386/tcg-target.h| 2 + tcg/tcg-op-gvec.h| 9 +++ tcg/tcg-op.h | 5 ++ tcg/tcg-opc.h| 5 ++ tcg/tcg.h|

[Qemu-devel] [PATCH v6 15/26] target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn

Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 103 +++-- 1 file changed, 35 insertions(+), 68 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 55a4902fc2..8769b4505a

[Qemu-devel] [PATCH v6 25/26] tcg/i386: Add vector operations/expansions for mul/extend

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 4 +- tcg/i386/tcg-target.opc.h | 1 + tcg/i386/tcg-target.inc.c | 186 ++ 3 files changed, 174 insertions(+), 17 deletions(-) diff --git

[Qemu-devel] [PATCH v6 19/26] target/arm: Use vector infrastructure for aa64 compares

Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 96 ++ 1 file changed, 62 insertions(+), 34 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c47faa5633..1ea7e37b03

[Qemu-devel] [Bug 1728256] Re: Memory corruption in Windows 10 guest / amd64

I just reported the bug in the kernel: https://bugzilla.kernel.org/show_bug.cgi?id=197951 If you reported or commented on the bug here, please go comment on that report confirming as well. A lot of open-source bugzilla projects tend to rarely pay attention to bug reports that only one person has

[Qemu-devel] [PATCH v6 12/26] tcg/i386: Add vector operations

The x86 vector instruction set is extremely irregular. With newer editions, Intel has filled in some of the blanks. However, we don't get many 64-bit operations until SSE4.2, introduced in 2009. The subsequent edition was for AVX1, introduced in 2011, which added three-operand addressing, and

[Qemu-devel] [PATCH v6 24/26] target/arm: Use vector infrastructure for aa64 widening shifts

Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 29 - 1 file changed, 12 insertions(+), 17 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c47d9caa49..1f7e9c4e19 100644 ---

[Qemu-devel] [PATCH v6 14/26] tcg: Add generic vector ops for interleave

Includes zip, unzip, and transform. Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 15 ++ tcg/i386/tcg-target.h| 3 + tcg/tcg-op-gvec.h| 17 +++ tcg/tcg-op.h | 6 + tcg/tcg-opc.h| 7 +

[Qemu-devel] [PATCH v6 09/26] target/arm: Use vector infrastructure for aa64 add/sub/logic

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 207 + 1 file changed, 134 insertions(+), 73 deletions(-) diff --git a/target/arm/translate-a64.c

[Qemu-devel] [PATCH v6 20/26] tcg/i386: Add vector operations/expansions for shift/cmp/interleave

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 6 +- tcg/i386/tcg-target.opc.h | 7 + tcg/i386/tcg-target.inc.c | 595 +- 3 files changed, 598 insertions(+), 10 deletions(-) diff --git

[Qemu-devel] [PATCH v6 26/26] tcg/aarch64: Add vector operations

Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 30 +- tcg/aarch64/tcg-target.opc.h | 3 + tcg/aarch64/tcg-target.inc.c | 674 --- 3 files changed, 660 insertions(+), 47 deletions(-) create mode 100644

[Qemu-devel] [PATCH v6 04/26] tcg: Add types and basic operations for host vectors

Nothing uses or enables them yet. Signed-off-by: Richard Henderson --- Makefile.target | 4 +- tcg/tcg-op.h | 30 + tcg/tcg-opc.h| 26 tcg/tcg.h| 56 + tcg/tcg-op-vec.c | 362

[Qemu-devel] [PATCH v6 05/26] tcg: Add generic vector expanders

Signed-off-by: Richard Henderson --- Makefile.target |2 +- accel/tcg/tcg-runtime.h | 29 ++ tcg/tcg-gvec-desc.h | 49 ++ tcg/tcg-op-gvec.h| 152 +++ tcg/tcg-op.h |1 +

[Qemu-devel] [PATCH v6 22/26] target/arm: Use vector infrastructure for aa64 multiplies

Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 171 - 1 file changed, 138 insertions(+), 33 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1ea7e37b03..c47d9caa49

[Qemu-devel] [PATCH v6 16/26] tcg: Add generic vector ops for constant shifts

Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Signed-off-by: Richard Henderson ---

[Qemu-devel] [PATCH v6 08/26] target/arm: Align vector registers

Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 89d49cdcb2..8238edaba9 100644 --- a/target/arm/cpu.h

[Qemu-devel] [PATCH v6 06/26] tcg: Allow multiple word entries into the constant pool

This will be required for storing vector constants. Signed-off-by: Richard Henderson --- tcg/tcg-pool.inc.c | 115 +++-- 1 file changed, 93 insertions(+), 22 deletions(-) diff --git a/tcg/tcg-pool.inc.c

[Qemu-devel] [PATCH v6 13/26] tcg: Add tcg_expand_vec_op and tcg-target.opc.h

These will be useful in the next few patches adding shifts, permutes, and multiplication. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.opc.h | 3 +++ tcg/tcg-opc.h | 6 ++ tcg/tcg.h | 11 +++

[Qemu-devel] [PATCH v6 10/26] target/arm: Use vector infrastructure for aa64 mov/not/neg

Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 43 ++- 1 file changed, 38 insertions(+), 5 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 572af456d1..bc14c28e71

[Qemu-devel] [PATCH v6 01/26] tcg: Remove TCGV_UNUSED* and TCGV_IS_UNUSED*

These are now trivial sets and tests against NULL. Unwrap. Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 4 --- tcg/tcg.h| 9 --- target/alpha/translate.c | 22 target/arm/translate-a64.c | 35

[Qemu-devel] [PATCH v6 02/26] tcg: Dynamically allocate TCGOps

With no fixed array allocation, we can't overflow a buffer. This will be important as optimizations related to host vectors may expand the number of ops used. Use QTAILQ to link the ops together. Signed-off-by: Richard Henderson --- include/exec/gen-icount.h |

[Qemu-devel] [PATCH v6 11/26] target/arm: Use vector infrastructure for aa64 dup/movi

Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 83 +++--- 1 file changed, 34 insertions(+), 49 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bc14c28e71..55a4902fc2

[Qemu-devel] [PATCH v6 00/26] tcg: generic vector operations

Quite a lot has changed since last time. The representation has changed such that the vector length and element size is stored in the TCGOp structure. The functions have changed such that the element size is passed explicitly rather than being encoded in the function name. I've added additional

[Qemu-devel] [PATCH v6 03/26] tcg: Generalize TCGOp parameters

We had two fields specific to INDEX_op_call. Rename these and add some macros so that the fields may be reused for other opcodes. Signed-off-by: Richard Henderson --- tcg/tcg.h | 10 ++ tcg/optimize.c | 4 ++-- tcg/tcg.c | 22

[Qemu-devel] [PATCH v6 07/26] tcg: Add tcg_signed_cond

Complimenting the existing tcg_unsigned_cond. Signed-off-by: Richard Henderson --- tcg/tcg.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/tcg/tcg.h b/tcg/tcg.h index 2acebd387a..49d4c5fe05 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -517,6 +517,12 @@

[Qemu-devel] [Bug 1728256] Re: Memory corruption in Windows 10 guest / amd64

I have yet to try disabling swap, but in the 5 days since I downgraded the kernel to 4.12.12 from 4.12.13, I have not had a single BSOD. I think 4.12.13 is the culprit. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU.

Re: [Qemu-devel] [PATCH for-2.11] Fix build of console and GUI executables for Windows

Am 16.11.2017 um 17:37 schrieb Stefan Weil: > It was broken by commit 8ecc89f6e792152496eccb684d6c8c48aba8027d which > moved the SDL linker flags from macro libs_softmmu to macro SDL_LIBS. > > Signed-off-by: Stefan Weil > --- > > Peter, can you apply this fix directly, or do

[Qemu-devel] [Bug 1728256] Re: Memory corruption in Windows 10 guest / amd64

I am on Arch as well, using a customized kernel using the vfio patchset (in this case 4.13.11). I was having the same issue as you guys, where my Windows 10 VM with an NVIDIA card passed in was getting the CRITICAL_STRUCTURE_CORRUPTION blue screen error message after running for a while. Usually I

[Qemu-devel] [PATCH] ppc: fix VTB migration

Migration of a system under stress (for example, with "stress-ng --numa 2") triggers on the destination some kernel watchdog messages like: NMI watchdog: BUG: soft lockup - CPU#0 stuck for 3489660870s! NMI watchdog: BUG: soft lockup - CPU#1 stuck for 3489660884s! This problem appears with the

Re: [Qemu-devel] [PATCH] accel/tcg/cpu-exec-common.c: Remove unnecessary include of memory-internal.h

On 11/21/2017 04:07 PM, Peter Maydell wrote: > The cpu-exec-common.c file includes memory-internal.h, but it doesn't > actually use anything from that header. Remove the unnecessary include. > > Signed-off-by: Peter Maydell > --- > accel/tcg/cpu-exec-common.c | 1 - >

[Qemu-devel] [ANNOUNCE] QEMU 2.11.0-rc2 is now available

Hello, On behalf of the QEMU Team, I'd like to announce the availability of the third release candidate for the QEMU 2.11 release. This release is meant for testing purposes and should not be used in a production environment. http://download.qemu-project.org/qemu-2.11.0-rc2.tar.xz

Re: [Qemu-devel] [PATCH v1] migration/ram.c: do not set 'postcopy_running' in POSTCOPY_INCOMING_END

* Juan Quintela (quint...@redhat.com) wrote: > Daniel Henrique Barboza wrote: > > When migrating a VM with 'migrate_set_capability postcopy-ram on' > > a postcopy_state is set during the process, ending up with the > > state POSTCOPY_INCOMING_END when the migration is

Re: [Qemu-devel] [PULL 0/2] Migration pull request

-rc2 release (2017-11-21 17:50:36 +) > > are available in the git repository at: > > git://github.com/juanquintela/qemu.git tags/migration/20171121 > > for you to fetch changes up to 383d8a77222c016610d626887de80e770cdd9936: > > migration/ram.c: do not set 'postcopy_runnin

Re: [Qemu-devel] [PATCH v3 00/45] Windbg supporting

Hi, This series seems to have some coding style problems. See output below for more information: Subject: [Qemu-devel] [PATCH v3 00/45] Windbg supporting Type: series Message-id: 151127322955.6888.16198535123422076171.st...@misha-pc.lan02.inno === TEST SCRIPT BEGIN === #!/bin/bash BASE=base

[Qemu-devel] [PULL 1/2] migration, xen: Fix block image lock issue on live migration

From: Anthony PERARD When doing a live migration of a Xen guest with libxl, the images for block devices are locked by the original QEMU process, and this prevent the QEMU at the destination to take the lock and the migration fail. >From QEMU point of view, once the

[Qemu-devel] [PULL 2/2] migration/ram.c: do not set 'postcopy_running' in POSTCOPY_INCOMING_END

From: Daniel Henrique Barboza When migrating a VM with 'migrate_set_capability postcopy-ram on' a postcopy_state is set during the process, ending up with the state POSTCOPY_INCOMING_END when the migration is over. This postcopy_state is taken into account inside

[Qemu-devel] [PULL 0/2] Migration pull request

tags/migration/20171121 for you to fetch changes up to 383d8a77222c016610d626887de80e770cdd9936: migration/ram.c: do not set 'postcopy_running' in POSTCOPY_INCOMING_END (2017-11-21 19:42:26 +0100) migration/next for 20171121

Re: [Qemu-devel] [PATCH for-2.12 1/2] cadence_ttc: extract CadenceTTCState to a new header file

On 8 November 2017 at 11:32, KONRAD Frederic wrote: > We want to add this model to the xlnx-zynqmp board so let's make > CadenceTTCState available in an header file. > > Signed-off-by: KONRAD Frederic > --- > hw/timer/cadence_ttc.c

Re: [Qemu-devel] [PATCH v2 for-2.11] migration, xen: Fix block image lock issue on live migration

Anthony PERARD wrote: > When doing a live migration of a Xen guest with libxl, the images for > block devices are locked by the original QEMU process, and this prevent > the QEMU at the destination to take the lock and the migration fail. > > From QEMU point of view,

Re: [Qemu-devel] [PATCH v1] migration/ram.c: do not set 'postcopy_running' in POSTCOPY_INCOMING_END

Daniel Henrique Barboza wrote: > When migrating a VM with 'migrate_set_capability postcopy-ram on' > a postcopy_state is set during the process, ending up with the > state POSTCOPY_INCOMING_END when the migration is over. This > postcopy_state is taken into account

Re: [Qemu-devel] [PATCH v7 00/13] Add support for the ZynqMP Generic QSPI

On 3 November 2017 at 00:00, Francisco Iglesias wrote: > Hi, > > This patch series is an attempt to add support for the ZynqMP QSPI (consisting > of the Generic QSPI and the legacy QSPI) to the xlnx-zcu102 board and connect > Numonyx n25q512a11 flashes to the QSPI. Also

Re: [Qemu-devel] KVM "fake DAX" flushing interface - discussion

On Tue, 2017-11-21 at 10:26 -0800, Dan Williams wrote: > On Tue, Nov 21, 2017 at 10:19 AM, Rik van Riel > wrote: > > On Fri, 2017-11-03 at 14:21 +0800, Xiao Guangrong wrote: > > > On 11/03/2017 12:30 AM, Dan Williams wrote: > > > > > > > > Good point, I was assuming that the

Re: [Qemu-devel] [PATCH v3 00/30] Initial i.MX7 support

On 6 November 2017 at 15:47, Andrey Smirnov wrote: > Hi everyone, > - Added proper USB emulation code, so now it should be possible to > emulated guest's USB bus The patchset is huge as it is, if you add more stuff to it it makes it even more likely to sink to

Re: [Qemu-devel] KVM "fake DAX" flushing interface - discussion

On Tue, Nov 21, 2017 at 10:19 AM, Rik van Riel wrote: > On Fri, 2017-11-03 at 14:21 +0800, Xiao Guangrong wrote: >> On 11/03/2017 12:30 AM, Dan Williams wrote: >> > >> > Good point, I was assuming that the mmio flush interface would be >> > discovered separately from the

Re: [Qemu-devel] [PATCH v3 30/30] Implement support for i.MX7 Sabre board

On 6 November 2017 at 15:48, Andrey Smirnov wrote: > Implement code needed to set up emulation of MCIMX7SABRE board from > NXP. For more info about the HW see: > >

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