On 06/25/2018 05:41 AM, Philippe Mathieu-Daudé wrote:
> Code change produced with:
>
> $ git ls-files | egrep '\.[ch]$' | \
> xargs sed -i -e 's/\(\W[KMGTPE]\)_BYTE/\1iB/g'
>
> Suggested-by: Stefan Weil
> Signed-off-by: Philippe Mathieu-Daudé
> Acked-by: David Gibson (ppc parts)
> ---
>
On 06/26/2018 09:49 PM, Eric Blake wrote:
> On 06/26/2018 05:22 PM, John Snow wrote:
>> Signed-off-by: John Snow
>> ---
>> tests/qemu-iotests/222 | 121
Probably would have helped to include 222.out, though.
>> +++
>> tests/qemu-iotests/group
On 06/25/2018 05:41 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> Acked-by: Eduardo Habkost
> ---
> target/i386/cpu.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
Reviewed-by: Richard Henderson
r~
On 06/25/2018 05:41 AM, Philippe Mathieu-Daudé wrote:
> Loosely based on 076b35b5a56.
>
> Suggested-by: Stefan Weil
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/qemu/units.h | 20
> 1 file changed, 20 insertions(+)
> create mode 100644 include/qemu/units.h
On 06/25/2018 05:41 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
> Reviewed-by: Stefan Weil
> ---
> block/vdi.c | 7 +++
> 1 file changed, 3 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson
r~
On 06/25/2018 09:00 AM, Alex Bennée wrote:
> This tests a bunch of registers that the kernel allows userspace to
> read including the CPUID registers.
>
> Signed-off-by: Alex Bennée
> ---
> tests/tcg/aarch64/Makefile.target | 2 +-
> tests/tcg/aarch64/sysregs.c | 99
On 06/25/2018 09:00 AM, Alex Bennée wrote:
> Userspace programs should (in theory) query the ELF HWCAP before
> probing these registers. Now we have implemented them all make it
> public.
>
> Signed-off-by: Alex Bennée
> ---
> linux-user/elfload.c | 1 +
> 1 file changed, 1 insertion(+)
Marc-André Lureau writes:
> Hi
>
> On Tue, Jun 19, 2018 at 11:06 AM, Markus Armbruster wrote:
>> Marc-André Lureau writes:
>>
>>> We commonly initialize attributes to None in .init(), then set their
>>> real value in .check(). Accessing the attribute before .check()
>>> yields None. If we're
On 06/25/2018 09:00 AM, Alex Bennée wrote:
> +#ifdef CONFIG_USER_ONLY
> +/* Some AArch64 CPU ID/feature are exported to userspace
> + * by the kernel (see HWCAP_CPUID) */
> +if (r->opc0 == 3 && r->crn == 0 &&
> +(r->crm == 0 ||
> +
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 5 +++
target/arm/translate-sve.c | 17 ++
target/arm/vec_helper.c| 67 ++
target/arm/sve.decode | 3 ++
4 files changed, 92 insertions(+)
diff
On 06/25/2018 09:00 AM, Alex Bennée wrote:
> Since kernel commit a86bd139f2 (arm64: arch_timer: Enable CNTVCT_EL0
> trap..) user-space has been able to read these system registers. As we
> can't use QEMUTimer's in linux-user mode we just directly call
> cpu_get_clock().
>
> Signed-off-by: Alex
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 4 +
target/arm/sve_helper.c| 162 +
target/arm/translate-sve.c | 37 +
target/arm/sve.decode | 4 +
4 files changed, 207 insertions(+)
diff
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 7 +++
target/arm/sve_helper.c| 100 +
target/arm/translate-sve.c | 24 +
target/arm/sve.decode | 4 ++
4 files changed, 135 insertions(+)
diff
Signed-off-by: Richard Henderson
---
v6: Rearrange the loops. The compiler does well with this form
and hopefully they are also easier to read.
---
target/arm/helper.h| 5 ++
target/arm/translate-sve.c | 18 ++
target/arm/vec_helper.c| 124
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 30 +
target/arm/helper.h| 12 +++---
target/arm/helper.c| 2 +-
target/arm/sve_helper.c| 88 ++
target/arm/translate-sve.c | 70
We've already added the helpers with an SVE patch, all that remains
is to wire up the aa64 and aa32 translators. Enable the feature
within -cpu max for CONFIG_USER_ONLY.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6: Fix aa32 index form.
---
target/arm/cpu.h |
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 14 ++
target/arm/sve_helper.c| 8
target/arm/translate-sve.c | 26 ++
target/arm/sve.decode | 4
4 files changed, 52 insertions(+)
diff
Enhance the existing helpers to support SVE, which takes the
index from each 128-bit segment. The change has no effect
for AdvSIMD, since there is only one such segment.
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 23 ++
target/arm/vec_helper.c| 50
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 42 +
target/arm/sve_helper.c| 43 ++
target/arm/translate-sve.c | 43 ++
Enable ARM_FEATURE_SVE for the generic "max" cpu.
Tested-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6: Set ARM_HWCAP_A64_SVE.
---
linux-user/elfload.c | 1 +
target/arm/cpu.c | 7 +++
target/arm/cpu64.c | 1 +
3 files changed, 9 insertions(+)
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 35 ++
target/arm/sve_helper.c| 61 ++
target/arm/translate-sve.c | 57 +++
target/arm/sve.decode | 8
For aa64 advsimd, we had been passing the pre-indexed vector.
However, sve applies the index to each 128-bit segment, so we
need to pass in the index separately.
For aa32 advsimd, the fp32 operation always has index 0, but
we failed to interpret the fp16 index correctly.
Signed-off-by: Richard
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 8 +++
target/arm/translate-sve.c | 47 ++
target/arm/vec_helper.c| 20
target/arm/sve.decode | 5
4 files changed, 80
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6: Squish fz16 a-la vfp_fcvt_f16_to_f32
---
target/arm/helper-sve.h| 13 +
target/arm/sve_helper.c| 55 ++
target/arm/translate-sve.c | 30 +
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6: Fix comment typos
---
target/arm/translate-sve.c | 60 +-
target/arm/sve.decode | 7 +
2 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-sve.c
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 49 ++
target/arm/sve_helper.c| 62 ++
target/arm/translate-sve.c | 40
target/arm/sve.decode | 11
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 56
target/arm/sve_helper.c| 69 +++
target/arm/translate-sve.c | 75 ++
target/arm/sve.decode |
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 14 +++
target/arm/sve_helper.c| 8
target/arm/translate-sve.c | 77 ++
target/arm/sve.decode | 9 +
4 files changed, 108 insertions(+)
diff
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 4 +++
target/arm/sve_helper.c| 70 ++
target/arm/translate-sve.c | 27 +++
target/arm/sve.decode | 3 ++
4 files changed, 104 insertions(+)
Signed-off-by: Richard Henderson
---
v6:
* Finish esz == msz && u==1 decode in sve.decode.
* Remove duplicate decode in trans_ST1_zprz.
* Add xs=2 comment.
* Reformat tables to leave room for ff helpers.
---
target/arm/helper-sve.h| 67 +
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 67 +
target/arm/sve_helper.c| 88 ++
target/arm/translate-sve.c | 40 -
3 files changed, 193 insertions(+), 2
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 14 +++
target/arm/translate-sve.c | 50 ++
target/arm/vec_helper.c| 48
target/arm/sve.decode | 19
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 7 +
target/arm/sve_helper.c| 56 ++
target/arm/translate-sve.c | 45 ++
target/arm/sve.decode | 5
4 files changed,
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 21 +
target/arm/sve.decode | 23 +++
2 files changed, 44 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 85 ++
target/arm/sve.decode | 11 +
2 files changed, 70 insertions(+), 26 deletions(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6:
* Rewrite to the usual two nested loops,
* Add comment about XS=2.
---
target/arm/helper-sve.h| 41 +
target/arm/sve_helper.c| 61 +++
target/arm/translate-sve.c | 75
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 30 +
target/arm/sve_helper.c| 38
target/arm/translate-sve.c | 90 ++
target/arm/sve.decode | 22 ++
4 files changed,
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6: Fix shift of data in 6 byte store.
---
target/arm/translate-sve.c | 103 +
target/arm/sve.decode | 6 +++
2 files changed, 109 insertions(+)
diff --git a/target/arm/translate-sve.c
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 35 +
target/arm/sve_helper.c| 153 +
target/arm/translate-sve.c | 121 +
target/arm/sve.decode
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 77 +
target/arm/sve_helper.c| 89 ++
target/arm/translate-sve.c | 46
target/arm/sve.decode | 17
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
v6: Fix typo in comment.
---
target/arm/helper-sve.h| 5 +++
target/arm/sve_helper.c| 41 +
target/arm/translate-sve.c | 62 ++
target/arm/sve.decode | 5
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-sve.c | 52 ++
target/arm/sve.decode | 9 +++
2 files changed, 61 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index
Signed-off-by: Richard Henderson
---
v6:
* Remove cold attribute from record_fault, add unlikely marker
to the if that protects its call, which seems to be enough to
prevent the function being inlined.
* Fix the set of bits masked by record_fault.
---
target/arm/helper-sve.h|
Signed-off-by: Richard Henderson
---
v6: Add some decode commentary.
---
target/arm/helper-sve.h| 16
target/arm/sve_helper.c| 158 +
target/arm/translate-sve.c | 49
target/arm/sve.decode | 18 +
4 files changed, 241
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 29 +
target/arm/sve_helper.c| 211 +
target/arm/translate-sve.c | 65
target/arm/sve.decode | 38 +++
4 files changed, 343
This is the remainder of the SVE enablement patches,
with an extra bonus patch to enable ARMv8.2-DotProd.
V6 updates based on review.
Patches with changes:
0002-target-arm-Implement-SVE-Contiguous-Load-first-fa.patch
0007-target-arm-Implement-SVE-FP-Multiply-Add-Group.patch
[Expired for QEMU because there has been no activity for 60 days.]
** Changed in: qemu
Status: Incomplete => Expired
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1767200
Title:
Kernel
On 2018-06-27 07:06:42 +0300, Michael S. Tsirkin wrote:
> On Tue, Jun 26, 2018 at 10:49:30PM -0500, Venu Busireddy wrote:
> > The patch set "Enable virtio_net to act as a standby for a passthru
> > device" [1] deals with live migration of guests that use passthrough
> > devices. However, that
On 2018-06-27 07:02:36 +0300, Michael S. Tsirkin wrote:
> On Tue, Jun 26, 2018 at 10:49:33PM -0500, Venu Busireddy wrote:
> > Add the "Vendor-Specific" capability to the Red Hat PCI bridge device
> > "pci-bridge", to contain the "Group Identifier" (UUID) that will be
> > used to pair a virtio
On Tue, Jun 26, 2018 at 10:49:30PM -0500, Venu Busireddy wrote:
> The patch set "Enable virtio_net to act as a standby for a passthru
> device" [1] deals with live migration of guests that use passthrough
> devices. However, that scheme uses the MAC address for pairing
> the virtio device and the
On 06/26/2018 03:44 AM, Peter Maydell wrote:
> A comment to the effect that the SVE fp-to-fp conversion
> routines always use IEEE format halfprec (ie ignore FPCR.AHP)
> would be helpful.
Ok.
> Are you sure we have the FPCR.FZ16 handling right here? That
> is, do we need the same "use the
On Tue, Jun 26, 2018 at 10:49:33PM -0500, Venu Busireddy wrote:
> Add the "Vendor-Specific" capability to the Red Hat PCI bridge device
> "pci-bridge", to contain the "Group Identifier" (UUID) that will be
> used to pair a virtio device with the passthrough device attached to
> that bridge.
>
>
In the beginning of the function, we initialize the local variable to 0,
and in the body of the function, we check the assigned values and exit
the loop immediately. So here it can never be non-zero.
Reported-by: Kevin Wolf
Signed-off-by: Fam Zheng
---
block/qcow2.c | 2 +-
1 file changed, 1
Fam Zheng (2):
qcow2: Remove dead check on !ret
block: Move request tracking to children in copy offloading
block/io.c| 59 ---
block/qcow2.c | 2 +-
2 files changed, 29 insertions(+), 32 deletions(-)
--
2.17.1
in_flight and tracked requests need to be tracked in every layer during
recursion. For now the only user is qemu-img convert where overlapping
requests and IOThreads don't exist, therefore this change doesn't make
much difference form user point of view, but it is incorrect as part of
the API. Fix
The patch set "Enable virtio_net to act as a standby for a passthru
device" [1] deals with live migration of guests that use passthrough
devices. However, that scheme uses the MAC address for pairing
the virtio device and the passthrough device. The thread "netvsc:
refactor notifier/event handling
Add a new bridge device "pcie-downstream" with a Vendor ID of
PCI_VENDOR_ID_REDHAT and Device ID of PCI_DEVICE_ID_REDHAT_DOWNSTREAM.
Also add the "Vendor-Specific" capability to the bridge to contain the
"Group Identifier" (UUID) that will be used to pair a virtio device with
the passthrough
Use the virtio PCI capability "VIRTIO_PCI_CAP_GROUP_ID_CFG" to store the
"Group Identifier" (UUID) specified via the command line option "uuid"
for the virtio device. The capability will be present in the virtio
device's configuration space iff the "uuid" option is specified.
Group Identifier is
Add the "Vendor-Specific" capability to the Red Hat PCI bridge device
"pci-bridge", to contain the "Group Identifier" (UUID) that will be
used to pair a virtio device with the passthrough device attached to
that bridge.
This capability is added to the bridge iff the "uuid" option is specified
for
Add VIRTIO_PCI_CAP_GROUP_ID_CFG (Group Identifier) capability to the
virtio PCI capabilities to allow for the grouping of devices.
Signed-off-by: Venu Busireddy
---
content.tex | 36
1 file changed, 36 insertions(+)
diff --git a/content.tex b/content.tex
It may not always be desirable to have a random UUID stuffed into the
'_field' member. Add a new boolean option '_default' that will allow
the caller to specify if a random UUID needs be generated or not.
Also modified the instance where this macro is used.
Signed-off-by: Venu Busireddy
---
On Wed, Jun 27, 2018 at 11:38:17AM +1000, Benjamin Herrenschmidt wrote:
> On Wed, 2018-06-27 at 03:35 +0300, Michael S. Tsirkin wrote:
> >
> > > +
> > > +/* Extract field fname from val */
> > > +#define GETFIELD(fname, val)\
> > > +(((val) & fname##_MASK) >>
On 06/25/2018 09:31 AM, Emilio G. Cota wrote:
> +} else if (page1 == page2) {
> +page_lock(p1);
> +if (ret_p2) {
> +*ret_p2 = p1;
I think you should set NULL here...
> @@ -1623,7 +1641,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t
> phys_pc,
>
On 06/26/2018 07:00 PM, Jean-Christophe Dubois wrote:
> The qdev_get_gpio_in() function accept an int as second parameter.
>
> Signed-off-by: Jean-Christophe Dubois
Reviewed-by: Philippe Mathieu-Daudé
> ---
> hw/arm/fsl-imx7.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
On 06/26/2018 11:14 PM, Eduardo Habkost wrote:
> Mapping.iteritems() doesn't exist in Python 3.
>
> Note that Mapping.items() exists in both Python 3 and Python 2,
> but it returns a list (and not an iterator) in Python 2. The
> existing code will work on both cases, though.
>
> Signed-off-by:
Instead of treating dockerfile contents as byte sequences, always
open dockerfiles in text mode and treat it as text.
This is not strictly required to make the script compatible with
Python 3, but it's a simpler and safer way than opening
dockerfiles in binary mode and decoding the data data
Mapping.iteritems() doesn't exist in Python 3.
Note that Mapping.items() exists in both Python 3 and Python 2,
but it returns a list (and not an iterator) in Python 2. The
existing code will work on both cases, though.
Signed-off-by: Eduardo Habkost
---
tests/docker/docker.py | 2 +-
1 file
Add type annotations that indicate how the code works today, to
make the conversion to Python 3 easier and safer.
With these type annotations, "mypy -2" is not reporting any
issues, but "mypy" in Python 3 mode reports a few problems:
tests/docker/docker.py:233: error: Argument 1 to
The "ldd" output is a byte sequence, not a string. Use bytes
literals while handling the output, and use os.fsdecode() on the
resulting file paths before returning.
Signed-off-by: Eduardo Habkost
---
tests/docker/docker.py | 15 ---
1 file changed, 12 insertions(+), 3 deletions(-)
The file passed as argument to TarFile.addfile() must be a binary
file, so BytesIO is more appropriate than StringIO.
This is necessary to make the code work on Python 3.
Signed-off-by: Eduardo Habkost
---
tests/docker/docker.py | 15 ++-
1 file changed, 6 insertions(+), 9
We'll add type annotations to the run() methods, so add 'return'
statements to all the functions so the type checker won't
complain.
Signed-off-by: Eduardo Habkost
---
tests/docker/docker.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tests/docker/docker.py
This series makes tests/docker/docker.py compatible with both
Python 2 and Python 3, and adds type annotation to make
maintenance easier in the future.
A note about dockerfile encoding
One decision I made while working on this was to open dockerfiles
in text mode
On 06/26/2018 05:22 PM, John Snow wrote:
Signed-off-by: John Snow
---
tests/qemu-iotests/222 | 121 +++
tests/qemu-iotests/group | 1 +
2 files changed, 122 insertions(+)
create mode 100644 tests/qemu-iotests/222
diff --git
On Wed, 2018-06-27 at 03:35 +0300, Michael S. Tsirkin wrote:
>
> > +
> > +/* Extract field fname from val */
> > +#define GETFIELD(fname, val)\
> > +(((val) & fname##_MASK) >> fname##_LSH)
> > +
> > +/* Set field fname of oval to fval
> > + * NOTE: oval isn't modified,
On 06/26/2018 05:22 PM, John Snow wrote:
In the case of image fleecing, the node we choose as the source
for a blockdev-backup is going to be both a root node AND the
backing node for the exported image. It does not qualify as a root
image in this case.
Loosen the restriction.
Did we regress
On Tue, Jun 26, 2018 at 04:22:14PM +0200, Cédric Le Goater wrote:
> commit d35aefa9ae15 ("ppc/pnv: introduce a new intc_create() operation
> to the chip model") changed the object link in the pnv_core_realize()
> routine but a return was forgotten in case of error, which can lead to
> more
On Tue, Jun 26, 2018 at 03:59:28PM +0200, Cédric Le Goater wrote:
> diff --git a/include/hw/pci-host/pnv_phb3_regs.h
> b/include/hw/pci-host/pnv_phb3_regs.h
> new file mode 100644
> index ..a1672726b908
> --- /dev/null
> +++ b/include/hw/pci-host/pnv_phb3_regs.h
> @@ -0,0 +1,510 @@
>
On Tue, Jun 26, 2018 at 06:37:12PM +0200, Cédric Le Goater wrote:
1;5202;0c> On 06/26/2018 03:27 PM, Greg Kurz wrote:
> > On Mon, 25 Jun 2018 11:17:13 +0200
> > Cédric Le Goater wrote:
> >
> >> Hello,
> >>
> >
> > Hello,
> >
> > Sorry I didn't manage to look at this before it got merged :)
> >
On Tue, Jun 26, 2018 at 04:38:26PM -0700, Siwei Liu wrote:
> On Mon, Jun 25, 2018 at 6:50 PM, Michael S. Tsirkin wrote:
> > On Mon, Jun 25, 2018 at 10:54:09AM -0700, Samudrala, Sridhar wrote:
> >> > > > > Might not neccessarily be something wrong, but it's very limited to
> >> > > > > prohibit
On Mon, Jun 25, 2018 at 6:50 PM, Michael S. Tsirkin wrote:
> On Mon, Jun 25, 2018 at 10:54:09AM -0700, Samudrala, Sridhar wrote:
>> > > > > Might not neccessarily be something wrong, but it's very limited to
>> > > > > prohibit the MAC of VF from changing when enslaved by failover.
>> > > > You
On 06/26/2018 03:07 PM, Stafford Horne wrote:
> Hello,
>
> I think I found out something.
>
> in: target/openrisc/sys_helper.c:92
>
> When we write to `env->tlb.dtlb[idx].tr` in helper_mtspr():
> 93 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1):
> /* DTLBW0TR 0-127 */
> 94
Signed-off-by: John Snow
---
tests/qemu-iotests/222 | 121 +++
tests/qemu-iotests/group | 1 +
2 files changed, 122 insertions(+)
create mode 100644 tests/qemu-iotests/222
diff --git a/tests/qemu-iotests/222 b/tests/qemu-iotests/222
new file mode
A simple, hastily-written example of image fleecing over NBD.
John Snow (2):
block: allow blockdev-backup from any source
iotests: add 222 to test basic fleecing
blockdev.c | 2 +-
tests/qemu-iotests/222 | 121 +++
In the case of image fleecing, the node we choose as the source
for a blockdev-backup is going to be both a root node AND the
backing node for the exported image. It does not qualify as a root
image in this case.
Loosen the restriction.
Signed-off-by: John Snow
---
blockdev.c | 2 +-
1 file
On Tue, 2018-06-26 at 17:57 +0200, Andrea Bolognani wrote:
> On Tue, 2018-06-26 at 15:59 +0200, Cédric Le Goater wrote:
> > This is a model of the PCIe host bridge found on Power8 chips,
> > including PowerBus logic interface, IOMMU support, PCIe root complex,
> > XICS MSI and LSI interrupt
Hello,
I think I found out something.
in: target/openrisc/sys_helper.c:92
When we write to `env->tlb.dtlb[idx].tr` in helper_mtspr():
93 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1):
/* DTLBW0TR 0-127 */
94 idx = spr - TO_SPR(1, 640);
95
From: Sebastian Bauer
The sm501 currently implements only a very limited set of raster operation
modes. After this change, unknown raster operation modes are logged so
these can be easily spotted.
Signed-off-by: Sebastian Bauer
Signed-off-by: BALATON Zoltan
---
hw/display/sm501.c | 23
Signed-off-by: Jean-Christophe Dubois
---
hw/arm/mcimx7d-sabre.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 95fb409d9c..9c5f0e70c3 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -18,10 +18,8 @@
#include
Display updates and drawing hardware cursor did not work when frame
buffer address was non-zero. Fix this by taking the frame buffer
address into account in these cases. This fixes screen dragging on
AmigaOS. Based on patch by Sebastian Bauer.
Signed-off-by: Sebastian Bauer
Signed-off-by:
Emulate the i2c part of SM501 which is used to access the EDID info
from a monitor.
The vmstate structure is changed and its version is increased but
SM501 is only used on SH and PPC sam460ex machines that don't support
cross-version migration.
Signed-off-by: BALATON Zoltan
---
v2:
- added
The qdev_get_gpio_in() function accept an int as second parameter.
Signed-off-by: Jean-Christophe Dubois
---
hw/arm/fsl-imx7.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index e15aadb587..44fde03cbe 100644
---
From: Sebastian Bauer
Changing the palette of a color index has as an immediate effect on
all pixels with the corresponding index on real hardware. Performing a
full update after a palette change is a simple way to emulate this
effect.
Signed-off-by: Sebastian Bauer
Signed-off-by: BALATON
From: Sebastian Bauer
Before, crt_h_total was used for src_width and dst_width. This is a
property of the current display setting and not relevant for the 2D
operation that also can be done off-screen. The pitch register's purpose
is to describe line pitch relevant of the 2D operation.
Version 2 of the sm501 changes with fixes that are needed to get
AmigaOS 4.1FE to boot and able to produce graphics.
The strange blue-white colors that first appear are actually correct
and because of AmigaOS selecting a low resolution PAL mode by default
instead of a board specific mode. To work
Signed-off-by: Jean-Christophe Dubois
---
hw/arm/fsl-imx7.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c
index 26c1d27f7c..e15aadb587 100644
--- a/hw/arm/fsl-imx7.c
+++ b/hw/arm/fsl-imx7.c
@@ -459,7 +459,7 @@ static void
Small fixes in the i.mx7d code.
Jean-Christophe Dubois (3):
i.mx7d: Remove unused header files
i.mx7d: Change SRC unimpleted device name from sdma to src
i.mx7d: Change IRQ number type from hwaddr to int
hw/arm/fsl-imx7.c | 8
hw/arm/mcimx7d-sabre.c | 2 --
2 files changed,
From: Sebastian Bauer
Add support for the negated destination operation mode. This is used e.g.
by AmigaOS for the INVERSEVID drawing mode. With this change, the cursor
in the shell and non-immediate window adjustment are working now.
Signed-off-by: Sebastian Bauer
Signed-off-by: BALATON
Set the changed memory region dirty after performed a 2D operation to
ensure that the screen is updated properly.
Signed-off-by: BALATON Zoltan
---
v2: fixed to work with non-zero fb_addr
hw/display/sm501.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
On 06/26/2018 12:50 PM, G 3 wrote:
>
> If FPSCR[ZE] is set or not set, answer = 0x7ff0. This indicates to
> me that the fdiv instruction needs a little work. This is what I think should
> happen. If division by zero takes place and the FPSCR[ZE] bit is set, then
> the
> value in the
On 06/26/2018 10:40 AM, Paolo Bonzini wrote:
This command lets you query the connection status of each pr-manager-helper
object.
Signed-off-by: Paolo Bonzini
---
+++ b/qapi/block.json
@@ -77,6 +77,33 @@
{ 'struct': 'BlockdevSnapshotInternal',
'data': { 'device': 'str', 'name': 'str' }
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