On Thu, Jun 28, 2018 at 12:14:51PM +0200, Greg Kurz wrote:
> In a future patch the machine code will need to retrieve the MMU
> information from KVM during machine initialization before the CPUs
> are created.
>
> Actually, KVM_PPC_GET_SMMU_INFO is a VM class ioctl, and thus, it only
> needs the
On Thu, Jun 28, 2018 at 09:48:25PM +0200, Greg Kurz wrote:
> On Thu, 28 Jun 2018 12:14:25 +0200
> Greg Kurz wrote:
>
> > Since the recent cleanups to hide host configuration details from guests,
> > it isn't possible to start an older machine type with HV KVM [*]:
> >
> > qemu-system-ppc64: KVM
On Thu, Jun 28, 2018 at 12:15:14PM +0200, Greg Kurz wrote:
> It is currently not possible to run a pseries-2.12 or older machine
> with HV KVM. QEMU prints the following and exits right away.
>
> qemu-system-ppc64: KVM doesn't support for base page shift 34
>
> The "hpt-max-page-size" capability
On Thu, Jun 28, 2018 at 12:15:33PM +0200, Greg Kurz wrote:
> It is unsafe to rely on *_enabled() helpers before the accelerator has
> been initialized, ie, accel_init_machine() has succeeded, because they
> always return false. But it is still possible to end up calling them
> indirectly by
On Fri, Jun 29, 2018 at 02:48:40PM +1000, David Gibson wrote:
> On Fri, Jun 29, 2018 at 12:38:33AM +0200, BALATON Zoltan wrote:
> > PPC440 SoCs such as the AMCC 460EX have a DMA controller which is used
> > by AmigaOS on the sam460ex. Implement the parts used by AmigaOS so it
> > can get further
On Fri, Jun 29, 2018 at 12:38:33AM +0200, BALATON Zoltan wrote:
> PPC440 SoCs such as the AMCC 460EX have a DMA controller which is used
> by AmigaOS on the sam460ex. Implement the parts used by AmigaOS so it
> can get further booting on the sam460ex machine.
>
> Signed-off-by: BALATON Zoltan
>
On Fri, Jun 29, 2018 at 12:38:33AM +0200, BALATON Zoltan wrote:
> The Sam460ex has an M41T80 serial RTC chip on I2C bus 0 at address 0x68.
>
> Signed-off-by: BALATON Zoltan
> Reviewed-by: Cédric Le Goater
With Cédric's review, I've applied patches 1..3 to ppc-for-3.0.
> ---
>
On Sun, Jun 24, 2018 at 07:12:48PM -0400, John Arbuckle wrote:
> The FPSCR[FI] bit indicates if the last floating point instruction had a
> result that was rounded. Each consecutive floating point instruction is
> suppose to set this bit to the correct value. What currently happens is this
>
On Thu, Jun 28, 2018 at 09:36:00PM +0800, Jason Wang wrote:
>
>
> On 2018年06月04日 17:55, guangrong.x...@gmail.com wrote:
> > From: Xiao Guangrong
> >
> > It's the simple lockless ring buffer implement which supports both
> > single producer vs. single consumer and multiple producers vs.
> >
On Tue, Jun 26, 2018 at 09:19:08AM -0700, Richard Henderson wrote:
> In another patch set this week, I had noticed the old linux-user
> do_store_exclusive code was still present. I had thought that was
> dead code that simply hadn't been removed, but it turned out that
> we had not completed the
On Tue, Jun 26, 2018 at 09:19:11AM -0700, Richard Henderson wrote:
> Section 1.4 of the Power ISA v3.0B states that this insn is
> single-copy atomic. As we cannot (yet) issue 128-bit loads
> within TCG, use the generic helpers provided.
>
> Signed-off-by: Richard Henderson
Applied to
On Thu, Jun 28, 2018 at 08:22:38AM -0700, Richard Henderson wrote:
> On 06/27/2018 08:49 PM, David Gibson wrote:
> >> +/* High part of 128-bit helper return. */
> >> +uint64_t retxh;
> >> +
> >
> > Adding a temporary here is kind of gross. I guess the helper
> > interface doesn't allow
On 06/28/2018 09:36 PM, Jason Wang wrote:
On 2018年06月04日 17:55, guangrong.x...@gmail.com wrote:
From: Xiao Guangrong
It's the simple lockless ring buffer implement which supports both
single producer vs. single consumer and multiple producers vs.
single consumer.
Finally, it fetches
On 06/28/2018 07:55 PM, Wei Wang wrote:
On 06/28/2018 06:02 PM, Xiao Guangrong wrote:
CC: Paul, Peter Zijlstra, Stefani, Lai who are all good at memory barrier.
On 06/20/2018 12:52 PM, Peter Xu wrote:
On Mon, Jun 04, 2018 at 05:55:17PM +0800, guangrong.x...@gmail.com wrote:
From: Xiao
On 06/28/2018 05:57 PM, Philippe Mathieu-Daudé wrote:
>> @@ -4851,11 +4851,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>>.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
>>.access = PL1_R, .type = ARM_CP_CONST,
>>.resetvalue =
Hi Daniel,
On 06/28/2018 05:36 PM, Daniel P. Berrangé wrote:
On Thu, Jun 28, 2018 at 05:12:39PM +0800, Xiao Guangrong wrote:
After this patch, the workload is moved to the worker thread, is it
acceptable?
It depends on your point of view. If you have spare / idle CPUs on the host,
then
On 28 June 2018 at 19:36, Andrew Jones wrote:
> On Thu, Jun 28, 2018 at 06:13:28PM +0800, Hongbo Zhang wrote:
>> On 28 June 2018 at 17:04, Andrew Jones wrote:
>> > On Thu, Jun 28, 2018 at 04:11:56PM +0800, Hongbo Zhang wrote:
>> >> On 27 June 2018 at 22:56, Igor Mammedov wrote:
>> >> > On Wed,
Is there any way to define a new CPU model that isn't EPYC (maybe
ryzen?) but is feature compatible with the threadripper?
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https://bugs.launchpad.net/bugs/1778966
Title:
Windows 1803
Opteron didn't work do to some missing features. I was able to get
nehalem to come up but that looks like the closest.
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https://bugs.launchpad.net/bugs/1778966
Title:
Windows 1803 and
Regrettably opteron_g5 is not a workaround. I get a complaint that my
cpu doesn't provide xop, fma4, tbm.
I've tried a number of other cpus including nehalem, phenom and athlon
with similar results.
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On Thu, Jun 28, 2018 at 02:14:15PM +0200, David Hildenbrand wrote:
> Let's set the alignment just like for the posix variant. This will
> implicitly set the alignment of the underlying memory region and
> therefore make memory_region_get_alignment(mr) return something > 0 for
> all memory backends
On Thu, Jun 28, 2018 at 02:14:16PM +0200, David Hildenbrand wrote:
> All applicable memory regions always have an alignment > 0. All memory
> backends result in file_ram_alloc() or qemu_anon_ram_alloc() getting
> called, setting the alignment to > 0.
>
> So a PCDIMM memory region always has an
On Thu, Jun 28, 2018 at 02:14:17PM +0200, David Hildenbrand wrote:
> We can assign and verify the slot before realizing and trying to plug.
> reading/writing the address property should never fail, so let's reduce
> error handling a bit by using _abort. Getting access to the memory
> region now
On Thu, Jun 28, 2018 at 10:35:24PM +0200, Sebastian Bauer wrote:
> When a branch instructions points to itself, only external events will
> change the internally observable cpu state. This change will adjust the
> behaviour of QEMU such that it sends the emulated cpu into a sleep state
> if this
On 06/28/2018 09:57 PM, Philippe Mathieu-Daudé wrote:
> Hi Richard,
>
> On 06/28/2018 09:15 PM, Richard Henderson wrote:
>> This register was added to aa32 state by ARMv8.2.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> target/arm/cpu.h| 1 +
>> target/arm/cpu.c| 4
>>
On 06/28/2018 09:15 PM, Richard Henderson wrote:
> Patch 1 fixes the SIGFPE that Alex found with --test-sve=3.
> Patch 2 fixes a problem pointed out by Laurent, presumably
> via inspection.
>
> The rest begin enabling cpu features for -cpu max.
> I'm still working on SVE itself, but these are
On 06/28/2018 09:15 PM, Richard Henderson wrote:
> For the supported extensions, fill in the appropriate bits in
> ID_ISAR5, ID_ISAR6, ID_AA64ISAR0, ID_AA64ISAR1.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.c | 24 +---
> target/arm/cpu64.c | 36
Hi Richard,
On 06/28/2018 09:15 PM, Richard Henderson wrote:
> This register was added to aa32 state by ARMv8.2.
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/cpu.h| 1 +
> target/arm/cpu.c| 4
> target/arm/cpu64.c | 2 ++
> target/arm/helper.c | 5 ++---
> 4 files
On 06/28/2018 09:15 PM, Richard Henderson wrote:
> Leave ARM_CP_SVE, removing ARM_CP_FPU; the sve_access_check
> produced by the flag already includes fp_access_check. If
> we also check ARM_CP_FPU the double fp_access_check asserts.
Maybe we can surround this assert() with #ifdef DEBUG_DISAS...
On 06/28/2018 09:15 PM, Richard Henderson wrote:
> We already check for the same condition within the normal integer
> sdiv and sdiv64 helpers. Use a slightly different formation that
> does not require deducing the expression type.
>
> Fixes: f97cfd596ed
> Signed-off-by: Richard Henderson
On 06/28/2018 09:15 PM, Richard Henderson wrote:
> There is no need to re-set these 3 features already
> implied by the call to aarch64_a15_initfn.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/arm/cpu.c | 3 ---
> 1 file changed, 3 deletions(-)
>
>
On 06/28/2018 09:15 PM, Richard Henderson wrote:
> There is no need to re-set these 9 features already
> implied by the call to aarch64_a57_initfn.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
> ---
> target/arm/cpu64.c | 9 -
> 1 file changed, 9
There is no need to re-set these 3 features already
implied by the call to aarch64_a15_initfn.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index aa62315cea..878cc6c7e8 100644
---
We already check for the same condition within the normal integer
sdiv and sdiv64 helpers. Use a slightly different formation that
does not require deducing the expression type.
Fixes: f97cfd596ed
Signed-off-by: Richard Henderson
---
target/arm/sve_helper.c | 16 +++-
1 file
This register was added to aa32 state by ARMv8.2.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 +
target/arm/cpu.c| 4
target/arm/cpu64.c | 2 ++
target/arm/helper.c | 5 ++---
4 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.h
For the supported extensions, fill in the appropriate bits in
ID_ISAR5, ID_ISAR6, ID_AA64ISAR0, ID_AA64ISAR1.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 24 +---
target/arm/cpu64.c | 36
2 files changed, 45 insertions(+),
Patch 1 fixes the SIGFPE that Alex found with --test-sve=3.
Patch 2 fixes a problem pointed out by Laurent, presumably
via inspection.
The rest begin enabling cpu features for -cpu max.
I'm still working on SVE itself, but these are standalone
and perhaps worth merging before softfreeze.
Leave ARM_CP_SVE, removing ARM_CP_FPU; the sve_access_check
produced by the flag already includes fp_access_check. If
we also check ARM_CP_FPU the double fp_access_check asserts.
Reported-by: Laurent Desnogues
Signed-off-by: Richard Henderson
---
target/arm/helper.c| 8
There is no need to re-set these 9 features already
implied by the call to aarch64_a57_initfn.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 9 -
1 file changed, 9 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 3b4bc73ffa..8040493d5c 100644
---
On Fri, Jun 29, 2018 at 12:44 AM, Eric Blake wrote:
> On 06/26/2018 10:10 AM, Sameeh Jubran wrote:
>
>> From: Sameeh Jubran
>>
>> The fsinfo command is currently implemented for Windows only and it's disk
>> parameter can be enabled by adding the define "CONFIG_QGA_NTDDSCSI" to
>> the qga
>>
Given a debian standard 4.16.0 kernel,
https://github.com/rth7680/qemu/tree/tgt-arm-sve-c
will crash qemu:
$ gdb --args ../bld/aarch64-softmmu/qemu-system-aarch64 \
-cpu max -M virt -m 4G -smp 8 \
-drive if=virtio,file=./deb-arm64.img,format=raw \
-bios /usr/share/edk2/aarch64/QEMU_EFI.fd
The PPC440 User Manual says that if bit 31 is set, the contents of
CR[CR0] are undefined for indexed store instructions but this form is
not invalid. Other PPC variants confirming to recent ISA where this
bit may be reserved should ignore reserved bits and not raise invalid
instruction exception.
Basic emulation of the M41T80 serial (I2C) RTC chip. Only getting time
of day is implemented. Setting time and RTC alarm are not supported.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
---
v3: Fixed \n-s in log messages
MAINTAINERS | 1 +
PPC440 SoCs such as the AMCC 460EX have a DMA controller which is used
by AmigaOS on the sam460ex. Implement the parts used by AmigaOS so it
can get further booting on the sam460ex machine.
Signed-off-by: BALATON Zoltan
---
v6:
- CamelCase type names
- Check return value of
These are the remaining patches for sam460ex needed to implement RTC
and get AmigaOS to boot. The sm501 patches (now a separate series) and
Sebastian's ehci patch are also needed to get AmigaOS working. I'd
appreciate if this could be merged before the imminent 3.0 freeze so
we could have at least
The Sam460ex has an M41T80 serial RTC chip on I2C bus 0 at address 0x68.
Signed-off-by: BALATON Zoltan
Reviewed-by: Cédric Le Goater
---
hw/ppc/sam460ex.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c
index bdc53d2..dc730cc 100644
---
Rewrite to make it closer to how real device works so that guest OS
drivers can access I2C devices. Previously this was only a hack to
allow U-Boot to get past accessing SPD EEPROMs but to support other
I2C devices and allow guests to access them we need to model real
device more properly.
On 06/27/2018 09:47 AM, Emilio G. Cota wrote:
>>> -if (p2) {
>>> +if (p2 && p2 != p) {
>>> page_unlock(p2);
>>
>> ... so that you need no change here.
>> Otherwise it looks good.
>
> I did that initially. However, note that if we do that then
> the second page is not added to the
On 06/27/2018 09:26 AM, Eric Blake wrote:
> On 06/27/2018 06:27 AM, Igor Mammedov wrote:
>> On Mon, 25 Jun 2018 09:41:53 -0300
>> Philippe Mathieu-Daudé wrote:
>>
>>> Loosely based on 076b35b5a56.
>>>
>>> Suggested-by: Stefan Weil
>>> Signed-off-by: Philippe Mathieu-Daudé
>>> ---
>
>>>
On 06/28/2018 01:07 PM, Aleksandar Markovic wrote:
> Therefore, I think it makes sense to (more or less) split translate.c into,
> let's say, following set of files:
>
> * translate_cmn_chk.h - definitions of (typically inlined) functions
> check_XXX()
> * translate_cmn_gen.h - declarations
On 06/28/2018 03:36 PM, Alex Bennée wrote:
> Philippe Mathieu-Daudé writes:
>> On 06/28/2018 01:23 PM, Alex Bennée wrote:
>>> Philippe Mathieu-Daudé writes:
>>>
Similar to the BootLinuxConsoleX86_64 test:
boot a Linux kernel on a Malta board and verify the serial is working.
Le 28/06/2018 à 22:05, Peter Maydell a écrit :
> On 28 June 2018 at 20:23, Laurent Vivier wrote:
>> Le 28/06/2018 à 15:23, Peter Maydell a écrit :
>>> On 28 June 2018 at 14:03, Laurent Vivier wrote:
Le 26/06/2018 à 18:56, Peter Maydell a écrit :
> Add support for MMU protection regions
On 06/27/2018 07:07 PM, Max Reitz wrote:
The generic bdrv_dirname() implementation would be able to generate some
form of directory name for many NBD nodes, but it would be always wrong.
Therefore, we have to explicitly make it an error (until NBD has some
form of specification for export paths,
On 06/28/2018 06:54 PM, Alex Bennée wrote:
> Alex Bennée writes:
>> Philippe Mathieu-Daudé writes:
>>
>>> Tests can change this property to run tests in other
>>> architectures than the host one.
>>>
>>> Signed-off-by: Philippe Mathieu-Daudé
>>> ---
>>>
On 06/27/2018 07:07 PM, Max Reitz wrote:
Signed-off-by: Max Reitz
---
tests/qemu-iotests/iotests.py | 3 +++
1 file changed, 3 insertions(+)
Wow, we didn't need that before? Matches what shell tests have.
Reviewed-by: Eric Blake
--
Eric Blake, Principal Software Engineer
Red Hat, Inc.
On 06/27/2018 07:07 PM, Max Reitz wrote:
Basically, bdrv_refresh_filename() should respect all children of a
BlockDriverState. However, generally those children are driver-specific,
so this function cannot handle the general case. On the other hand,
there are only few drivers which use other
On 06/27/2018 07:07 PM, Max Reitz wrote:
If the backing file is overridden, this most probably does change the
guest-visible data of a BDS. Therefore, we will need to consider this
in bdrv_refresh_filename().
So all in all, there will be false negatives where (as of a future
patch)
Alex Bennée writes:
> Philippe Mathieu-Daudé writes:
>
>> Tests can change this property to run tests in other
>> architectures than the host one.
>>
>> Signed-off-by: Philippe Mathieu-Daudé
>> ---
>> tests/acceptance/avocado_qemu/__init__.py | 17 +
>> 1 file changed, 13
On 06/27/2018 07:07 PM, Max Reitz wrote:
bdrv_refresh_filename() should simply skip all implicit nodes. They are
supposed to be invisible to the user, so they should not appear in
filename information.
Signed-off-by: Max Reitz
---
block.c | 14 ++
1 file changed, 14
On 06/27/2018 07:07 PM, Max Reitz wrote:
Before this patch, bdrv_refresh_filename() is used in a pushing manner:
Whenever the BDS graph is modified, the parents of the modified edges
are supposed to be updated (recursively upwards). However, that is
unviable, considering that we want child
On 06/26/2018 10:10 AM, Sameeh Jubran wrote:
From: Sameeh Jubran
The fsinfo command is currently implemented for Windows only and it's disk
parameter can be enabled by adding the define "CONFIG_QGA_NTDDSCSI" to the qga
code. When enabled and executed the qemu-ga crashed with the following
On 06/28/2018 01:52 PM, Peter Maydell wrote:
> On 27 June 2018 at 18:44, Alistair Francis wrote:
>> The following changes since commit 00928a421d47f49691cace1207481b7aad31b1f1:
>>
>> Merge remote-tracking branch
>> 'remotes/pmaydell/tags/pull-target-arm-20180626' into staging (2018-06-26
>>
On 06/28/2018 04:25 PM, John Snow wrote:
Signed-off-by: John Snow
---
tests/qemu-iotests/222 | 152 +
tests/qemu-iotests/222.out | 66
tests/qemu-iotests/group | 1 +
3 files changed, 219 insertions(+)
create mode
On Wed, Jun 27, 2018 at 08:03:07PM -0700, Richard Henderson wrote:
> Changes since v2:
> * Fix missing mtspr break.
> * Reorg print_insn_or1k and interrupt logging to the start.
> * Adjust exit after mtspr; fixing smp kernel crash.
> * Fix signals patch based on Larent's review.
Thanks, I
On Wed, Jun 27, 2018 at 06:36:20PM -0700, Richard Henderson wrote:
> On 06/27/2018 04:08 PM, Stafford Horne wrote:
> > I am still getting failures on SMP, this time the kernel is jumping to some
> > unknown address, maybe an itlb issue, I will continue to debug. Bisecting
> > it is
> > exposing
Formalize the fleecing workflow in patch one,
test that it works in patch two.
V3:
- Added explicit zero checking as per Eblake's suggestion
- Remove stale python code
John Snow (2):
block: allow blockdev-backup from any source
iotests: add 222 to test basic fleecing
blockdev.c
In the case of image fleecing, the node we choose as the source
for a blockdev-backup is going to be both a root node AND the
backing node for the exported image. It does not qualify as a root
image in this case.
Loosen the restriction.
Signed-off-by: John Snow
Reviewed-by: Eric Blake
---
Signed-off-by: John Snow
---
tests/qemu-iotests/222 | 152 +
tests/qemu-iotests/222.out | 66
tests/qemu-iotests/group | 1 +
3 files changed, 219 insertions(+)
create mode 100644 tests/qemu-iotests/222
create mode
On 06/28/2018 02:05 PM, Eric Blake wrote:
> On 06/28/2018 01:00 PM, John Snow wrote:
>> In the case of image fleecing, the node we choose as the source
>> for a blockdev-backup is going to be both a root node AND the
>> backing node for the exported image. It does not qualify as a root
>> image
On 06/27/2018 03:41 PM, Zhang Chen wrote:
From: Zhang Chen
Suggested by Markus Armbruster rename COLO unknown mode to none mode.
Signed-off-by: Zhang Chen
---
migration/colo-failover.c | 2 +-
migration/colo.c | 2 +-
qapi/migration.json | 10 +-
3 files
We are gradually moving away from sector-based interfaces, towards
byte-based. Make the change for the internal helper function
get_cluster_offset(), by changing n_start and n_end to be byte
offsets rather than sector indices within the cluster being
allocated. However, assert that these values
My quest continues. I spent some time pruning sector-based usage
out of qcow as far as possible (and was dismayed at how long it
took to prove no iotests regressions); so for the other drivers, I
did the bare minimum to get rid of an interface, but will leave it
to those file owners if they want
On 28.06.2018 22:04, Paolo Bonzini wrote:
> From: David Hildenbrand
>
> Right now, there is some inconsistency between hotplugged and
> coldplugged memory. DIMMs added via "-device" result in different stats
> than DIMMs added using "device_add".
>
> E.g.
> [...]
> -numa
When a branch instructions points to itself, only external events will
change the internally observable cpu state. This change will adjust the
behaviour of QEMU such that it sends the emulated cpu into a sleep state
if this case is detected.
The effect for guests whose idle task contains this
On 06/28/2018 02:57 PM, Paolo Bonzini wrote:
Let management know if there were any problems communicating with
qemu-pr-helper. The event is edge-triggered, and is sent every time
the connection status of the pr-manager-helper object changes.
Is this something that guest actions can
From: Daniel Henrique Barboza
To add support for the emulation of Block Limits VPD page
for passthrough devices, a few adjustments in the current code
base is required to avoid repetition and improve clarity.
In scsi-generic.c, detach the Inquiry handling from
scsi_read_complete and put it into
We are gradually moving away from sector-based interfaces, towards
byte-based. Make the change for the last few sector-based calls
into the block layer from the vhdx driver.
Ideally, the vhdx driver should switch to doing everything
byte-based, but that's a more invasive change that requires a
We are gradually moving away from sector-based interfaces, towards
byte-based. Now that all callers of vectored I/O have been converted
to use our preferred byte-based bdrv_co_p{read,write}v(), we can
delete the unused bdrv_co_{read,write}v().
Furthermore, this gets rid of the signature
From: Viktor Prutyanov
Unlike dying Windows, live system memory doesn't contain
correct register contexts. But they can be populated with QEMU register
values.
After this patch, QEMU will be able to produce guest Windows live system
dump.
Signed-off-by: Viktor Prutyanov
Message-Id:
We are gradually moving away from sector-based interfaces, towards
byte-based. Make the change for the last few sector-based calls
into the block layer from the replication driver.
Ideally, the replication driver should switch to doing everything
byte-based, but that's a more invasive change
From: Peter Xu
People start to use "info pic" for all kinds of irqchip dumps. Let x86
ioapic join the family. It dumps the same thing as "info ioapic".
Signed-off-by: Peter Xu
Message-Id: <20171229073104.3810-3-pet...@redhat.com>
Signed-off-by: Paolo Bonzini
---
hw/intc/ioapic_common.c |
From: Thomas Huth
Peter reported that the boot-serial tester sometimes runs into timeouts
with SPARC guests. It's currently completely unclear whether this is due
to too much load on the host machine (so that the guest really just ran
too slow), or whether there is something wrong with the
We are gradually moving away from sector-based interfaces, towards
byte-based. Make the change for the internals of the qcow
driver read function, by iterating over offset/bytes instead of
sector_num/nb_sectors, and with a rename of index_in_cluster and
repurposing of n to track bytes instead of
From: Peter Xu
Something that commit 254316fa1f ("intc: make HMP 'info irq' and 'info
pic' commands available on all targets", 2016-10-04) forgot to touch up.
Signed-off-by: Peter Xu
Message-Id: <20171229073104.3810-2-pet...@redhat.com>
Signed-off-by: Paolo Bonzini
---
hmp-commands-info.hx |
From: Daniel Henrique Barboza
The VPD Block Limits Inquiry page is optional, allowing SCSI devices
to not implement it. This is the case for devices like the MegaRAID
SAS 9361-8i and Microsemi PM8069.
In case of SCSI passthrough, the response of this request is used by
the QEMU SCSI layer to
From: Viktor Prutyanov
KdDebuggerDataBlock may be encrypted in guest memory and dump will be
useless in this case. But guest driver can obtain decrypted KDBG and
expose its address through BugcheckParameter1 field in raw header.
After this patch, QEMU will be able to use fallback
From: Alexey Kardashevskiy
This adds owners/parents (which are the same, just occasionally
owner==NULL) printing for memory regions; a new '-o' flag
enabled new output.
Signed-off-by: Alexey Kardashevskiy
Message-Id: <20180604032511.6980-1-...@ozlabs.ru>
Signed-off-by: Paolo Bonzini
---
From: Viktor Prutyanov
This patch adds Windows crashdumping feature. Now QEMU can produce ELF-dump
containing Windows crashdump header, which can help to convert to a valid
WinDbg-understandable crashdump file, or immediately create such file.
The crashdump will be obtained by joining physical
We are gradually moving away from sector-based interfaces, towards
byte-based. The qcow driver is now ready to fully utilize the
byte-based callback interface, as long as we override the default
alignment to still be 512 (needed at least for asserts present
because of encryption, but easier to do
On 28 June 2018 at 20:23, Laurent Vivier wrote:
> Le 28/06/2018 à 15:23, Peter Maydell a écrit :
>> On 28 June 2018 at 14:03, Laurent Vivier wrote:
>>> Le 26/06/2018 à 18:56, Peter Maydell a écrit :
Add support for MMU protection regions that are smaller than
TARGET_PAGE_SIZE. We do
From: "Justin Terry (VM)"
Adds a workaround to an incorrect value setting
CPUID Fn8000_0001_ECX[bit 9 OSVW] = 1. This can cause a guest linux kernel
to panic when an issue to rdmsr C001_0140h returns 0. Disabling this feature
correctly allows the guest to boot without accessing the osv
We are gradually moving away from sector-based interfaces, towards
byte-based. Make the change for the internals of the qcow
driver write function, by iterating over offset/bytes instead of
sector_num/nb_sectors, and with a rename of index_in_cluster and
repurposing of n to track bytes instead of
From: Daniel Henrique Barboza
For the VPD Block Limits emulation with SCSI passthrough,
we'll issue an Inquiry request with EVPD set to retrieve
the available VPD pages of the device. This would be done in
a way similar of what scsi_generic_read_device_identification
does: create a SCSI command
From: "Michael S. Tsirkin"
When guest CPU PM is enabled, and with -cpu host, expose the host CPU
MWAIT leaf in the CPUID so guest can make good PM decisions.
Note: the result is 100% CPU utilization reported by host as host
no longer knows that the CPU is halted.
Signed-off-by: Michael S.
From: Peter Xu
So that now it looks better when with other irqchips.
Signed-off-by: Peter Xu
Message-Id: <20171229073104.3810-4-pet...@redhat.com>
Signed-off-by: Paolo Bonzini
---
hw/intc/ioapic_common.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
From: Mark Cave-Ayland
MIPS jazz is the last user of the legacy esp_init() function so move creation
of the ESP device over to use qdev.
Note that the esp_reset and dma_enable qemu_irqs are currently unused and so
we do not wire these up and instead remove the variables to prevent the
compiler
We are gradually moving away from sector-based interfaces, towards
byte-based. Make the change for the last few sector-based calls
into the block layer from the parallels driver.
Ideally, the parallels driver should switch to doing everything
byte-based, but that's a more invasive change that
From: Viktor Prutyanov
We use CPU #0 to access guest virtual memory, but it can execute user
thread at that moment. So, switch CR3 to PageDirectoryBase from header
and restore original value at the end.
Signed-off-by: Viktor Prutyanov
Message-Id:
Let management know if there were any problems communicating with
qemu-pr-helper. The event is edge-triggered, and is sent every time
the connection status of the pr-manager-helper object changes.
Signed-off-by: Paolo Bonzini
---
qapi/block.json | 24
From: Mark Cave-Ayland
Remove the legacy esp_init() function now that there are no more remaining
users.
Signed-off-by: Mark Cave-Ayland
Message-Id: <20180613094727.11326-3-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Paolo Bonzini
Tested-by: Hervé Poussineau
---
hw/scsi/esp.c | 30
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