"Michael S. Tsirkin" wrote:
> On Mon, Nov 26, 2018 at 08:59:53PM +0100, Juan Quintela wrote:
>> Hi
>>
>> V2:
>>
>> - Rebase on top of master
>>
>> Please review.
>>
>> Later, Juan.
>
> And just making sure the point is so that one
> can disable virtio-pci and still build virtio?
>
> And the
+-- On Mon, 19 Nov 2018, P J P wrote --+
| From: Prasad J Pandit
|
| The length parameter values are not negative, thus use an unsigned
| type 'size_t' for them. Many routines pass 'len' values to memcpy(3)
| calls. If it was negative, it could lead to memory corruption issues.
| Add check to
Stefan Weil wrote:
> These two patches fix wrong format strings used in disas/nanomips.
Stefan,
I truly appreciate your interest in nanoMIPS dissasembler.
In my opinion, this series comes too late in 3.1 development cycle to be
accepted. The described severity of undesired behavior is just way
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20181126153036.22414-1-fzig...@redhat.com
Subject: [Qemu-devel] [PATCH] spice: Use new SpiceImageCompression definition
Type: series
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
On Fri, Nov 16, 2018 at 11:57:15AM +0100, Cédric Le Goater wrote:
> This introduces a set of XIVE models specific to KVM which derive from
> the XIVE base models. The interfaces with KVM are a new capability and
> a new KVM device for the XIVE native exploitation interrupt mode.
>
> They handle
On Fri, Nov 16, 2018 at 11:57:14AM +0100, Cédric Le Goater wrote:
> Introduce a new sPAPR IRQ handler to handle resend after migration
> when the machine is using a KVM XICS interrupt controller model.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
> ---
>
- Original Message -
> From: "Markus Armbruster"
> To: qemu-devel@nongnu.org
> Cc: c...@redhat.com, f...@euphon.net, stefa...@redhat.com, pbonz...@redhat.com
> Sent: Tuesday, November 27, 2018 4:41:43 PM
> Subject: [PATCH for-3.1] vfio-helpers: Fix qemu_vfio_open_pci() crash
>
>
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 3 ---
tcg/tcg.c | 44 +---
2 files changed, 37 insertions(+), 10 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index b2e274b7af..ac5d01c223 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -1089,9 +1089,6 @@
On Tue, Nov 27, 2018 at 01:35:02PM +0100, Christophe Fergeau wrote:
> hey,
>
> On Mon, Nov 26, 2018 at 03:30:36PM +, Frediano Ziglio wrote:
> > Definitions were updated by spice-server in patch de66161 included
> > in 0.12.6 released on 12th June 2015.
>
> QEMU's configure only checks for
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 35 +++
1 file changed, 23 insertions(+), 12 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 27814df882..21668831a1 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2417,6 +2417,26 @@ static void
No need for a "tcg_" prefix for a static function; we already
have another "la_" prefix for indicating liveness analysis.
Pass in nb_globals and nb_temps, as we will already have them
in registers for other loops within the parent function.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 13
There are two blocks of the form
if (foo) {
stuff1;
goto bar;
} else {
baz:
stuff2;
}
which have unnecessary and confusing indentation.
Remove the else and unindent stuff2.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 139
With these preferences, we can arrange for function call arguments to
be computed into the proper registers instead of requiring extra moves.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 197 +-
1 file changed, 165 insertions(+), 32
Pass this through to tcg_reg_alloc.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index c596277fd0..7f29a2045a 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2859,7 +2859,7 @@ static void
Allocate storage for, but do not yet fill in, per-opcode
preferences for the output operands. Pass it in to the
register allocation routines for output operands.
Signed-off-by: Richard Henderson
---
tcg/tcg.h | 3 +++
tcg/tcg.c | 18 +++---
2 files changed, 14 insertions(+), 7
Pass this through to temp_sync.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 509e5974bd..c83ca238aa 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -3099,7 +3099,8 @@ static void
Try harder to honor the output_pref. When we're forced to allocate
a second register for the input, it does not need to use the input
constraint; that will be honored by the register we allocate for the
output and a move is already required.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 36
Pass this through to tcg_reg_alloc.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 7f29a2045a..509e5974bd 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2887,8 +2887,8 @@ static inline
The intent here is to remove several move insns putting the
function arguments into the proper place. I'm hoping that
this will solve the skylake regression with spec2006, as
seen with the ool softmmu patch set.
Emilio, all of this is present on my tcg-next-for-4.0 branch.
r~
Richard
This new argument will aid register allocation by indicating how
the temporary will be used in future. If the preference cannot
be satisfied, fall back to the constraints of the current insn.
Short circuit the preference when it cannot be satisfied or if
it does not further constrain the
Use this to notice the opcodes that exit the TB, which implies
that local temps are really dead and need not be synced.
Previously we so marked the true end of the TB, but that was
immediately overwritten by the la_bb_end invoked by any
TCG_OPF_BB_END opcode, like exit_tb.
Signed-off-by: Richard
On Tue, Nov 27, 2018 at 06:25:40PM +0800, Wei Wang wrote:
> On 11/27/2018 03:38 PM, Peter Xu wrote:
> > On Thu, Nov 15, 2018 at 06:08:01PM +0800, Wei Wang wrote:
> > > +typedef enum PrecopyNotifyReason {
> > > +PRECOPY_NOTIFY_ERR = 0,
> > > +PRECOPY_NOTIFY_START_ITERATION = 1,
> > > +
On Fri, Nov 16, 2018 at 11:57:13AM +0100, Cédric Le Goater wrote:
> The XIVE models for the QEMU and KVM accelerators will have a lot in
> common. Introduce an abstract class for the source, the thread context
> and the interrupt controller object to handle the differences in the
> object
On Fri, Nov 16, 2018 at 11:57:11AM +0100, Cédric Le Goater wrote:
> Each interrupt mode has its own specific interrupt presenter object,
> that we store under the CPU object, one for XICS and one for XIVE.
>
> Extend the sPAPR IRQ backend with a new handler to support them both.
>
>
On Fri, Nov 16, 2018 at 11:57:12AM +0100, Cédric Le Goater wrote:
> The interrupt mode is statically defined to XIVE only for this machine.
> The guest OS is required to have support for the XIVE exploitation
> mode of the POWER9 interrupt controller.
>
> Signed-off-by: Cédric Le Goater
> ---
>
On Fri, Nov 16, 2018 at 11:57:10AM +0100, Cédric Le Goater wrote:
> The XIVE interface for the guest is described in the device tree under
> the "interrupt-controller" node. A couple of new properties are
> specific to XIVE :
>
> - "reg"
>
>contains the base address and size of the thread
On Fri, Nov 16, 2018 at 11:57:09AM +0100, Cédric Le Goater wrote:
> The different XIVE virtualization structures (sources and event queues)
> are configured with a set of Hypervisor calls :
>
> - H_INT_GET_SOURCE_INFO
>
>used to obtain the address of the MMIO page of the Event State
>
Prepare for pvpanic-mmio configure interface.
Signed-off-by: Peng Hao
---
hw/arm/sysbus-fdt.c | 2 ++
hw/arm/virt.c | 2 ++
hw/misc/pvpanic.c | 11 +--
3 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/hw/arm/sysbus-fdt.c b/hw/arm/sysbus-fdt.c
index
Add configure interface for pvpanic-mmio. In qemu command line
use -device pvpanic-mmio to enable the device.
Signed-off-by: Peng Hao
---
hw/arm/virt-acpi-build.c | 5 -
hw/arm/virt.c| 7 +++
hw/misc/pvpanic.c| 1 +
3 files changed, 8 insertions(+), 5 deletions(-)
The first patches are simple cleanups:
- patch 1 move the pvpanic device with the 'ocmmon objects' so we compile
it once for the x86/arm/aarch64 archs,
- patch 2 simply renames ISA fields/definitions to generic ones.
Then instead of add/use the MMIO pvpanic device in
Add configure query interface for pvpanic-mmio.
Signed-off-by: Peng Hao
---
include/hw/misc/pvpanic.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h
index f1a05b2..dc042cf 100644
--- a/include/hw/misc/pvpanic.h
+++
Add pvpanic device in arm virt machine.
Signed-off-by: Peng Hao
---
default-configs/arm-softmmu.mak | 1 +
hw/arm/virt.c | 21 +
include/hw/arm/virt.h | 1 +
3 files changed, 23 insertions(+)
diff --git a/default-configs/arm-softmmu.mak
Add mmio support info in docs/specs/pvpanic.txt.
Signed-off-by: Peng Hao
---
docs/specs/pvpanic.txt | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/docs/specs/pvpanic.txt b/docs/specs/pvpanic.txt
index c7bbacc..b1beea3 100644
--- a/docs/specs/pvpanic.txt
+++
Add pvpanic device in virt acpi table, so when kenrel command line
uses acpi=force, kernel can get info from acpi table.
Signed-off-by: Peng Hao
---
hw/arm/virt-acpi-build.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
Add pvpanic new type "TYPE_PVPANIC_MMIO"
Signed-off-by: Peng Hao
---
hw/misc/pvpanic.c | 50 +++
include/hw/misc/pvpanic.h | 1 +
2 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
index
From: Philippe Mathieu-Daudé
To ease the MMIO device addition in the next patch, rename:
- ISA_PVPANIC_DEVICE -> PVPANIC_ISA_DEVICE.
- MemoryRegion io -> mr.
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Peng Hao
---
hw/misc/pvpanic.c | 28
1 file changed,
From: Philippe Mathieu-Daudé
The 'pvpanic' ISA device can be use by any machine with an ISA bus.
Reviewed-by: Peter Maydell
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Peng Hao
---
hw/misc/Makefile.objs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Fri, Nov 16, 2018 at 11:57:05AM +0100, Cédric Le Goater wrote:
> We will need to use xics_max_server_number() to create the sPAPRXive
> object modeling the interrupt controller of the machine which is
> created before the CPUs.
>
> Signed-off-by: Cédric Le Goater
My only concern here is that
On Fri, Nov 16, 2018 at 11:57:06AM +0100, Cédric Le Goater wrote:
> Initialize the MSI bitmap from it as this will be necessary for the
> sPAPR IRQ backend for XIVE.
>
> Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
> ---
> include/hw/ppc/spapr_irq.h | 1 +
> hw/ppc/spapr.c
On Fri, Nov 16, 2018 at 11:57:08AM +0100, Cédric Le Goater wrote:
> The XIVE IRQ backend uses the same layout as the new XICS backend but
> covers the full range of the IRQ number space. The IRQ numbers for the
> CPU IPIs are allocated at the bottom of this space, below 4K, to
> preserve
On Tue, Nov 27, 2018 at 05:27:49PM +0100, Igor Mammedov wrote:
> On Tue, 27 Nov 2018 16:42:18 +0100
> Samuel Ortiz wrote:
>
> > Hi Igor,
> >
> > On Tue, Nov 27, 2018 at 04:25:51PM +0100, Igor Mammedov wrote:
> > > On Mon, 26 Nov 2018 17:29:37 +0100
> > > Samuel Ortiz wrote:
> > >
> > > >
On Mon, Nov 26, 2018 at 08:59:53PM +0100, Juan Quintela wrote:
> Hi
>
> V2:
>
> - Rebase on top of master
>
> Please review.
>
> Later, Juan.
And just making sure the point is so that one
can disable virtio-pci and still build virtio?
And the point of that is mostly as a cleanup on
generic
On 11/27/18 8:41 PM, David Gibson wrote:
On Wed, Nov 28, 2018 at 01:32:21PM +1100, Benjamin Herrenschmidt wrote:
On Wed, 2018-11-28 at 11:13 +1100, David Gibson wrote:
Don't you need a cast to avoid (nsr << 8) being a shift-wider-than-size?
Shouldn't be a problem as long as it fits in an
Hi,
This series failed docker-quick@centos7 build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Message-id: 1543262162-6351-1-git-send-email-peng.h...@zte.com.cn
Subject: [Qemu-devel] [PATCH V9 0/9] add
Hi,
This series failed docker-mingw@fedora build test. Please find the testing
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.
Message-id: 1543262162-6351-1-git-send-email-peng.h...@zte.com.cn
Subject: [Qemu-devel] [PATCH V9 0/9] add pvpanic
On Wed, Nov 28, 2018 at 01:32:21PM +1100, Benjamin Herrenschmidt wrote:
> On Wed, 2018-11-28 at 11:13 +1100, David Gibson wrote:
> > Don't you need a cast to avoid (nsr << 8) being a shift-wider-than-size?
>
> Shouldn't be a problem as long as it fits in an int, no ?
I dunno, I can never
On Fri, Nov 16, 2018 at 11:57:04AM +0100, Cédric Le Goater wrote:
> The IVPE scans the O/S CAM line of the XIVE thread interrupt contexts
> to find a matching Notification Virtual Target (NVT) among the NVTs
> dispatched on the HW processor threads.
>
> On a real system, the thread interrupt
On Wed, 2018-11-28 at 10:49 +1100, David Gibson wrote:
> On Fri, Nov 16, 2018 at 11:57:01AM +0100, Cédric Le Goater wrote:
> > The last sub-engine of the XIVE architecture is the Interrupt
> > Virtualization Presentation Engine (IVPE). On HW, they share elements,
> > the Power Bus interface (CQ),
On Wed, 2018-11-28 at 11:13 +1100, David Gibson wrote:
> Don't you need a cast to avoid (nsr << 8) being a shift-wider-than-size?
Shouldn't be a problem as long as it fits in an int, no ?
Cheers,
Ben.
On Tue, Nov 27, 2018 at 14:06:57 -0500, Emilio G. Cota wrote:
> On Tue, Nov 27, 2018 at 14:48:11 +, Alex Bennée wrote:
> > With a little tweaking to the TCG we could then insert
> > our instrumentation at the end of the pass with all the knowledge we
> > want to export to the plugin.
>
>
On Wed, Nov 21, 2018 at 12:43:34AM -0500, Stefan Berger wrote:
> On 11/20/18 11:51 AM, Stefano Garzarella wrote:
> > On Tue, Nov 20, 2018 at 5:13 PM Steve Douthit
> > wrote:
> > > On 11/20/18 10:55 AM, Kevin O'Connor wrote:
> > > > FYI, this was raised a few months ago - see:
> > > >
> > > >
Hi, Palmer
On 11/28/18 8:34 AM, Palmer Dabbelt wrote:
On Mon, 26 Nov 2018 01:06:33 PST (-0800), Bastian Koppelmann wrote:
On 11/26/18 4:20 AM, Mao Zhongyi wrote:
Signed-off-by: Mao Zhongyi
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by:
On Tue, Nov 27, 2018 at 19:54:02 -0500, Emilio G. Cota wrote:
> To avoid altering the signature of .translate_insn, I've modified
> arm_ldl_code directly, as follows:
>
> uint32_t insn = cpu_ldl_code(env, addr);
> +
> if (bswap_code(sctlr_b)) {
> -return bswap32(insn);
> +
>From af4497f2b161bb4165acb8eee5cae3f2a7ea2227 Mon Sep 17 00:00:00 2001
From: John Arbuckle
Date: Tue, 27 Nov 2018 20:01:20 -0500
Subject: [PATCH] ui/cocoa.m: fix crash due to cocoa_refresh() on Mac OS 10.14
Mac OS 10.14 only wants UI code to be called from the main thread. The
cocoa_refresh()
On Fri, Nov 16, 2018 at 11:57:03AM +0100, Cédric Le Goater wrote:
> sPAPRXive models the XIVE interrupt controller of the sPAPR machine.
> It inherits from the XiveRouter and provisions storage for the routing
> tables :
>
> - Event Assignment Structure (EAS)
> - Event Notification Descriptor
On Mon, Nov 26, 2018 at 20:38:25 -0500, Emilio G. Cota wrote:
> On Mon, Nov 26, 2018 at 11:30:25 -0800, Richard Henderson wrote:
> > On 11/26/18 11:07 AM, Emilio G. Cota wrote:
> > > The main reason why I added the qemu_plugin_insn_append calls
> > > was to avoid reading the instructions twice
For a multiple cpu guest, during cpu 0 delete a memory sot then add it,
if cpu 1 write the memory address which belong to the deleted memory slot and
not exist in PTE,
kvm_mmu_page_fault fail, then return the QEMU with the reason KVM_EXIT_MMIO,
QEMU will also fail, What will happen in Guest?
On Tue, 27 Nov 2018 at 18:49, John Snow wrote:
>
> Some versions of Clang prior to 6.0 (and some builds of clang after,
> such as 6.0.1-2.fc28) fail to recognize { 0 } as a valid initializer
> for a struct with subobjects when -Wmissing-braces is enabled.
>
>
On Mon, 26 Nov 2018 01:06:33 PST (-0800), Bastian Koppelmann wrote:
On 11/26/18 4:20 AM, Mao Zhongyi wrote:
Signed-off-by: Mao Zhongyi
---
target/riscv/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Bastian Koppelmann
Shouldn't we also use
On Fri, Nov 16, 2018 at 11:57:01AM +0100, Cédric Le Goater wrote:
> The last sub-engine of the XIVE architecture is the Interrupt
> Virtualization Presentation Engine (IVPE). On HW, they share elements,
> the Power Bus interface (CQ), the routing table descriptors, and they
> can be combined in
Cast the kernel start address to the target bit length.
This ensures that we calculate the initrd offset to a valid address for
the architecture.
Signed-off-by: Alistair Francis
Suggested-by: Alexander Graf
Reported-by: Alexander Graf
---
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2
On Fri, Nov 16, 2018 at 11:57:02AM +0100, Cédric Le Goater wrote:
> After the event data was pushed in the O/S Event Queue, the IVPE
> raises the bit corresponding to the priority of the pending interrupt
> in the register IBP (Interrupt Pending Buffer) to indicate there is an
> event pending in
On Tue, Nov 27, 2018 at 08:30:15AM +0100, Cédric Le Goater wrote:
> On 11/27/18 1:11 AM, David Gibson wrote:
> > On Mon, Nov 26, 2018 at 10:39:44AM +0100, Cédric Le Goater wrote:
> >> On 11/26/18 6:44 AM, David Gibson wrote:
> >>> On Fri, Nov 23, 2018 at 11:28:24AM +0100, Cédric Le Goater wrote:
>
On Tue, Nov 27, 2018 at 02:04:53PM +0100, Greg Kurz wrote:
> As explained in HACKING, the g_malloc(sizeof(T) * n) construct is unsafe
> because it can't detect multiplication overflowing size_t and doesn't
> allow type checking.
>
> It appears to be used in a bunch of places though:
>
> $ git
No, that is not something that QEMU supports. There is no such thing as
a "generic arm board". All arm boards are different hardware, and we
model only a few boards. We don't provide "put together your own model
from building blocks" functionality, I'm afraid, and it's unlikely we
ever will in
On Tue, 27 Nov 2018 at 19:00, Paolo Bonzini wrote:
>
> The following changes since commit 4822f1ee9efa8df56e29db0a68323b484bdb0335:
>
> Merge remote-tracking branch
> 'remotes/kraxel/tags/fixes-31-20181127-pull-request' into staging (2018-11-27
> 11:21:38 +)
>
>
On Tue, Nov 27, 2018 at 15:43:52 +0300, Roman Bolshakov wrote:
> ld64 on macOS has similar -exported_symbols_list option. Here's the reference:
>
> -exported_symbols_list filename
> The specified filename contains a list of global symbol names
> that will remain as global symbols
On 11/27/18 6:41 AM, Andrey Shinkevich wrote:
The 'Format specific information' of qemu-img info command will show
the name, flags and granularity for every QCOW2 bitmap.
Signed-off-by: Andrey Shinkevich
---
Dear colleagues,
With this patch, qemu-img info will display a name, flags and
On 27.11.18 23:28, Alistair Francis wrote:
> On Tue, Nov 27, 2018 at 2:24 PM Alistair Francis wrote:
>>
>> On Tue, Nov 27, 2018 at 2:12 PM Alexander Graf wrote:
>>>
>>>
>>>
>>> On 27.11.18 23:05, Alistair Francis wrote:
On Mon, Nov 26, 2018 at 11:02 AM Palmer Dabbelt wrote:
>
>
** Description changed:
Hello, i have a big problem with QEMU arm virtual machine. So...
I run QEMU machine with bare-metal ThreadX fullflash from Texet TM-333 phone
(Spreadtrum platform)
[CODE]qemu-system-arm -S -gdb tcp::1234,ipv4 -drive
On Tue, Nov 27, 2018 at 2:24 PM Alistair Francis wrote:
>
> On Tue, Nov 27, 2018 at 2:12 PM Alexander Graf wrote:
> >
> >
> >
> > On 27.11.18 23:05, Alistair Francis wrote:
> > > On Mon, Nov 26, 2018 at 11:02 AM Palmer Dabbelt wrote:
> > >>
> > >> On Wed, 21 Nov 2018 18:09:27 PST (-0800),
On Tue, Nov 27, 2018 at 2:12 PM Alexander Graf wrote:
>
>
>
> On 27.11.18 23:05, Alistair Francis wrote:
> > On Mon, Nov 26, 2018 at 11:02 AM Palmer Dabbelt wrote:
> >>
> >> On Wed, 21 Nov 2018 18:09:27 PST (-0800), alistai...@gmail.com wrote:
> >>> On Wed, Nov 21, 2018 at 5:58 PM Palmer Dabbelt
On 27.11.18 23:05, Alistair Francis wrote:
> On Mon, Nov 26, 2018 at 11:02 AM Palmer Dabbelt wrote:
>>
>> On Wed, 21 Nov 2018 18:09:27 PST (-0800), alistai...@gmail.com wrote:
>>> On Wed, Nov 21, 2018 at 5:58 PM Palmer Dabbelt wrote:
On Wed, 21 Nov 2018 14:34:44 PST (-0800),
On Mon, Nov 26, 2018 at 11:02 AM Palmer Dabbelt wrote:
>
> On Wed, 21 Nov 2018 18:09:27 PST (-0800), alistai...@gmail.com wrote:
> > On Wed, Nov 21, 2018 at 5:58 PM Palmer Dabbelt wrote:
> >>
> >> On Wed, 21 Nov 2018 14:34:44 PST (-0800), Alistair Francis wrote:
> >> > Ensure that the calculate
Maybe this is correct for palmetto-board, but qemu user should be able
to debug any basic arm instructions for generic arm board with general
purpose SPI, I2C etc... My SPI Flash has 4 Mb, and RAM adress may start
from 0x40, This is impossible for 256 Mb Flash. It would be great,
if qemu can
On Tue, Nov 27, 2018 at 1:06 PM Alistair Francis
wrote:
It looks like the cover was lost, here it is:
This patch set adds RISC-V backend support to QEMU. This is based on
Michael Clark's original work with some patches ontop.
This has been slightly tested and can run other architecture softmmu
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
tcg/riscv/tcg-target.inc.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 51961ade81..13756f6d0d 100644
---
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
tcg/riscv/tcg-target.inc.c | 162 -
1 file changed, 158 insertions(+), 4 deletions(-)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 4f3a6de52c..e3b5f48848 100644
Signed-off-by: Alistair Francis
---
tcg/riscv/tcg-target.inc.c | 44 +++---
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index b8e9c0e126..cf1680935a 100644
--- a/tcg/riscv/tcg-target.inc.c
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
configure | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/configure b/configure
index 0a3c6a72c3..fb52954368 100755
--- a/configure
+++ b/configure
@@ -709,6
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
tcg/riscv/tcg-target.inc.c | 244 +
1 file changed, 244 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 97831bfb9d..4f3a6de52c 100644
---
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
tcg/riscv/tcg-target.inc.c | 78 ++
1 file changed, 78 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 9c48679f11..e5a07b146f 100644
---
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
tcg/riscv/tcg-target.inc.c | 111 +
1 file changed, 111 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index d5fd7ca854..51961ade81 100644
---
Signed-off-by: Alistair Francis
---
tcg/riscv/tcg-target.inc.c | 77 ++
1 file changed, 77 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 13756f6d0d..b8e9c0e126 100644
--- a/tcg/riscv/tcg-target.inc.c
+++
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
accel/tcg/user-exec.c | 75 +++
1 file changed, 75 insertions(+)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index cd75829cf2..941295ea49 100644
--- a/accel/tcg/user-exec.c
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
tcg/riscv/tcg-target.inc.c | 40 ++
1 file changed, 40 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
disas.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/disas.c b/disas.c
index 5325b7e6be..82a408f272 100644
--- a/disas.c
+++ b/disas.c
@@ -522,8 +522,14 @@ void
Initialize the generic timer scale factor based on the counter frequency
register cntfrq_el0, and default to the current static value if necessary.
Always use the default value for TCG.
Signed-off-by: Bijan Mottahedeh
---
hw/arm/virt.c | 17 +
target/arm/helper.c|
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
tcg/riscv/tcg-target.inc.c | 60 ++
1 file changed, 60 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
tcg/riscv/tcg-target.inc.c | 472 +
1 file changed, 472 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
tcg/riscv/tcg-target.inc.c | 141 +
1 file changed, 141 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index cac4a4b615..97831bfb9d 100644
---
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
tcg/riscv/tcg-target.inc.c | 51 ++
1 file changed, 51 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index ca7ae8939a..9c48679f11 100644
---
v1 -> v2:
- Call the asm code only for kvm and always use the default value for TCG.
This patch series address two Qemu issues:
- improper system clock frequency initialization
- lack of pause (virtsh suspend) time accounting
A simple test to reproduce the problem executes one or more
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
tcg/riscv/tcg-target.inc.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index
On 11/27/18 2:02 PM, Eric Blake wrote:
> On 11/27/18 12:49 PM, John Snow wrote:
>> Some versions of Clang prior to 6.0 (and some builds of clang after,
>> such as 6.0.1-2.fc28) fail to recognize { 0 } as a valid initializer
>> for a struct with subobjects when -Wmissing-braces is enabled.
>>
>>
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
tcg/riscv/tcg-target.h | 173 +
1 file changed, 173 insertions(+)
create mode 100644 tcg/riscv/tcg-target.h
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
new file mode
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
tcg/riscv/tcg-target.inc.c | 105 +
1 file changed, 105 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 5719af3c08..c659c4de39 100644
---
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
tcg/riscv/tcg-target.inc.c | 116 +
1 file changed, 116 insertions(+)
create mode 100644 tcg/riscv/tcg-target.inc.c
diff --git a/tcg/riscv/tcg-target.inc.c
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
---
tcg/riscv/tcg-target.inc.c | 138 +
1 file changed, 138 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index a4a1579440..5719af3c08 100644
---
Signed-off-by: Alistair Francis
Signed-off-by: Michael Clark
Reviewed-by: Richard Henderson
---
include/exec/poison.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 32d53789f8..ecdc83c147 100644
--- a/include/exec/poison.h
+++
1 - 100 of 403 matches
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