On 12/10/18 7:39 AM, David Gibson wrote:
> On Sun, Dec 09, 2018 at 08:46:00PM +0100, Cédric Le Goater wrote:
>> The XIVE interface for the guest is described in the device tree under
>> the "interrupt-controller" node. A couple of new properties are
>> specific to XIVE :
>>
>> - "reg"
>>
>>
Hello all,
On 12/7/18 4:59 PM, Peter Maydell wrote:
> Jaap: could you test whether this patch fixes the issue you
> were seeing, please?
My test is going very well. With the patch applied, I have no longer been able
to freeze/hang the VM. Currently at 7024 reboots and counting over
runtime 1
Queued, thanks!
On 12/10/18 7:42 AM, David Gibson wrote:
> On Sun, Dec 09, 2018 at 08:46:03PM +0100, Cédric Le Goater wrote:
>> For the time being, the XIVE reset handler updates the OS CAM line of
>> the vCPU as it is done under a real hypervisor when a vCPU is
>> scheduled to run on a HW thread.
>>
>> This
Marc-André Lureau writes:
> Hi
> On Thu, Dec 6, 2018 at 9:42 PM Markus Armbruster wrote:
>>
>> Marc-André Lureau writes:
>>
>> > Wrap generated enum/struct members and code with #if/#endif, using the
>>
>> enum and struct members
>
> ok
>
>>
>> > .ifcond members added in the previous patches.
On 12/10/18 5:27 AM, David Gibson wrote:
> On Sun, Dec 09, 2018 at 08:45:54PM +0100, Cédric Le Goater wrote:
>> The last sub-engine of the XIVE architecture is the Interrupt
>> Virtualization Presentation Engine (IVPE). On HW, the IVRE and the
>> IVPE share elements, the Power Bus interface (CQ),
On 12/10/18 5:16 AM, David Gibson wrote:
> On Sun, Dec 09, 2018 at 08:45:52PM +0100, Cédric Le Goater wrote:
>> The Event Notification Descriptor (END) XIVE structure also contains
>> two Event State Buffers providing further coalescing of interrupts,
>> one for the notification event (ESn) and
On 12/10/18 4:41 AM, David Gibson wrote:
> On Mon, Dec 10, 2018 at 09:05:06AM +1100, Benjamin Herrenschmidt wrote:
>> On Sun, 2018-12-09 at 20:46 +0100, Cédric Le Goater wrote:
>>> Signed-off-by: Cédric Le Goater
>>> ---
>>
>> If you're going to do that, can we include large decrementer in there
On Sun, Dec 09, 2018 at 08:46:03PM +0100, Cédric Le Goater wrote:
> For the time being, the XIVE reset handler updates the OS CAM line of
> the vCPU as it is done under a real hypervisor when a vCPU is
> scheduled to run on a HW thread.
>
> This handler will become even more useful when we
On Sun, Dec 09, 2018 at 08:46:08PM +0100, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
Applied, since we'll need something like this sooner or later anyway.
I may have conflicts to resolve since I think a patch including a
similar chage is in someone else's tree, but it shouldn't be
On Sun, Dec 09, 2018 at 08:45:59PM +0100, Cédric Le Goater wrote:
> The different XIVE virtualization structures (sources and event queues)
> are configured with a set of Hypervisor calls :
>
> - H_INT_GET_SOURCE_INFO
>
>used to obtain the address of the MMIO page of the Event State
>
On Sun, Dec 09, 2018 at 08:46:00PM +0100, Cédric Le Goater wrote:
> The XIVE interface for the guest is described in the device tree under
> the "interrupt-controller" node. A couple of new properties are
> specific to XIVE :
>
> - "reg"
>
>contains the base address and size of the thread
Eduardo Habkost writes:
> On Thu, Dec 06, 2018 at 07:59:02AM +0100, Markus Armbruster wrote:
>> Daniel Henrique Barboza writes:
>>
>> > changes in v11:
>> > - fixed typos, changed version to 4.0 in patches 1 and 3
>> > - changed text in patch 2 to be less alarming
>> > - patch 3: changed error
Hi,
> #3 0x701be412 in __GI___assert_fail (assertion=0x55fb8738
> "p->actual_length + bytes <= iov->size", file=0x55fb8456
> "hw/usb/core.c", line=592, function=0x55fb8980
> <__PRETTY_FUNCTION__.26351> "usb_packet_copy") at assert.c:101
> #4 0x55bd5ed7 in
On Mon, Nov 12, 2018 at 03:12:26PM +1100, Alexey Kardashevskiy wrote:
>
>
> On 12/11/2018 05:10, Greg Kurz wrote:
> > Hi Alexey,
> >
> > Just a few remarks. See below.
> >
> > On Thu, 8 Nov 2018 12:44:06 +1100
> > Alexey Kardashevskiy wrote:
> >
> >> SLOF receives a device tree and updates
On Sun, Dec 09, 2018 at 08:45:56PM +0100, Cédric Le Goater wrote:
> sPAPRXive models the XIVE interrupt controller of the sPAPR machine.
> It inherits from the XiveRouter and provisions storage for the routing
> tables :
>
> - Event Assignment Structure (EAS)
> - Event Notification Descriptor
On Sun, Dec 09, 2018 at 08:45:58PM +0100, Cédric Le Goater wrote:
> The XIVE IRQ backend uses the same layout as the new XICS backend but
> covers the full range of the IRQ number space. The IRQ numbers for the
> CPU IPIs are allocated at the bottom of this space, below 4K, to
> preserve
On Sun, Dec 09, 2018 at 08:45:52PM +0100, Cédric Le Goater wrote:
> The Event Notification Descriptor (END) XIVE structure also contains
> two Event State Buffers providing further coalescing of interrupts,
> one for the notification event (ESn) and one for the escalation events
> (ESe). A MMIO
On Fri, Dec 07, 2018 at 04:08:05PM +, Mark Cave-Ayland wrote:
> This is in preparation for some upcoming QEMU NDRV driver changes that pass
> display information from the host to the guest.
>
> Signed-off-by: Mark Cave-Ayland
This looks fine by my limited knowledge of this area. I'm
On Fri, Dec 07, 2018 at 08:56:30AM +, Mark Cave-Ayland wrote:
> These helpers allow us to move FP register values to/from the specified
> TCGv_i64
> argument.
>
> To prevent FP helpers accessing the cpu_fpr array directly, add extra TCG
> temporaries as required.
It's not obvious to me why
On Sun, Dec 09, 2018 at 08:45:57PM +0100, Cédric Le Goater wrote:
> The IVPE scans the O/S CAM line of the XIVE thread interrupt contexts
> to find a matching Notification Virtual Target (NVT) among the NVTs
> dispatched on the HW processor threads.
>
> On a real system, the thread interrupt
On Sun, Dec 09, 2018 at 08:45:54PM +0100, Cédric Le Goater wrote:
> The last sub-engine of the XIVE architecture is the Interrupt
> Virtualization Presentation Engine (IVPE). On HW, the IVRE and the
> IVPE share elements, the Power Bus interface (CQ), the routing table
> descriptors, and they can
On Sun, Dec 09, 2018 at 08:45:53PM +0100, Cédric Le Goater wrote:
> Each POWER9 processor chip has a XIVE presenter that can generate four
> different exceptions to its threads:
>
> - hypervisor exception,
> - O/S exception
> - Event-Based Branch (EBB)
> - msgsnd (doorbell).
>
> Each
On Mon, Dec 10, 2018 at 09:05:06AM +1100, Benjamin Herrenschmidt wrote:
> On Sun, 2018-12-09 at 20:46 +0100, Cédric Le Goater wrote:
> > Signed-off-by: Cédric Le Goater
> > ---
>
> If you're going to do that, can we include large decrementer in there
> too ? (patches from Suraj in my tree but
Thank you all for help with my last patch. I found one more entry in my
notes that could be a bug, or could be a misunderstanding on my part.
The memory map in DocID15818 (Rev 15) datasheet says:
ADC1 - ADC2 - ADC3: 0x40012000-0x400123FF
That suggests a size of 0x400 (they share that
On 12/5/18 1:16 AM, Paolo Bonzini wrote:
On 04/12/18 16:49, Christophe de Dinechin wrote:
Linux and QEMU's own qht work just fine with compile-time directives.
Wouldn’t it work fine without any compile-time directive at all?
Yes, that's what I meant. Though there are certainly cases
On Sat, Dec 08, 2018 at 11:58:59AM +, xuyandong wrote:
> > Hi all,
> >
> >
> >
> > In our test, we configured VM with several pci-bridges and a
> > virtio-net nic been attached with bus 4,
> >
> > After VM is startup, We ping this nic from host to judge if it is
> > working normally. Then, we
On Fri, Dec 07, 2018 at 09:49:29AM +0100, Cédric Le Goater wrote:
> On 12/7/18 4:10 AM, David Gibson wrote:
> > On Thu, Dec 06, 2018 at 12:22:22AM +0100, Cédric Le Goater wrote:
> >> The last sub-engine of the XIVE architecture is the Interrupt
> >> Virtualization Presentation Engine (IVPE). On
On Fri, Dec 07, 2018 at 08:49:21AM +0100, Cédric Le Goater wrote:
> On 12/7/18 2:57 AM, David Gibson wrote:
> > On Thu, Dec 06, 2018 at 07:22:54AM +0100, Cédric Le Goater wrote:
> >> On 12/6/18 4:41 AM, David Gibson wrote:
> >>> On Thu, Dec 06, 2018 at 12:22:18AM +0100, Cédric Le Goater wrote:
>
On Mon, Dec 10, 2018 at 01:33:53AM +0100, BALATON Zoltan wrote:
> On Fri, 7 Dec 2018, Mark Cave-Ayland wrote:
> > This patchset is an attempt at trying to improve the VMX (Altivec)
> > instruction
> > performance by making use of the new TCG vector operations where possible.
>
> This is very
On Fri, Dec 07, 2018 at 03:13:14PM -0200, Leonardo Bras wrote:
> From: "Paul A. Clarke"
>
> Changes requirement for "vsubsbs" instruction, which has been supported
> since ISA 2.03. (Please see section 5.9.1.2 of ISA 2.03)
>
> Reported-by: Paul A. Clarke
> Signed-off-by: Paul A. Clarke
>
On Fri, Dec 07, 2018 at 04:08:04PM +, Mark Cave-Ayland wrote:
> I've unofficially been doing most of the work on the Mac machines for a while
> now, so update MAINTAINERS to reflect this. David is still happy to be listed
> as a reviewer as per our discussion at KVM forum.
>
> Signed-off-by:
On Sat, Dec 08, 2018 at 11:58:59AM +, xuyandong wrote:
> Hi all,
>
>
>
> In our test, we configured VM with several pci-bridges and a virtio-net nic
> been attached with bus 4,
>
> After VM is startup, We ping this nic from host to judge if it is working
> normally. Then, we hot add pci
n Sat, Dec 08, 2018 at 11:58:59AM +, xuyandong wrote:
> > Hi all,
> >
> >
> >
> > In our test, we configured VM with several pci-bridges and a
> > virtio-net nic been attached with bus 4,
> >
> > After VM is startup, We ping this nic from host to judge if it is
> > working normally. Then, we
On Fri, Dec 07, 2018 at 05:14:17PM -0500, Wainer dos Santos Moschetta wrote:
> The x86_cpu_class_check_missing_features() returns a list
> of unavailable features compared to the host CPU. Currently it may
> return empty strings for unamed features as well as duplicated
> names.
>
> For example,
On Fri, 7 Dec 2018, Mark Cave-Ayland wrote:
This patchset is an attempt at trying to improve the VMX (Altivec) instruction
performance by making use of the new TCG vector operations where possible.
This is very welcome, thanks for doing this.
In order to use TCG vector operations, the
On Fri, Dec 07, 2018 at 18:41:07 -0200, Eduardo Habkost wrote:
> I've noticed QEMU Travis builds are failing recently, and they
> seem to happen only on the --enable-gprof jobs. I have enabled
> V=1 and noticed that the jobs are hanging inside test-qht-par.
>
> Example here (look for
On Sun, 2018-12-09 at 20:46 +0100, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater
> ---
If you're going to do that, can we include large decrementer in there
too ? (patches from Suraj in my tree but they night need a bit of
massaging).
> include/hw/compat.h | 3 +++
>
On Fri, 7 Dec 2018 at 18:00, Richard Henderson
wrote:
>
> On 12/5/18 9:32 AM, Aaron Lindsay wrote:
> > On Dec 05 08:43, Aaron Lindsay wrote:
> >> Signed-off-by: Aaron Lindsay
> >> +if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4) {
> >
> > After further discussion on my last version,
I was seeing this problem when my Debian laptop suspended. The CentOS
guest would begin consuming a lot of cpu and only a hard-reset would fix
it.
Changing the rtc line to
seems to have fixed it, though I haven't done extensive testing yet.
Thanks!
--
You received this bug
This pseries machine makes use of a new sPAPR IRQ backend supporting
both interrupt modes : XIVE and XICS, the default being XICS.
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index
Cc'ing Alberto
On 12/7/18 6:09 PM, Richard Henderson wrote:
> This covers inc, dec, and the bit test instructions.
>
> I believe we've finally covered all of the cases for
> which we have an atomic path that would use the cpu_A0
> temp, which is only initialized for address sources.
>
Hi Alberto,
Can you open another ticket for your new bug?
Thanks.
On Fri, Dec 7, 2018 at 6:22 PM Richard Henderson wrote:
>
> This second crash is of course a different bug.
>
> --
> You received this bug notification because you are a member of qemu-
> devel-ml, which is subscribed to QEMU.
>
Depending on the interrupt mode chosen, enable or disable the XIVE
MMIOs.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/spapr_xive.h | 1 +
hw/intc/spapr_xive.c| 9 +
hw/ppc/spapr_irq.c | 8
3 files changed, 18 insertions(+)
diff --git
Signed-off-by: Cédric Le Goater
---
include/hw/compat.h | 3 +++
hw/ppc/spapr.c | 25 ++---
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/include/hw/compat.h b/include/hw/compat.h
index 6f4d5fc64704..70958328fe7a 100644
--- a/include/hw/compat.h
+++
The different XIVE virtualization structures (sources and event queues)
are configured with a set of Hypervisor calls :
- H_INT_GET_SOURCE_INFO
used to obtain the address of the MMIO page of the Event State
Buffer (ESB) entry associated with the source.
- H_INT_SET_SOURCE_CONFIG
The interrupt mode is chosen by the CAS negotiation process and
activated after a reset to take into account the required changes in
the machine. These impact the device tree layout, the interrupt
presenter object and the exposed MMIO regions in the case of XIVE.
This default interrupt mode for
For the time being, the XIVE reset handler updates the OS CAM line of
the vCPU as it is done under a real hypervisor when a vCPU is
scheduled to run on a HW thread.
This handler will become even more useful when we introduce the
machine supporting both interrupt modes, XIVE and XICS. In this
Each interrupt mode has its own specific interrupt presenter object,
that we store under the CPU object, one for XICS and one for XIVE.
Extend the sPAPR IRQ backend with a new handler to support them both.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
Changes since v6:
-
Introduce a new sPAPR IRQ handler to handle resend after migration
when the machine is using a KVM XICS interrupt controller model.
Signed-off-by: Cédric Le Goater
Reviewed-by: David Gibson
---
include/hw/ppc/spapr_irq.h | 2 ++
hw/ppc/spapr.c | 13 +
The IVPE scans the O/S CAM line of the XIVE thread interrupt contexts
to find a matching Notification Virtual Target (NVT) among the NVTs
dispatched on the HW processor threads.
On a real system, the thread interrupt contexts are updated by the
hypervisor when a Virtual Processor is scheduled to
The last sub-engine of the XIVE architecture is the Interrupt
Virtualization Presentation Engine (IVPE). On HW, the IVRE and the
IVPE share elements, the Power Bus interface (CQ), the routing table
descriptors, and they can be combined in the same HW logic. We do the
same in QEMU and combine both
The XIVE interface for the guest is described in the device tree under
the "interrupt-controller" node. A couple of new properties are
specific to XIVE :
- "reg"
contains the base address and size of the thread interrupt
managnement areas (TIMA), for the User level and for the Guest OS
sPAPRXive models the XIVE interrupt controller of the sPAPR machine.
It inherits from the XiveRouter and provisions storage for the routing
tables :
- Event Assignment Structure (EAS)
- Event Notification Descriptor (END)
The sPAPRXive model incorporates an internal XiveSource for the IPIs
The XIVE IRQ backend uses the same layout as the new XICS backend but
covers the full range of the IRQ number space. The IRQ numbers for the
CPU IPIs are allocated at the bottom of this space, below 4K, to
preserve compatibility with XICS which does not use that range.
This should be enough given
The Event Notification Descriptor (END) XIVE structure also contains
two Event State Buffers providing further coalescing of interrupts,
one for the notification event (ESn) and one for the escalation events
(ESe). A MMIO page is assigned for each to control the EOI through
loads only. Stores are
This pseries machine makes use of a new sPAPR IRQ backend supporting
the XIVE interrupt mode.
The guest OS is required to have support for the XIVE exploitation
mode of the POWER9 interrupt controller.
Signed-off-by: Cédric Le Goater
---
hw/ppc/spapr.c | 15 +++
1 file changed, 15
Hello,
Here is the version 7 of the QEMU models adding support for the XIVE
interrupt controller to the sPAPR machine, under TCG only this
time. KVM support will be proposed in an other patchset, along with
the KVM XIVE device patchset, and so will PowerNV.
The most important changes for sPAPR
Pass arguments with -plugin=libfoo.so,arg=bar,arg=baz
Signed-off-by: Emilio G. Cota
---
configure | 4 +-
tests/plugin/bb.c | 66 ++
tests/plugin/empty.c | 30 ++
tests/plugin/insn.c | 63 +
Signed-off-by: Emilio G. Cota
---
target/xtensa/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 46e1338448..c140742562 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -882,7
Signed-off-by: Emilio G. Cota
---
target/i386/translate.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 83c1ebe491..6ea784da54 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -1900,28
Each POWER9 processor chip has a XIVE presenter that can generate four
different exceptions to its threads:
- hypervisor exception,
- O/S exception
- Event-Based Branch (EBB)
- msgsnd (doorbell).
Each exception has a state independent from the others called a Thread
Interrupt Management
Currently, the interrupt presenter of the vCPU is set at realize
time. Setting it at reset will become useful when the new machine
supporting both interrupt modes is introduced. In this machine, the
interrupt mode is chosen at CAS time and activated after a reset.
Signed-off-by: Cédric Le Goater
Signed-off-by: Emilio G. Cota
---
target/m68k/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index d55e707cf6..71263f8b37 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -373,7 +373,7 @@
This field defines the interrupt modes supported by the hypervisor in
the "ibm,arch-vec-5-platform-support" property. The CAS negotiation
process will select which mode to use.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/spapr.h | 6 ++
include/hw/ppc/spapr_irq.h | 1 +
Signed-off-by: Emilio G. Cota
---
target/openrisc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index a271cd3903..6b5efc0155 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@
Signed-off-by: Emilio G. Cota
---
accel/tcg/translator.c | 16
1 file changed, 16 insertions(+)
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index afd0a49ea6..68174a2986 100644
--- a/accel/tcg/translator.c
+++ b/accel/tcg/translator.c
@@ -17,6 +17,7 @@
#include
Add support for both ld (using --dynamic-list) and MacOSX's ld64
(-exported_symbols_list).
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
configure | 82 +
Makefile| 1 +
Makefile.target | 18 ++-
.gitignore
From: Lluís Vilanova
Signed-off-by: Lluís Vilanova
[ cota: s/instrument/plugin ]
Signed-off-by: Emilio G. Cota
---
linux-user/main.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/linux-user/main.c b/linux-user/main.c
index 923cbb753a..482766f0f4 100644
---
After the event data was enqueued in the O/S Event Queue, the IVPE
raises the bit corresponding to the priority of the pending interrupt
in the register IBP (Interrupt Pending Buffer) to indicate there is an
event pending in one of the 8 priority queues. The Pending Interrupt
Priority Register
We first inject empty instrumentation from translator_loop.
After translation, we go through the plugins to see what
they want to register for, filling in the empty instrumentation.
If if turns out that some instrumentation remains unused, we
remove it.
This approach supports the following
Signed-off-by: Emilio G. Cota
---
target/hppa/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index df9179e70f..806dbda51f 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -4754,7 +4754,7 @@
From: Lluís Vilanova
Signed-off-by: Lluís Vilanova
[ cota: s/instrument/plugin ]
Signed-off-by: Emilio G. Cota
---
vl.c| 11 +++
qemu-options.hx | 17 +
2 files changed, 28 insertions(+)
diff --git a/vl.c b/vl.c
index 1fcacc5caa..a1d6b76315 100644
---
Signed-off-by: Emilio G. Cota
---
target/sparc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 74315cdf09..2c754b6163 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5900,7 +5900,7
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
bsd-user/syscall.c | 3 +++
linux-user/exit.c | 1 +
2 files changed, 4 insertions(+)
diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c
index 66492aaf5d..b7818af450 100644
--- a/bsd-user/syscall.c
+++ b/bsd-user/syscall.c
@@ -332,6
XXX: store hostaddr from non-i386 TCG backends
XXX: what hostaddr to return for I/O accesses?
XXX: what hostaddr to return for cross-page accesses?
Here the trickiest feature is passing the host address to
memory callbacks that request it. Perhaps it would be more
appropriate to pass a "physical"
Signed-off-by: Emilio G. Cota
---
qemu-plugins.symbols | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 qemu-plugins.symbols
diff --git a/qemu-plugins.symbols b/qemu-plugins.symbols
new file mode 100644
index 00..2a5b18862a
--- /dev/null
+++
I considered using translator_ld* from arm_ldl_code
et al. However, note that there's a helper that also calls
arm_ldl_code, so we'd have to change that caller.
In thumb's case I'm also calling plugin_insn_append directly,
since we can't assume that all instructions are 16 bits long.
Signed-off-by: Emilio G. Cota
---
target/riscv/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 18d7b6d147..fa96f45a69 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1848,7 +1848,7
Signed-off-by: Emilio G. Cota
---
bsd-user/syscall.c | 9 +
linux-user/syscall.c | 3 +++
2 files changed, 12 insertions(+)
diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c
index b7818af450..4993f81b2b 100644
--- a/bsd-user/syscall.c
+++ b/bsd-user/syscall.c
@@ -323,6 +323,8 @@
XXX: cleanly get the gUSA instructions
Signed-off-by: Emilio G. Cota
---
target/sh4/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index ab254b0e8d..1704ce8dae 100644
--- a/target/sh4/translate.c
+++
In preparation for plugin support.
Signed-off-by: Emilio G. Cota
---
accel/tcg/atomic_template.h | 110
1 file changed, 75 insertions(+), 35 deletions(-)
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index 8d177fefef..2f7d5ee02a
Signed-off-by: Emilio G. Cota
---
target/alpha/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 25cd95931d..f8d194994a 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2987,7 +2987,7
Plugins might allocate per-TB data that then they get passed each
time a TB is executed (via the *userdata pointer).
Notify plugin code every time a code cache flush occurs, so
that plugins can then reclaim the memory of the per-TB data.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
Signed-off-by: Emilio G. Cota
---
cpus.c| 10 ++
exec.c| 2 ++
qom/cpu.c | 2 ++
3 files changed, 14 insertions(+)
diff --git a/cpus.c b/cpus.c
index c9acef73e4..e3844c69c8 100644
--- a/cpus.c
+++ b/cpus.c
@@ -43,6 +43,7 @@
#include "exec/exec-all.h"
#include
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
accel/tcg/atomic_template.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h
index efde12fdb2..8d177fefef 100644
--- a/accel/tcg/atomic_template.h
+++
It's unused.
Signed-off-by: Emilio G. Cota
---
tcg/tcg.h | 4 ++--
tcg/optimize.c | 4 ++--
tcg/tcg.c | 10 --
3 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index f4efbaa680..a745e926bb 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -1073,8
Suggested-by: Richard Henderson
Signed-off-by: Emilio G. Cota
---
include/exec/translator.h | 28
1 file changed, 28 insertions(+)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 71e7b2c347..39f6f514a7 100644
--- a/include/exec/translator.h
Add the API first to ease review.
Signed-off-by: Emilio G. Cota
---
include/qemu/qemu-plugin.h | 241 +
1 file changed, 241 insertions(+)
create mode 100644 include/qemu/qemu-plugin.h
diff --git a/include/qemu/qemu-plugin.h b/include/qemu/qemu-plugin.h
new
Suggested-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
include/qom/cpu.h | 13 +
cpus-common.c | 2 ++
2 files changed, 15 insertions(+)
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 772cc960fe..fab18089db 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
Signed-off-by: Emilio G. Cota
---
target/ppc/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 2d31b5f7a1..7a7c8a9a88 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -7555,11 +7555,9
Will gain a user soon.
Signed-off-by: Emilio G. Cota
---
tcg/tcg-op.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index e2948b10a2..d3c79a6cb2 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1219,6 +1219,11 @@ static inline void tcg_gen_ld_ptr(TCGv_ptr
v1: https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg05682.html
Changes since v1:
- Drop the 2-pass translation. Instead, empty instrumentation
is injected during translation. If it turns out that this
empty instrumentation is not needed, it is removed from
the output. For this,
By adding it to plugin-gen's header file, we can export is as
an inline, since tcg.h is included in the header (we need tcg_ctx).
Signed-off-by: Emilio G. Cota
---
include/exec/plugin-gen.h | 27 ++-
accel/tcg/plugin-gen.c| 10 +-
2 files changed, 27
We will use this from plugins to mark mem accesses so that
we can later obtain their host address.
Signed-off-by: Emilio G. Cota
---
tcg/tcg.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 6fd525023b..a376f83ab6 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@
Some design requirements/goals:
- Make sure we cannot deadlock, particularly under MTTCG. For this,
we acquire a lock when called from plugin code, and keep
RCU lists of callbacks so that we do not have to hold the lock
when calling the callbacks. This is also for performance, since
some
This will be used by plugins to get the host address
of instructions.
Signed-off-by: Emilio G. Cota
---
include/exec/exec-all.h | 13 +
accel/tcg/cputlb.c | 14 +-
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/include/exec/exec-all.h
Afterwise is "wise after the fact", as in "hindsight".
Here we meant "afterwards" (as in "subsequently"). Fix it.
Reviewed-by: Alex Bennée
Signed-off-by: Emilio G. Cota
---
tcg/README | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/README b/tcg/README
index
This will allow us to trace 16B-long memory accesses.
While at it, add some defines for the mem_info bits and simplify
trace_mem_get_info by making it a wrapper around trace_mem_build_info.
Signed-off-by: Emilio G. Cota
---
trace-events | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
This is faster than removing elements one by one.
Will gain a user soon.
Signed-off-by: Emilio G. Cota
---
include/qemu/queue.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/include/qemu/queue.h b/include/qemu/queue.h
index ac418efc43..0283c2dd7d 100644
---
1 - 100 of 107 matches
Mail list logo
