Re: [Qemu-devel] [PATCH] util/error: do not free error on error_abort

Vladimir Sementsov-Ogievskiy writes: > It would be nice to have Error object not freed away when debugging a > coredump. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > --- > util/error.c | 8 +--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/util/error.c

[Qemu-devel] [Bug 1824744] Re: ivshmem PCI device exposes wrong endianness on ppc64le

** Summary changed: - ivshmem device PCI device exposes wrong endianness on ppc64le + ivshmem PCI device exposes wrong endianness on ppc64le -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1824744

[Qemu-devel] [Bug 1824744] [NEW] ivshmem device PCI device exposes wrong endianness on ppc64le

Public bug reported: On a ppc64le host with a ppc64le guest running on QEMU 3.1.0 when an ivshmem device is used, the ivshmem device appears to expose the wrong endianness for the values in BAR 0. For example, when the guest is assigned an ivshmem device ID of 1, the IVPosition register (u32,

[Qemu-devel] [PATCH RFC v7 12/12] hw/registerfields.h: Add 8bit and 16bit register macros.

Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato --- include/hw/registerfields.h | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h

[Qemu-devel] [PATCH RFC v7 09/12] hw/rx: RX Target hardware definition

rx62n - RX62N cpu. rxqemu - QEMU virtual target. Signed-off-by: Yoshinori Sato --- include/hw/rx/rx.h| 7 ++ include/hw/rx/rx62n.h | 54 hw/rx/rx62n.c | 226 ++ hw/rx/rxqemu.c| 100 ++

[Qemu-devel] [PATCH RFC v7 04/12] target/rx: RX disassembler

Signed-off-by: Yoshinori Sato --- include/disas/bfd.h |5 + target/rx/disas.c | 1481 +++ 2 files changed, 1486 insertions(+) create mode 100644 target/rx/disas.c diff --git a/include/disas/bfd.h b/include/disas/bfd.h index

[Qemu-devel] [PATCH RFC v7 08/12] hw/char: RX62N serical communication interface (SCI)

This module supported only non FIFO type. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/char/renesas_sci.h | 45 ++ hw/char/renesas_sci.c | 341

[Qemu-devel] [PATCH RFC v7 02/12] target/rx: TCG helper

Signed-off-by: Yoshinori Sato --- target/rx/helper.h| 31 target/rx/helper.c| 148 target/rx/op_helper.c | 481 ++ 3 files changed, 660 insertions(+) create mode 100644 target/rx/helper.h create mode 100644

[Qemu-devel] [PATCH RFC v7 07/12] hw/timer: RX62N internal timer modules

renesas_tmr: 8bit timer modules. renesas_cmt: 16bit compare match timer modules. This part use many renesas's CPU. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/timer/renesas_cmt.h | 33

[Qemu-devel] [PATCH RFC v7 03/12] target/rx: CPU definition

Signed-off-by: Yoshinori Sato --- target/rx/cpu-qom.h | 52 target/rx/cpu.h | 197 target/rx/cpu.c | 232 3 files changed, 481 insertions(+) create mode 100644

[Qemu-devel] [PATCH RFC v7 11/12] MAINTAINERS: Add RX

Signed-off-by: Yoshinori Sato --- MAINTAINERS | 19 +++ 1 file changed, 19 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 56139ac8ab..99d3428f04 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -272,6 +272,13 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F:

[Qemu-devel] [PATCH RFC v7 01/12] target/rx: TCG translation

This part only supported RXv1 instructions. Instruction manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032ej0120_rxsm.pdf Signed-off-by: Yoshinori Sato --- target/rx/translate.c | 2433 target/rx/insns.decode |

[Qemu-devel] [PATCH RFC v7 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers

Some RX peripheral using 8bit and 16bit registers. Added 8bit and 16bit APIs. Signed-off-by: Yoshinori Sato --- include/hw/registerfields.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index 2659a58737..f6bf911990

[Qemu-devel] [PATCH RFC v7 10/12] Add rx-softmmu

Signed-off-by: Yoshinori Sato --- configure | 8 default-configs/rx-softmmu.mak | 7 +++ include/sysemu/arch_init.h | 1 + arch_init.c| 2 ++ hw/Kconfig | 1 + 5 files changed, 19 insertions(+) create mode 100644

[Qemu-devel] [PATCH RFC v7 00/12] Add RX archtecture support

Hello. This patch series is added Renesas RX target emulation. It was corrected because the correspondence to registerfield was insufficient. My git repository is bellow. git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git Testing binaries bellow. u-boot Download -

[Qemu-devel] [PATCH RFC v7 06/12] hw/intc: RX62N interrupt controller (ICUa)

This implementation supported only ICUa. Hardware manual. https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01uh0033ej0140_rx62n.pdf Signed-off-by: Yoshinori Sato --- include/hw/intc/rx_icu.h | 49 +++ hw/intc/rx_icu.c | 373

[Qemu-devel] [PATCH RFC v7 05/12] target/rx: Miscellaneous files

Signed-off-by: Yoshinori Sato --- target/rx/gdbstub.c | 112 target/rx/monitor.c | 38 target/rx/Makefile.objs | 11 + 3 files changed, 161 insertions(+) create mode 100644 target/rx/gdbstub.c create mode 100644

Re: [Qemu-devel] [PATCH 5/6] memory_ldst: Add atomic ops for PTE updates

On Mon, 2019-04-15 at 13:38 +1000, David Gibson wrote: > On Thu, Apr 11, 2019 at 10:00:03AM +0200, Cédric Le Goater wrote: > > From: Benjamin Herrenschmidt > > > > On some architectures, PTE updates for dirty and changed bits need > > to be performed atomically. This adds a couple of > >

Re: [Qemu-devel] [PATCH v2] spapr: add splpar hcalls H_JOIN, H_PROD, H_CONFER

David Gibson's on April 15, 2019 2:13 pm: > On Fri, Apr 12, 2019 at 07:36:03PM +1000, Nicholas Piggin wrote: >> These implementations have a few deficiencies that are noted, but are >> good enough for Linux to use. >> >> Signed-off-by: Nicholas Piggin >> --- >> >> Cleaned up checkpatch

[Qemu-devel] [Bug 1824053] Re: Qemu-img convert appears to be stuck on aarch64 host with low probability

I can't reproduce this problem with qemu.git/matser? It seems to have been fixed in qemu.git/matser. But I haven't found which patch fixed this problem from QEMU version 2.8.1 to qemu.git/matser. Could anybody give me some suggestions? Thanks for your reply. -- You received this bug

Re: [Qemu-devel] [PATCH v2] spapr: add splpar hcalls H_JOIN, H_PROD, H_CONFER

On Fri, Apr 12, 2019 at 07:36:03PM +1000, Nicholas Piggin wrote: > These implementations have a few deficiencies that are noted, but are > good enough for Linux to use. > > Signed-off-by: Nicholas Piggin > --- > > Cleaned up checkpatch warnings, sorry I didn't realise that exists. > >

Re: [Qemu-devel] [PATCH 5/6] memory_ldst: Add atomic ops for PTE updates

On Thu, Apr 11, 2019 at 10:00:03AM +0200, Cédric Le Goater wrote: > From: Benjamin Herrenschmidt > > On some architectures, PTE updates for dirty and changed bits need > to be performed atomically. This adds a couple of address_space_cmpxchg* > helpers for that purpose. > > Signed-off-by:

Re: [Qemu-devel] [PATCH 0/2] ui/cocoa: Fix absolute and relative input issues on Mojave

ping > On Apr 8, 2019, at 10:04 AM, Chen Zhang wrote: > > The following patches fixed absolute and relative input device issues on > macOS Mojave. > > Chen Zhang (2): > ui/cocoa: Fix absolute input device grabbing issue on Mojave > ui/cocoa: Fix mouse grabbing in fullscreen mode for

Re: [Qemu-devel] [PATCH] e1000: Never increment the RX undersize count register

On 2019/4/15 上午11:29, Jason Wang wrote: On 2019/4/5 下午6:31, Stefano Garzarella wrote: On Thu, Apr 04, 2019 at 10:21:26AM -0500, Mark Kanda wrote: From: Chris Kenna In situations where e1000 receives an undersized Ethernet frame, QEMU increments the emulated "Receive Undersize Count (RUC)"

Re: [Qemu-devel] [PATCH] e1000: Never increment the RX undersize count register

On 2019/4/5 下午6:31, Stefano Garzarella wrote: On Thu, Apr 04, 2019 at 10:21:26AM -0500, Mark Kanda wrote: From: Chris Kenna In situations where e1000 receives an undersized Ethernet frame, QEMU increments the emulated "Receive Undersize Count (RUC)" register when padding the frame. This is

Re: [Qemu-devel] [RFC PATCH] hw/arm/virt: use variable size of flash device to save memory

On 2019/4/12 18:57, Kevin Wolf wrote: > Am 12.04.2019 um 11:50 hat Xiang Zheng geschrieben: >> >> On 2019/4/12 9:52, Xiang Zheng wrote: >>> On 2019/4/11 20:22, Kevin Wolf wrote: Okay, so your problem is that blk_pread() writes to the whole buffer, writing explicit zeroes for unallocated

Re: [Qemu-devel] [PATCH 3/4] target/ppc: improve performance of large BAT invalidations

On Fri, Apr 12, 2019 at 11:06:17PM +0200, Artyom Tarasenko wrote: > Performing a complete flush is ~ 100 times faster than flushing > 256MiB of 4KiB pages. Set a limit of 1024 pages and perform a complete > flush afterwards. > > This patch significantly speeds up AIX 5.1 and NetBSD-ofppc. > >

[Qemu-devel] Booting from a Bootcamp partition

Hi I was wondering if anyone has been able to boot from a bootcamp partition inside of QEMU. I know this partition can be used in QEMU but my own attempts at booting Windows 7 on my bootcamp partition did not work. I always see "A disk read error occurred". Has anyone else been successful at

Re: [Qemu-devel] [PATCH 4/4] hw/isa/i82378.c: use 1900 as a base year

Le 14/04/2019 à 20:53, Artyom Tarasenko a écrit : On Sun, Apr 14, 2019 at 7:01 PM Hervé Poussineau wrote: Le 12/04/2019 à 23:06, Artyom Tarasenko a écrit : AIX 5.1 expects the base year to be 1900. Adjust accordingly. Signed-off-by: Artyom Tarasenko --- hw/isa/i82378.c | 4 +++- 1

Re: [Qemu-devel] [PATCH] ati-vga: Fix check for blt outside vram

On Tue, 9 Apr 2019, Philippe Mathieu-Daudé wrote: This patch looks 4.0 worthwhile. Now that it seems we'll have another rc, will this get in? Gerd, I think you have to send a pull request with it for that. Regards, BALATON Zoltan On 4/9/19 12:56 PM, BALATON Zoltan wrote: Fix the check

Re: [Qemu-devel] [PATCH] target/arm: Implement NSACR gating of floating point

On 4/14/19 8:02 AM, Peter Maydell wrote: > There's similar wording for the effect of NSACR on CPACR, so > again I think we need to actually make the bits RAZ/WI > regardless of their underlying value, not just force them > to 0. I don't see that language for CPACR, just "the corresponding bits in

Re: [Qemu-devel] [PULL 0/2] Block layer patches for 4.0-rc4

On Fri, 12 Apr 2019 at 17:05, Kevin Wolf wrote: > > The following changes since commit 13c24edaa742181af8d9c6b027ee366b04de1ea1: > > qemu-img: fix .hx and .texi disparity (2019-04-12 14:17:10 +0100) > > are available in the Git repository at: > > git://repo.or.cz/qemu/kevin.git

Re: [Qemu-devel] How to I trigger a rebuild?

Am 14.04.19 um 20:12 schrieb Peter Maydell: On Sun, 14 Apr 2019 at 17:08, Joachim Durchholz wrote: Am 14.04.19 um 03:15 schrieb Max Filippov: On Sat, Apr 13, 2019 at 8:28 AM Joachim Durchholz wrote: I did the usual ./configure; make dance. Then modified a source file (ui/curses.c), called

Re: [Qemu-devel] [PATCH 4/4] hw/isa/i82378.c: use 1900 as a base year

On Sun, Apr 14, 2019 at 7:01 PM Hervé Poussineau wrote: > > Le 12/04/2019 à 23:06, Artyom Tarasenko a écrit : > > AIX 5.1 expects the base year to be 1900. Adjust accordingly. > > > > Signed-off-by: Artyom Tarasenko > > --- > > hw/isa/i82378.c | 4 +++- > > 1 file changed, 3 insertions(+), 1

Re: [Qemu-devel] [PATCH 1/4] lsi53c895a: hide 53c895a registers in 53c810

On Sun, Apr 14, 2019 at 5:43 PM Hervé Poussineau wrote: > > Le 12/04/2019 à 23:06, Artyom Tarasenko a écrit : > > AIX/PReP does access to the aliased IO registers of 53810. > > Implement aliasing to make the AIX driver work. > > > > Signed-off-by: Artyom Tarasenko > > --- > >

Re: [Qemu-devel] How to I trigger a rebuild?

On Sun, 14 Apr 2019 at 17:08, Joachim Durchholz wrote: > > Am 14.04.19 um 03:15 schrieb Max Filippov: > > On Sat, Apr 13, 2019 at 8:28 AM Joachim Durchholz > > wrote: > >> I did the usual ./configure; make dance. > >> Then modified a source file (ui/curses.c), called make again, but didn't > >>

Re: [Qemu-devel] [PATCH] target/arm: Implement NSACR gating of floating point

On Sat, 13 Apr 2019 at 08:07, Richard Henderson wrote: > > On 4/11/19 5:39 AM, Peter Maydell wrote: > > +static uint64_t cptr_el2_read(CPUARMState *env, const ARMCPRegInfo *ri) > > +{ > > +/* > > + * For A-profile AArch32 EL3, if NSACR.CP10 > > + * is 0 then HCPTR.{TCP11,TCP10} ignore

Re: [Qemu-devel] How to use QEMU's "cpu_physical_memory_" functions?

On Sat, 13 Apr 2019 at 10:47, 宋延杰 wrote: > I have started a project which requires the host to continuously write to > VM's memory. VM reads its memory and performs some operations. > I've found in this thread > that > I can

Re: [Qemu-devel] [PATCH 4/4] hw/isa/i82378.c: use 1900 as a base year

Le 12/04/2019 à 23:06, Artyom Tarasenko a écrit : AIX 5.1 expects the base year to be 1900. Adjust accordingly. Signed-off-by: Artyom Tarasenko --- hw/isa/i82378.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/isa/i82378.c b/hw/isa/i82378.c index a5d67bc..546c928

Re: [Qemu-devel] How to I trigger a rebuild?

Am 14.04.19 um 03:15 schrieb Max Filippov: On Sat, Apr 13, 2019 at 8:28 AM Joachim Durchholz wrote: I did the usual ./configure; make dance. Then modified a source file (ui/curses.c), called make again, but didn't see curses.c recompiled, and the change was indeed ineffective. make clean; make

Re: [Qemu-devel] [PATCH 3/4] target/ppc: improve performance of large BAT invalidations

Le 12/04/2019 à 23:06, Artyom Tarasenko a écrit : Performing a complete flush is ~ 100 times faster than flushing 256MiB of 4KiB pages. Set a limit of 1024 pages and perform a complete flush afterwards. This patch significantly speeds up AIX 5.1 and NetBSD-ofppc. Signed-off-by: Artyom

Re: [Qemu-devel] [PATCH 1/4] lsi53c895a: hide 53c895a registers in 53c810

Le 12/04/2019 à 23:06, Artyom Tarasenko a écrit : AIX/PReP does access to the aliased IO registers of 53810. Implement aliasing to make the AIX driver work. Signed-off-by: Artyom Tarasenko --- hw/scsi/lsi53c895a.c | 31 ++- 1 file changed, 26 insertions(+), 5

Re: [Qemu-devel] [PATCH 2/4] 40p and prep: implement PCI bus mastering

Le 12/04/2019 à 23:06, Artyom Tarasenko a écrit : Signed-off-by: Artyom Tarasenko --- hw/pci-host/prep.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) Reviewed-by: Hervé Poussineau

Re: [Qemu-devel] [PATCH RFC 1/1] block/rbd: increase dynamically the image size

On Sun, Apr 14, 2019 at 9:20 AM Stefano Garzarella wrote: > > On Thu, Apr 11, 2019 at 01:06:49PM -0400, Jason Dillaman wrote: > > On Thu, Apr 11, 2019 at 9:02 AM Stefano Garzarella > > wrote: > > > > > > On Thu, Apr 11, 2019 at 08:35:44AM -0400, Jason Dillaman wrote: > > > > On Thu, Apr 11,

Re: [Qemu-devel] [PATCH RFC v6 12/12] include/hw/regiserfields.h: Add 8bit and 16bit registers

On Thu, 11 Apr 2019 19:09:38 +0900, Philippe Mathieu-Daudé wrote: > > Hi Yoshinori, > > Note about the patch subject: > - typo in regiserfields (missing 't') -> registerfields > - I'd simply use "hw/registerfields: Add 8bit and 16bit register macros" OK. > On 4/1/19 4:03 PM, Yoshinori Sato

Re: [Qemu-devel] [PATCH RFC 1/1] block/rbd: increase dynamically the image size

On Thu, Apr 11, 2019 at 01:06:49PM -0400, Jason Dillaman wrote: > On Thu, Apr 11, 2019 at 9:02 AM Stefano Garzarella > wrote: > > > > On Thu, Apr 11, 2019 at 08:35:44AM -0400, Jason Dillaman wrote: > > > On Thu, Apr 11, 2019 at 7:00 AM Stefano Garzarella > > > wrote: > > > > > > > > RBD APIs

Re: [Qemu-devel] [RFC-PATCH] Introducing virtio-example device.

On 4/10/19 10:25 PM, Stefan Hajnoczi wrote: On Wed, Apr 10, 2019 at 4:45 PM Yoni Bettan wrote: On 4/9/19 4:17 PM, Stefan Hajnoczi wrote: On Mon, Apr 01, 2019 at 02:18:43PM +0300, Yoni Bettan wrote: There are multiple problems with the code, but the larger issue is that this example device