On Fri, Oct 15, 2021 at 6:08 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn32.decode | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
On Fri, Oct 15, 2021 at 6:06 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn32.decode | 6 +++---
> target/riscv/insn_trans/trans_rvv.c.inc | 5 -
>
On 10/17/21 4:59 PM, Alistair Francis wrote:
+#if defined(TARGET_RISCV64)
+/* 16 bits -> 64 bits */
+tcg_gen_ext16s_tl(dest, cpu_fpr[a->rs1]);
+#else
+/* 16 bits -> 32 bits */
+tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]);
+tcg_gen_ext16s_tl(dest, dest);
+#endif
Can we use
On Fri, Oct 15, 2021 at 6:25 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/insn32.decode | 2 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 10 --
> 2 files
On Fri, Oct 15, 2021 at 6:03 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/helper.h | 2 +-
> target/riscv/insn32.decode | 2 +-
>
On Fri, Oct 15, 2021 at 6:22 PM wrote:
>
> From: Frank Chang
>
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/helper.h | 2 +-
> target/riscv/insn32.decode | 2 +-
>
On Fri, Oct 15, 2021 at 6:04 PM wrote:
>
> From: Frank Chang
>
> Vector AMOs are removed from standard vector extensions. Will be added
> later as separate Zvamo extension, but will need a different encoding
> from earlier proposal.
>
> Signed-off-by: Frank Chang
Reviewed-by: Alistair Francis
On Mon, Oct 18, 2021 at 3:31 PM Richard Henderson
wrote:
>
> On 10/17/21 9:52 PM, Alistair Francis wrote:
> > On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson
> > wrote:
> >>
> >> The position of this read-only field is dependent on the
> >> current cpu width. Rather than having to compute
On 10/17/21 3:55 PM, Alistair Francis wrote:
On Fri, Oct 15, 2021 at 5:50 PM wrote:
From: Frank Chang
TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
commit: c445593, but other TB_FLAGS bits for rvv and rvh were
not shift as well so these bits may overlap with each other when
On 10/18/2021 11:46 AM, Xiaoyao Li wrote:
On 10/16/2021 4:22 AM, Eduardo Habkost wrote:
On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote:
commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support")
added the support of Intel PT by making CPUID[14] of PT as fixed feature
On 10/17/21 9:52 PM, Alistair Francis wrote:
On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson
wrote:
The position of this read-only field is dependent on the
current cpu width. Rather than having to compute that
difference in many places, compute it only on read.
Signed-off-by: Richard
On Mon, Oct 18, 2021 at 12:02 AM Warner Losh wrote:
>
>
>
> On Sun, Oct 17, 2021 at 10:29 PM Warner Losh wrote:
>>
>>
>>
>> On Sun, Oct 17, 2021 at 9:43 PM Kyle Evans wrote:
>>>
>>> On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>>> >
>>> > To increase flexibility, only descend into *-user
On Sun, Oct 17, 2021 at 04:58:37PM +0200, Philippe Mathieu-Daudé wrote:
> On 10/16/21 09:27, Paolo Bonzini wrote:
> > On 16/10/21 04:04, Richard Henderson wrote:
> >> I've seen a lot of failures on this job recently, and they're all
> >> timeouts cloning the git submodules. Would it be better to
On Sun, Oct 17, 2021 at 3:27 AM Richard Henderson
wrote:
>
> The multiply high-part instructions require a separate
> implementation for RV32 when TARGET_LONG_BITS == 64.
>
> Reviewed-by: LIU Zhiwei
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Mon, Oct 18, 2021 at 12:15 PM Frank Chang wrote:
>
> On Mon, Oct 18, 2021 at 8:03 AM Alistair Francis wrote:
>>
>> On Sat, Oct 16, 2021 at 7:08 PM wrote:
>> >
>> > From: Kito Cheng
>> >
>> > Signed-off-by: Kito Cheng
>> > Signed-off-by: Chih-Min Chao
>> > Signed-off-by: Frank Chang
>> >
On Sun, Oct 17, 2021 at 10:29 PM Warner Losh wrote:
>
>
> On Sun, Oct 17, 2021 at 9:43 PM Kyle Evans wrote:
>
>> On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>> >
>> > To increase flexibility, only descend into *-user when that is
>> > configured. This allows *-user to selectively include
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Create dummy signal queueing function so we can start to integrate other
> architectures (at the cost of signals remaining broken) to tame the
> dependency graph a bit and to bring in signals in a more controlled
> fashion. Log unimplemented
On Sun, Oct 17, 2021 at 3:32 AM Richard Henderson
wrote:
>
> The position of this read-only field is dependent on the
> current cpu width. Rather than having to compute that
> difference in many places, compute it only on read.
>
> Signed-off-by: Richard Henderson
This means that the value
From: Alistair Francis
Signed-off-by: Alistair Francis
---
target/riscv/cpu.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1d69d1887e..837bea3272 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@
On Sun, Oct 17, 2021 at 9:43 PM Kyle Evans wrote:
> On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
> >
> > To increase flexibility, only descend into *-user when that is
> > configured. This allows *-user to selectively include directories based
> > on the host OS which may not exist on all
On Fri, Oct 8, 2021 at 4:29 PM Warner Losh wrote:
>
> From: Guy Yur
>
> Switch checks for !(flags & MAP_ANONYMOUS) with checks for fd != -1.
> MAP_STACK and MAP_GUARD both require fd == -1 and don't require mapping
> the fd either. Add analysis from Guy Yur detailing the different cases
> for
On Sun, Oct 17, 2021 at 3:28 AM Richard Henderson
wrote:
>
> Most shift instructions require a separate implementation
> for RV32 when TARGET_LONG_BITS == 64.
>
> Reviewed-by: LIU Zhiwei
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
>
On Mon, Oct 18, 2021 at 8:18 AM Alistair Francis
wrote:
> On Sun, Oct 17, 2021 at 4:59 PM Frank Chang
> wrote:
> >
> > On Sun, Oct 17, 2021 at 8:55 AM Frank Chang
> wrote:
> >>
> >> On Sun, Oct 17, 2021 at 1:56 AM Richard Henderson <
> richard.hender...@linaro.org> wrote:
> >>>
> >>> On
On Sun, Oct 17, 2021 at 3:29 AM Richard Henderson
wrote:
>
> The count zeros instructions require a separate implementation
> for RV32 when TARGET_LONG_BITS == 64.
>
> Reviewed-by: LIU Zhiwei
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
>
On 10/16/2021 4:22 AM, Eduardo Habkost wrote:
On Thu, Sep 09, 2021 at 10:41:48PM +0800, Xiaoyao Li wrote:
commit e37a5c7fa459 ("i386: Add Intel Processor Trace feature support")
added the support of Intel PT by making CPUID[14] of PT as fixed feature
set (from ICX) for any CPU model on any
From: Alistair Francis
Signed-off-by: Alistair Francis
---
target/riscv/cpu_bits.h | 8
1 file changed, 8 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..3aa2512d13 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> To increase flexibility, only descend into *-user when that is
> configured. This allows *-user to selectively include directories based
> on the host OS which may not exist on all hosts. Adopt Paolo's
> suggestion of checking the
On Fri, Oct 8, 2021 at 4:25 PM Warner Losh wrote:
>
> Convert DEBUG_MMAP to qemu_log CPU_LOG_PAGE.
>
> Signed-off-by: Warner Losh
> ---
> bsd-user/mmap.c | 53 +
> 1 file changed, 23 insertions(+), 30 deletions(-)
>
> diff --git a/bsd-user/mmap.c
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Add the missing glue to pull in do_freebsd_sysarch to call
> do_freebsd_arch_sysarch. Put it in os-sys.c, which will be used for
> sysctl and sysarch system calls because they are mostly arch specific.
>
> Signed-off-by: Stacey Son
>
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> The 'used' field in TaskState is write only. Remove it from TaskState.
>
> Signed-off-by: Warner Losh
> Reviewed-by: Richard Henderson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> bsd-user/main.c | 1 -
> bsd-user/qemu.h | 1 -
> 2 files
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Similar to the same function in linux-user: this stops all the current tasks.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Warner Losh
> ---
> bsd-user/main.c | 9 +
> bsd-user/qemu.h | 1 +
> 2 files changed, 10 insertions(+)
>
>
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> To avoid a name clash with FreeBSD's sigqueue data structure in
> signalvar.h, rename sigqueue to qemu_sigqueue. This sturcture
s/sturcture/structure/
> is currently defined, but unused.
>
> Signed-off-by: Warner Losh
> Reviewed-by: Richard
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Some architectures publish AT_HWCAP2 as well as AT_HWCAP. Those
> architectures will define ELF_HWCAP2 in their target_arch_elf.h files
> for the value for this process. If it is defined, then publish it.
>
> Signed-off-by: Warner Losh
>
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> do_freebsd_arch_sysarch() exists in $ARCH/target_arch_sysarch.h for x86.
> Call it from do_freebsd_sysarch() and remove the mostly duplicate
> version in syscall.c. Future changes will move it to os-sys.c and
> support other architectures.
>
>
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> From: Stacey Son
>
> To emulate signals and interrupted system calls, we need to have the
> same mechanisms we have in the kernel, including these errno values.
>
> Signed-off-by: Stacey Son
> Signed-off-by: Warner Losh
> Reviewed-by:
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> All architectures have a ELF_HWCAP, so remove the fallback ifdef.
> Place ELF_HWCAP in the same order as on native FreeBSD.
>
> Signed-off-by: Warner Losh
> Reviewed-by: Richard Henderson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
>
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Move TARGET_MC_GET_CLEAR_RET to freebsd/target_os_signal.h since it's
> architecture agnostic on FreeBSD.
>
> Signed-off-by: Warner Losh
> Reviewed-by: Richard Henderson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
>
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Make get_errno and is_error global so files other than syscall.c can use
> them.
>
> Signed-off-by: Warner Losh
> Reviewed-by: Richard Henderson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> bsd-user/qemu.h| 4
>
On Fri, Oct 8, 2021 at 6:15 PM Warner Losh wrote:
>
> Signed-off-by: Warner Losh
> Reviewed-by: Richard Henderson
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> bsd-user/i386/target_arch_cpu.h | 2 --
> bsd-user/x86_64/target_arch_cpu.h | 2 --
> 2 files changed, 4 deletions(-)
>
> diff
On Sun, Oct 17, 2021 at 10:01:18PM -0300, Daniel Henrique Barboza wrote:
> This new version presents drastic design changes across all areas, most
> of them based on the feedback received in v3.
>
> - TCG reviewers: for people looking to review only TCG related changes,
> here's a summmary of
On Fri, Oct 15, 2021 at 03:19:40PM -0300, matheus.fe...@eldorado.org.br wrote:
> From: Matheus Ferst
>
> PowerISA says that mtmsr[d] "does not alter MSR[HV], MSR[S], MSR[ME], or
> MSR[LE]", but the current code only filters the GPR-provided value if
> L=1. This behavior caused some problems in
From: Alistair Francis
Signed-off-by: Alistair Francis
---
hw/intc/sifive_plic.c | 55 +--
1 file changed, 11 insertions(+), 44 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 49e566a76f..d73503cea4 100644
---
From: Alistair Francis
Signed-off-by: Alistair Francis
---
hw/intc/sifive_plic.c | 82 +--
1 file changed, 33 insertions(+), 49 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 5444368ad4..49e566a76f 100644
---
From: Alistair Francis
Signed-off-by: Alistair Francis
---
hw/intc/sifive_plic.c | 109 +-
1 file changed, 22 insertions(+), 87 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index d73503cea4..3f56223554 100644
---
From: Alistair Francis
Signed-off-by: Alistair Francis
---
hw/intc/sifive_plic.c | 45 +++
1 file changed, 24 insertions(+), 21 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index f0e2799efc..d77a5ced23 100644
---
From: Alistair Francis
Signed-off-by: Alistair Francis
---
hw/intc/sifive_plic.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 9ba36dc0b3..f0e2799efc 100644
--- a/hw/intc/sifive_plic.c
From: Alistair Francis
Signed-off-by: Alistair Francis
---
hw/intc/sifive_plic.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 877e76877c..5444368ad4 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@
From: Alistair Francis
Signed-off-by: Alistair Francis
---
hw/intc/sifive_plic.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index d77a5ced23..877e76877c 100644
--- a/hw/intc/sifive_plic.c
+++
From: Alistair Francis
The Ibex PLIC is now spec complient. Let's remove the Ibex PLIC and
instead use the SiFive PLIC.
Signed-off-by: Alistair Francis
---
hw/intc/ibex_plic.c | 307
hw/intc/meson.build | 1 -
2 files changed, 308 deletions(-)
From: Alistair Francis
Update the OpenTitan machine model to match the latest OpenTitan FPGA
design.
Signed-off-by: Alistair Francis
---
include/hw/riscv/opentitan.h | 6 +++---
hw/riscv/opentitan.c | 22 +-
2 files changed, 20 insertions(+), 8 deletions(-)
diff
Hi Igor,
On Fri, Oct 15, 2021 at 8:59 PM Igor Mammedov wrote:
>
> On Fri, 15 Oct 2021 17:25:01 +0800
> Bin Meng wrote:
>
> > On Fri, Oct 15, 2021 at 4:52 PM limingwang (A)
> > wrote:
> > >
> > >
> > > On Wed, Oct 13, 2021 at 22:41 PM Bin Meng wrote:
> > > >
> > > > On Tue, Oct 12, 2021 at
On Mon, Oct 18, 2021 at 8:03 AM Alistair Francis
wrote:
> On Sat, Oct 16, 2021 at 7:08 PM wrote:
> >
> > From: Kito Cheng
> >
> > Signed-off-by: Kito Cheng
> > Signed-off-by: Chih-Min Chao
> > Signed-off-by: Frank Chang
> > Reviewed-by: Richard Henderson
> > ---
> > target/riscv/cpu.c
Cache the pointer to PCI function 0 (ISA bridge, that this IDE device
has to use for IRQs) in the PCIIDEState and pass that as the opaque
data for the interrupt handler to eliminate both the need to look up
function 0 at every interrupt and also a QOM type cast of the opaque
pointer as that's also
The current logic is only considering event-based exceptions triggered
by the performance monitor. This is true now, but we might want to add
support for external event-based exceptions in the future.
Let's make it a bit easier to do so by adding the bit logic that would
happen in case we were
On Mon, Oct 18, 2021 at 6:30 AM Jose Martins wrote:
>
> Hello Zhiwei and Alistair,
>
> I noticed this patch did not make it upstream, contrarily to a couple
> other patches I submitted around the same time. Is there something
> else needed from my side to push this forward?
>From your last
From: Gustavo Romero
Following up the rfebb implementation, this patch adds the EBB exception
support that are triggered by Performance Monitor alerts. This exception
occurs when an enabled PMU condition or event happens and both MMCR0_EBE
and BESCR_PME are set.
The supported PM alerts will
An Event-Based Branch (EBB) allows applications to change the NIA when a
event-based exception occurs. Event-based exceptions are enabled by
setting the Branch Event Status and Control Register (BESCR). If the
event-based exception is enabled when the exception occurs, an EBB
happens.
The
The initial PMU support were made under the assumption that the counters
would be set before running the PMU and read after either freezing the
PMU manually or via a performance monitor alert.
Turns out that some EBB powerpc kernel tests set the counters after
unfreezing the counters. Setting a
Up until this moment we were assuming that the counter negative
enabled bits, PMC1CE and PMCjCE, would never be changed when the
PMU is already started.
Turns out that there is no such restriction in the PowerISA v3.1,
and software can enable/disable overflow conditions of the counters
at any
PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.
Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time
The PowerISA v3.1 defines that if the proper bits are set (MMCR0_PMC1CE
for PMC1 and MMCR0_PMCjCE for the remaining PMCs), counter negative
conditions are enabled. This means that if the counter value overflows
(i.e. exceeds 0x8000) a performance monitor alert will occur. This alert
can
The PMU is already counting cycles by calculating time elapsed in
nanoseconds. Counting instructions is a different matter and requires
another approach.
This patch adds the capability of counting completed instructions
(Perf event PM_INST_CMPL) by counting the amount of instructions
translated
This patch starts an IBM Power8+ compatible PMU implementation by adding
the representation of PMU events that we are going to sample, PMUEvent.
This struct represents a Perf event, determined by the PMUEventType
enum, that is being sampled by a specific counter 'sprn'. PMUEvent also
contains an
This patch adds the barebones of the PMU logic by enabling cycle
counting. The overall logic goes as follows:
- a helper is added to control the PMU state on each MMCR0 write. This
allows for the PMU to start/stop as the frozen counter bit (MMCR0_FC)
is cleared or set;
- MMCR0 reg initial value
The value of MMCR1 determines the events that are going to be sampled by
the programmable counters (PMCs 1-4). PMCs 5 and 6 are always counting
instructions and cycles respectively and aren't affected by MMCR1.
This patch adds a helper to initialize PMCs 1-4 PMUEvents when writing
the MMCR1
From: Gustavo Romero
Userspace need access to PMU SPRs to be able to operate the PMU. One of
such SPRs is MMCR0.
MMCR0, as defined by PowerISA v3.1, is classified as a 'group A' PMU
register. This class of registers has common read/write rules that are
governed by MMCR0 PMCC bits. MMCR0 is also
Similar to the previous patch, let's add problem state read/write access to
the MMCR2 SPR, which is also a group A PMU SPR that needs to be filtered
to be read/written by userspace.
Signed-off-by: Daniel Henrique Barboza
---
target/ppc/cpu.h | 9 +++
target/ppc/cpu_init.c
This new version presents drastic design changes across all areas, most
of them based on the feedback received in v3.
- TCG reviewers: for people looking to review only TCG related changes,
here's a summmary of where are the TCG code in the series:
* Patches that have a lot of TCG/translation
Problem state needs to be able to read and write the PMU counters,
otherwise it won't be aware of any sampling result that the PMU produces
after a Perf run.
This patch does that in a similar fashion as already done in the
previous patches. PMCs 5 and 6 have a special condition, aside from the
We're going to add PMU support for TCG PPC64 chips, based on IBM POWER8+
emulation and following PowerISA v3.1. This requires several PMU related
registers to be exposed to userspace (problem state). PowerISA v3.1
dictates that the PMCC bits of the MMCR0 register controls the level of
access of
On Sun, 2021-10-17 at 17:08 +0200, Philippe Mathieu-Daudé wrote:
> Hi Benjamin,
>
> On 10/17/21 09:48, Benjamin Herrenschmidt wrote:
> > The framebuffer driver fails to initialize with recent Raspberry Pi
> > kernels, such as the ones shipped in the current RaspiOS images
> > (with the out of
On Sun, Oct 17, 2021 at 4:59 PM Frank Chang wrote:
>
> On Sun, Oct 17, 2021 at 8:55 AM Frank Chang wrote:
>>
>> On Sun, Oct 17, 2021 at 1:56 AM Richard Henderson
>> wrote:
>>>
>>> On 10/16/21 1:52 AM, Frank Chang wrote:
>>> > On Sat, Oct 16, 2021 at 1:05 AM Richard Henderson
>>> > >> >
On Sat, Oct 16, 2021 at 7:13 PM wrote:
>
> From: Frank Chang
>
> Zfhmin extension is a subset of Zfh extension, consisting only of data
> transfer and conversion instructions.
>
> If enabled, only the following instructions from Zfh extension are
> included:
> * flh, fsh, fmv.x.h, fmv.h.x,
On Sat, Oct 16, 2021 at 7:08 PM wrote:
>
> From: Kito Cheng
>
> Signed-off-by: Kito Cheng
> Signed-off-by: Chih-Min Chao
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
> ---
> target/riscv/cpu.c| 1 +
> target/riscv/cpu.h| 1 +
On Sat, Oct 16, 2021 at 7:11 PM wrote:
>
> From: Kito Cheng
>
> Signed-off-by: Kito Cheng
> Signed-off-by: Chih-Min Chao
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/fpu_helper.c | 6 ++
>
On Sat, Oct 16, 2021 at 7:12 PM wrote:
>
> From: Kito Cheng
>
> Signed-off-by: Kito Cheng
> Signed-off-by: Chih-Min Chao
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/fpu_helper.c | 21
On Sat, Oct 16, 2021 at 7:09 PM wrote:
>
> From: Kito Cheng
>
> Signed-off-by: Kito Cheng
> Signed-off-by: Chih-Min Chao
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
> ---
> target/riscv/fpu_helper.c | 67 +
> target/riscv/helper.h |
On Sat, Oct 16, 2021 at 7:08 PM wrote:
>
> From: Kito Cheng
>
> Signed-off-by: Kito Cheng
> Signed-off-by: Chih-Min Chao
> Signed-off-by: Frank Chang
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/fpu_helper.c | 86
On Sat, Oct 16, 2021 at 1:09 PM MingWang Li wrote:
>
> From: Mingwang Li
>
> If default main_mem is used to be registered as the system memory,
> other memory cannot be initialized. Therefore, the system memory
> should be initialized to the machine->ram, which consists of the
> default main_mem
From: BALATON Zoltan
Other functions in the VT82xx chips need to raise ISA interrupts. Keep
a reference to them in the device state and add via_isa_set_irq() to
allow setting their state.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Jiaxun Yang
Message-Id:
From: BALATON Zoltan
This model only works as a function of the via superio chip not as a
standalone PCI device.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20211015092159.3e863748...@zero.eik.bme.hu>
Signed-off-by: Philippe Mathieu-Daudé
---
hw/ide/via.c
On Fri, Oct 15, 2021 at 5:50 PM wrote:
>
> From: Frank Chang
>
> TB_FLAGS mem_idx bits was extended from 2 bits to 3 bits in
> commit: c445593, but other TB_FLAGS bits for rvv and rvh were
> not shift as well so these bits may overlap with each other when
> rvv is enabled.
>
> Signed-off-by:
Avoid using a TCG temporary by moving Data Format to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20211003175743.3738710-5-f4...@amsat.org>
---
target/mips/tcg/msa_translate.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
While for the DEXTR_S.H opcode:
"The shift argument is provided in the instruction."
For the DEXTRV_S.H opcode we have:
"The five least-significant bits of register rs provide the
shift argument, interpreted as a five-bit unsigned integer;
the remaining bits in rs are ignored."
While
From: BALATON Zoltan
The vt82c686b_realize and vt8231_realize methods are almost identical,
factor out the common parts to a via_isa_realize function to avoid
code duplication.
Signed-off-by: BALATON Zoltan
Reviewed-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
From: BALATON Zoltan
Use via_isa_set_irq() which better encapsulates irq handling in the
vt82xx model and avoids using isa_get_irq() that has a comment saying
it should not be used.
Signed-off-by: BALATON Zoltan
Reviewed-by: Philippe Mathieu-Daudé
Message-Id:
Avoid using a TCG temporary by moving Data Format to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20211003175743.3738710-6-f4...@amsat.org>
---
target/mips/tcg/msa_translate.c | 23 ++-
1 file changed, 14
Since gen_mipsdsp_accinsn() got added in commit b53371ed5d4
("target-mips: Add ASE DSP accumulator instructions"), the
'v2_t' TCG temporary has never been used. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20211014224551.2204949-1-f4...@amsat.org>
Avoid using a TCG temporary by moving Data Format to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20211003175743.3738710-4-f4...@amsat.org>
---
target/mips/tcg/msa_translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
We already use sextract32(), use extract32() for completeness
instead of open-coding it.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20211003175743.3738710-7-f4...@amsat.org>
---
target/mips/tcg/msa_translate.c | 11 ---
1 file changed, 4
The offset is constant and read-only: move it to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20211003175743.3738710-9-f4...@amsat.org>
---
target/mips/tcg/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git
Commits cbe50b9a8e7 ("target-mips: add MSA VEC/2R format instructions")
and 3bdeb68866e ("target-mips: add MSA 2RF format instructions") added
the MSA 2R/2RF instructions. However these instructions don't use any
target vector register, so remove the unused TCG temporaries.
Reviewed-by: Richard
From: Jiaxun Yang
Generate FDT on our own if no dtb argument supplied.
Avoid introducing unused device in FDT with user supplied dtb.
Signed-off-by: Jiaxun Yang
[PMD: Fix coding style]
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20211002184539.169-4-jiaxun.y...@flygoat.com>
---
The following changes since commit c148a0572130ff485cd2249fbdd1a3260d5e10a4:
Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20211016' into
staging (2021-10-16 11:16:28 -0700)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/mips-20211018
for you to
Data Format is a 2-bit constant value.
Avoid using a TCG temporary by moving it to the constant pool.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-Id: <20211003175743.3738710-3-f4...@amsat.org>
---
target/mips/tcg/msa_translate.c | 3 +--
1 file changed, 1
From: Jiaxun Yang
ELF kernel allows us debugging much easier with DWARF symbols.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
[PMD: Fix coding style]
Signed-off-by: Philippe Mathieu-Daudé
Message-Id: <20211002184539.169-3-jiaxun.y...@flygoat.com>
---
hw/mips/boston.c | 36
From: Jiaxun Yang
Use memmap array to uinfy address of memory map.
That would allow us reuse address information for FDT generation.
Signed-off-by: Jiaxun Yang
Reviewed-by: Philippe Mathieu-Daudé
[PMD: Use local 'regaddr' in gen_firmware(), fix coding style]
Signed-off-by: Philippe
Per the "MIPS Architecture Extension: nanoMIPS32 DSP TRM" rev 0.04,
MULT and MULTU opcodes:
The value of ac selects an accumulator numbered from 0 to 3.
When ac=0, this refers to the original HI/LO register pair of the
MIPS32 architecture.
In Release 6 of the MIPS Architecture,
On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote:
On 10/17/21 20:44, BALATON Zoltan wrote:
On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote:
On 10/15/21 03:06, BALATON Zoltan wrote:
Use via_isa_set_irq() which better encapsulates irq handling in the
vt82xx model and avoids using
On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote:
On 10/17/21 21:39, BALATON Zoltan wrote:
On Sun, 17 Oct 2021, Philippe Mathieu-Daudé wrote:
On 10/15/21 03:06, BALATON Zoltan wrote:
Use via_isa_set_irq() which better encapsulates irq handling in the
vt82xx model and avoids using
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