On Thu, 3 Mar 2022 14:40:56 +0100
Christian Schoenebeck wrote:
> This patch set converts occurrences of API doc comments from Doxygen format
> into kerneldoc format. No behaviour change whatsoever.
>
> Christian Schoenebeck (6):
> 9pfs/9p.h: convert Doxygen -> kerneldoc format
>
Eugenio Pérez writes:
> Finally offering the possibility to enable SVQ from the command line.
>
> Signed-off-by: Eugenio Pérez
> ---
> qapi/net.json| 8 +++-
> net/vhost-vdpa.c | 48
> 2 files changed, 47 insertions(+), 9 deletions(-)
>
Eugenio Perez Martin writes:
> Yes, that's right. I expressed my point poorly actually, I'll go the reverse.
>
> qapi-gen.py forces me to write a comment in the doc:
> qapi/block-core.json:2971: feature 'unstable' lacks documentation
>
> When I add the documentation line, it's enough to add
From: Naveen Nagar
Add support for up to 64 LBA formats through the LBAFEE field of the
Host Behavior Support feature.
Reviewed-by: Keith Busch
Signed-off-by: Naveen Nagar
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 34 +++---
hw/nvme/ns.c | 15
From: Naveen Nagar
This adds support for one possible new protection information format
introduced in TP4068 (and integrated in NVMe 2.0): the 64-bit CRC guard
and 48-bit reference tag. This version does not support storage tags.
Like the CRC16 support already present, this uses a software
From: Naveen Nagar
Add support for getting and setting the Host Behavior Support feature.
Reviewed-by: Keith Busch
Signed-off-by: Naveen Nagar
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 8
hw/nvme/nvme.h | 4 +++-
include/block/nvme.h | 9 +
3 files
From: Klaus Jensen
A subsequent patch will introduce a new tuple size; so add a helper and
use that instead of sizeof() and magic numbers.
Reviewed-by: Keith Busch
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 14 --
hw/nvme/dif.c | 16
hw/nvme/dif.h | 5
From: Klaus Jensen
Move dif/pi data structures and inlines to dif.h.
Reviewed-by: Keith Busch
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 1 +
hw/nvme/dif.c | 1 +
hw/nvme/dif.h | 53 ++
hw/nvme/nvme.h | 50
From: Klaus Jensen
There is no need to extract the format command parameters for each
namespace. Move it to the entry point.
Reviewed-by: Keith Busch
Signed-off-by: Klaus Jensen
---
hw/nvme/ctrl.c | 31 ++-
1 file changed, 18 insertions(+), 13 deletions(-)
diff
From: Klaus Jensen
Hi Peter,
Last round of hw/nvme updates for v7.0.
The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47b1:
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into
staging (2022-03-02 12:38:46 +)
are available in the Git
On 2022/03/04 3:34, Akihiko Odaki wrote:
On Fri, Mar 4, 2022 at 12:43 AM Vladislav Yaroshchuk
wrote:
On Tue, Mar 1, 2022 at 11:21 AM Akihiko Odaki wrote:
On 2022/03/01 17:09, Vladislav Yaroshchuk wrote:
> Not sure that only one field is enough, cause
> we may have two states
On 2022/03/04 10:37, Jason Wang wrote:
On Thu, Mar 3, 2022 at 11:43 PM Vladislav Yaroshchuk
wrote:
On Tue, Mar 1, 2022 at 11:21 AM Akihiko Odaki wrote:
On 2022/03/01 17:09, Vladislav Yaroshchuk wrote:
> Not sure that only one field is enough, cause
> we may have two states
On Fri, Mar 4, 2022 at 8:50 AM Atish Patra wrote:
>
> Currently, the aclint and ibex timer devices uses the "timer" &
> "timecmp" to generate the m-mode timer interrupt. In future,
> we will have timer interrupt injected to S/VS mode directly.
> No functionality change introduced in this patch.
vstimecmp CSR allows the guest OS or to program the next guest timer
interrupt directly. Thus, hypervisor no longer need to inject the
timer interrupt to the guest if vstimecmp is used. This was ratified
as a part of the Sstc extension.
Signed-off-by: Atish Patra
---
target/riscv/cpu.h
Currently, the aclint and ibex timer devices uses the "timer" &
"timecmp" to generate the m-mode timer interrupt. In future,
we will have timer interrupt injected to S/VS mode directly.
No functionality change introduced in this patch.
Add a prefix "m" these enviornment variables to indicate its
stimecmp allows the supervisor mode to update stimecmp CSR directly
to program the next timer interrupt. This CSR is part of the Sstc
extension which was ratified recently.
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 7 +++
target/riscv/cpu.h | 5 ++
This series implements Sstc extension[1] which was ratified recently.
The first patch is a prepartory patches while PATCH 2 adds stimecmp
support while PATCH 3 adds vstimecmp support. This series is based on
the ISA extension[2] & privilege version update series[3].
The series can also be found
On Thu, Mar 03, 2022 at 03:59:02PM -0500, John Snow wrote:
> Fority compare_images() to be more discerning about the status codes it
Fortify
> receives. If qemu_img() returns an exit code that implies it didn't
> actually perform the comparison, treat that as an exceptional
> circumstance and
On Thu, Mar 03, 2022 at 03:59:01PM -0500, John Snow wrote:
> re-write qemu_img() as a function that will by default raise a
> VerboseProcessException (extended from CalledProcessException) on
> non-zero return codes. This will produce a stack trace that will show
> the command line arguments and
On Thu, Mar 03, 2022 at 03:58:59PM -0500, John Snow wrote:
> This adds an Exception that extends the Python stdlib
> subprocess.CalledProcessError.
>
> The difference is that the str() method of this exception also adds the
> stdout/stderr logs. In effect, if this exception goes unhandled, Python
On 2022/3/4 2:51, Eugenio Pérez wrote:
This iova tree function allows it to look for a hole in allocated
regions and return a totally new translation for a given translated
address.
It's usage is mainly to allow devices to access qemu address space,
remapping guest's one into a new iova
On Fri, Mar 4, 2022 at 12:33 AM Eugenio Perez Martin
wrote:
>
> On Mon, Feb 28, 2022 at 8:06 AM Jason Wang wrote:
> >
> >
> > 在 2022/2/27 下午9:41, Eugenio Pérez 写道:
> > > This tree is able to look for a translated address from an IOVA address.
> > >
> > > At first glance it is similar to
On Thu, Mar 3, 2022 at 5:25 PM Eugenio Perez Martin wrote:
>
> On Thu, Mar 3, 2022 at 8:12 AM Jason Wang wrote:
> >
> >
> > 在 2022/3/2 上午2:49, Eugenio Perez Martin 写道:
> > > On Mon, Feb 28, 2022 at 3:57 AM Jason Wang wrote:
> > >> 在 2022/2/27 下午9:40, Eugenio Pérez 写道:
> > >>> At this mode no
On Thu, Mar 3, 2022 at 11:43 PM Vladislav Yaroshchuk
wrote:
>
>
>
> On Tue, Mar 1, 2022 at 11:21 AM Akihiko Odaki wrote:
>>
>> On 2022/03/01 17:09, Vladislav Yaroshchuk wrote:
>> > > Not sure that only one field is enough, cause
>> > > we may have two states on bh execution start:
>> >
We were mapping this to ld1 (32-bit unpacked unscaled offset),
which discarded the upper 32 bits of the address coming from
the vector argument.
Fixed by setting XS=2, which is the existing translator internal
value for no extension. Update the comments, which matched the
incorrect code.
Fixes:
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Signed-off-by: Atish Patra
From: Atish Patra
mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.
Support mcycle/minstret
The sscofpmf extension was ratified as a part of priv spec v1.12.
Mark the csr_ops accordingly.
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 90 ++
1 file changed, 60 insertions(+), 30 deletions(-)
diff --git a/target/riscv/csr.c
From: Atish Patra
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
From: Atish Patra
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Atish Patra
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.
Simplify the predicate function so that we just handle things differently
between RV32/RV64 and S/HS mode.
Reviewed-by: Bin Meng
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension.
From: Atish Patra
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
From: Atish Patra
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h |
From: Atish Patra
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many programmable counters should be implemented
From: Atish Patra
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair
The latest version of the SBI specification includes a Performance Monitoring
Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level
extensions, and 'cofpmf' for Count OverFlow and Privilege Mode
On Wed, 22 Dec 2021 11:05:23 -0800
Steve Sistare wrote:
> +if (vfio_notifier_init(vdev, >intx.unmask, "intx-unmask", 0)) {
...
> +vfio_notifier_cleanup(vdev, >intx.unmask, "intx-unmask", 0);
...
> +vfio_notifier_cleanup(vdev, >intx.unmask, "intx-unmask", 0);
...
> +ret =
On 3/3/22 06:55, Peter Maydell wrote:
Alternately, force size == 1, so that we always get a non-NULL value that can
be freed.
That's a change on the POSIX side as well, of course.
Yes, I had a look at what actual malloc() implementations tend
to do, and the answer seems to be that forcing
On Thu, Mar 03, 2022 at 04:03:22PM +, Daniel P. Berrangé wrote:
> When using the --list option, qemu-nbd acts as an NBD client rather
> than a server. As such when using TLS, it has a need to validate
> the server certificate. This adds a --tls-hostname option which can
> be used to override
On Thu, Mar 03, 2022 at 03:58:58PM -0500, John Snow wrote:
> >>> print(add_visual_margin(msg, width=72, name="Commit Message"))
> ┏━ Commit Message ━━
> ┃ add_visual_margin() takes a chunk of text and wraps it in a visual
> ┃ container that
Ping - Dan, Kevin: Any thoughts on the new API here? I only ask
because there was a bit of feedback in response to the last patch and
I didn't want to stage this without giving you a fair chance to look.
I'm not expecting any real review on the Python, just wanted to see if
you felt like this
On Thu, Mar 03, 2022 at 05:48:14PM +0100, Hanna Reitz wrote:
> 185 tests quitting qemu while a block job is active. It does not
> specifically test quitting qemu while a mirror or active commit job is
> in its READY phase.
>
> Add two test cases for this, where we respectively mirror or commit
On Thu, Mar 03, 2022 at 05:48:13PM +0100, Hanna Reitz wrote:
> To implement this, we reuse the existing daemonizing functions from the
> system emulator, which mainly do the following:
> - Fork off a child process, and set up a pipe between parent and child
> - The parent process waits until the
On Thu, Mar 03, 2022 at 05:48:12PM +0100, Hanna Reitz wrote:
> In contrast to qemu-nbd (where it is called --fork) and the system
> emulator, QSD does not have a --daemonize switch yet. Just like them,
> QSD allows setting up block devices and exports on the command line.
> When doing so, it is
On Thu, Mar 03, 2022 at 04:03:21PM +, Daniel P. Berrangé wrote:
> When connecting to an NBD server with TLS and x509 credentials,
> the client must validate the hostname it uses for the connection,
> against that published in the server's certificate. If the client
> is tunnelling its
On 3/3/22 10:23, Peter Maydell wrote:
We forgot a space in some log messages, so the output ended
up looking like
gicv3_dist_write: invalid guest write at offset 8000size 8
with a missing space before "size". Add the missing spaces.
Signed-off-by: Peter Maydell
---
On 3/3/22 10:23, Peter Maydell wrote:
The trace_gicv3_icv_hppir_read trace event takes an integer value
which it uses to form the register name, which should be either
ICV_HPPIR0 or ICV_HPPIR1. We were passing in the 'grp' variable for
this, but that is either GICV3_G0 or GICV3_G1NS, which
On 3/3/22 10:23, Peter Maydell wrote:
The GICv3 has some registers that support byte accesses, and some
that support 8-byte accesses. Our TCG implementation implements all
of this, switching on the 'size' argument and handling the registers
that must support reads of that size while logging an
On 3/3/22 10:23, Peter Maydell wrote:
For debugging guest use of the ITS, it can be helpful to trace
when the ITS reads and writes the in-memory tables.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 37 +++--
hw/intc/trace-events| 9 +
On 3/3/22 10:23, Peter Maydell wrote:
When debugging code that's using the ITS, it's helpful to
see tracing of the ITS commands that the guest executes. Add
suitable trace events.
Signed-off-by: Peter Maydell
---
hw/intc/arm_gicv3_its.c | 28 ++--
hw/intc/trace-events
On 3/3/22 10:53, Matheus K. Ferst wrote:
On 03/03/2022 16:30, Richard Henderson wrote:
On 3/3/22 07:20, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
LLVM/Clang doesn't know the VSX registers when compiling with
-mabi=elfv1. Use only registers >= 32 and list them with their
Create a new function to combine a CPUTLBEntry addend
with the guest address to form a host address.
Reviewed-by: WANG Xuerui
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
accel/tcg/cputlb.c | 24
All RV64 32-bit operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard Henderson
---
tcg/riscv/tcg-target-sa32.h | 6 +-
When using reserved_va, which is the default for a 64-bit host
and a 32-bit guest, set guest_base_signed_addr32 if requested
by TCG_TARGET_SIGNED_ADDR32, and the executable layout allows.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to
allow the 32-bit guest address to be sign extended within the
64-bit host register instead of zero extended.
This will simplify tcg hosts like MIPS, RISC-V, and LoongArch,
which naturally sign-extend 32-bit values, in contrast to
While the host may prefer to treat 32-bit addresses as signed,
there are edge cases of guests that cannot be implemented with
addresses 0x7fff_ and 0x8000_ being non-consecutive.
Therefore, default to guest_base_signed_addr32 false, and allow
probe_guest_base to determine whether it is
All 32-bit mips operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/mips/tcg-target-sa32.h | 8
tcg/mips/tcg-target.c.inc | 10 ++
2
Define as 0 for all tcg hosts. Put this in a separate header,
because we'll want this in places that do not ordinarily have
access to all of tcg/tcg.h.
Reviewed-by: WANG Xuerui
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Alistair Francis
Signed-off-by: Richard
The general ternary logic operation can implement BITSEL.
Funnel the 4-operand operation into three variants of the
3-operand instruction, depending on input operand overlap.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
AVX512VL has a general ternary logic operation, VPTERNLOGQ,
which can implement NOT, ORC, NAND, NOR, EQV.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 10 +-
tcg/i386/tcg-target.c.inc | 34
AArch64 has both sign and zero-extending addressing modes, which
means that either treatment of guest addresses is equally efficient.
Enabling this for AArch64 gives us testing of the feature in CI.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target-sa32.h |
All 32-bit LoongArch operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.
Cc: WANG Xuerui
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/loongarch64/tcg-target-sa32.h | 2 +-
Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V;
expand 16-bit scalar rotate with VPSHLDV.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 49 +++
1 file changed, 29 insertions(+), 20
AVX512VL has VPABSQ, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc
There is no such instruction on x86, so we should
not be pretending it has arguments.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 1 -
1 file changed, 1 deletion(-)
diff --git a/tcg/i386/tcg-target.c.inc
AVX512DQ has VPMULLQ.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index
The condition for UMIN/UMAX availability is about to change;
use the canonical version.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
While there are no specific 16-bit rotate instructions, there
are double-word shifts, which can perform the same operation.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 18 +-
1 file changed, 17 insertions(+),
We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target-con-set.h | 1 +
tcg/i386/tcg-target.opc.h | 3 +++
tcg/i386/tcg-target.c.inc | 38 +++
AVX512VL has VPROLVD and VPRORVQ.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 25 -
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git
AVX512 has VPSRAQ with immediate operand, in the same form as
with AVX, but requires EVEX encoding and W1.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 30 +-
1 file changed, 21 insertions(+), 9
There are some operation sizes in some subsets of AVX512 that
are missing from previous iterations of AVX. Detect them.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
include/qemu/cpuid.h | 20 +---
tcg/i386/tcg-target.h | 4
AVX512VL has VPROLD and VPROLQ, layered onto the same
opcode as PSHIFTD, but requires EVEX encoding and W1.
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 15 +--
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git
AVX512VL has VPSRAVQ, and
AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 32
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git
The evex encoding is added here, for use in a subsequent patch.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 51 ++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git
AVX512VL has VPSRAQ.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
---
tcg/i386/tcg-target.c.inc | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/s390x/tcg-target.h | 6 +++---
tcg/s390x/tcg-target.c.inc | 17 +
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
tcg/ppc/tcg-target.h | 6 +++---
tcg/ppc/tcg-target.c.inc | 15 +++
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/tcg/ppc/tcg-target.h
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/tcg/tcg-opc.h| 3 +++
include/tcg/tcg.h|
From: Alex Bennée
valgrind pointed out that arg_info()->val can be undefined which will
be the case if the arguments are not constant. The ordering of the
checks will have ensured we never relied on an undefined value but for
the sake of completeness re-order the code to be clear.
Reviewed-by:
This adds an Exception that extends the Python stdlib
subprocess.CalledProcessError.
The difference is that the str() method of this exception also adds the
stdout/stderr logs. In effect, if this exception goes unhandled, Python
will print the output in a visually distinct wrapper to the terminal
From: Ziqiao Kong
The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and
thus the MAX_OPC_PARAM_IARGS should be 7.
Reviewed-by: Taylor Simpson
Signed-off-by: Ziqiao Kong
Message-Id: <20220227113127.414533-2-ziqiaok...@gmail.com>
Fixes: e6cadf49c3d ("tcg: Add support for a helper with
-tcg-20220303
for you to fetch changes up to f23e6de25c31cadd9a3b7122f9384e6b259ce37f:
tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32 (2022-03-03 10:47:20 -1000)
Reorder do_constant_folding_cond test to satisfy valgrind.
Fix
>>> print(add_visual_margin(msg, width=72, name="Commit Message"))
┏━ Commit Message ━━
┃ add_visual_margin() takes a chunk of text and wraps it in a visual
┃ container that force-wraps to a specified width. An optional title
┃ label may be
Fority compare_images() to be more discerning about the status codes it
receives. If qemu_img() returns an exit code that implies it didn't
actually perform the comparison, treat that as an exceptional
circumstance and force the caller to be aware of the peril.
If a negative test is desired
re-write qemu_img() as a function that will by default raise a
VerboseProcessException (extended from CalledProcessException) on
non-zero return codes. This will produce a stack trace that will show
the command line arguments and return code from the failed process run.
Users that want something
qemu_img() returning zero ought to be the rule, not the
exception. Remove all explicit checks against the condition in
preparation for making non-zero returns an Exception.
Signed-off-by: John Snow
Reviewed-by: Eric Blake
---
tests/qemu-iotests/163 | 9 +++--
This is kinda-sorta V3-ish of a series I started in response to Thomas
Huth's encountering a failure in qemu-img because of missing zstd
support. This series changes the qemu_img() function in iotests.py to
one that raises an Exception on non-zero return code by default.
Alongside this, the
On Tue, 08 Feb 2022 05:07:23 PST (-0800), liyu.yukit...@bytedance.com wrote:
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li
---
On 03/03/2022 16:30, Richard Henderson wrote:
On 3/3/22 07:20, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
LLVM/Clang doesn't know the VSX registers when compiling with
-mabi=elfv1. Use only registers >= 32 and list them with their Altivec
name.
Signed-off-by: Matheus Ferst
On 03/03/2022 15:49, Richard Henderson wrote:
On 3/3/22 07:20, matheus.fe...@eldorado.org.br wrote:
From: Matheus Ferst
Change VSX Scalar Multiply-Add/Subtract Type-A/M Single Precision
helpers to use float64r32_muladd. This method should correctly handle
all rounding modes, so the workaround
Create three separate functions for the three separate registers.
Avoid extra dispatch through op_helper.c.
Dispatch to the correct function in translation.
Clean up the ifdefs in wrctl.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/helper.h| 4 +-
We can thus remove an ifdef covering the entire file.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/nios2/mmu.c | 3 ---
target/nios2/meson.build | 3 +--
2 files changed, 1 insertion(+), 5 deletions(-)
diff --git
It was never correct to be able to write to ipending.
Until the rest of the irq code is tidied, the read of
ipending will generate an "unnecessary" mask.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/nios2/translate.c | 14
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
meson.build | 1 +
target/nios2/mmu.c| 96 ---
target/nios2/trace-events | 10
3 files changed, 39 insertions(+), 68 deletions(-)
Previously, we would avoid setting CPU_INTERRUPT_HARD when interrupts
are disabled at a particular point in time, instead queuing the value
into cpu->irq_pending. This is more complicated than required.
Instead, set CPU_INTERRUPT_HARD any time there is a pending interrupt,
and exclusively check
-nios-20220303
for you to fetch changes up to b72c9d5951f1dfa047f545408dd9e35597e6b9d3:
target/nios2: Rewrite interrupt handling (2022-03-03 09:51:59 -1000)
Rewrite nios2 interrupt handling
This functionality can be had via plugins, if desired.
In the meantime, it is unused code.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/nios2/helper.h| 1 -
target/nios2/mmu.h | 1 -
target/nios2/mmu.c | 20
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