On Mon, Jun 20, 2022 at 10:33:00PM +, Dionna Glaze wrote:
> For SEV-SNP, an OS is "SEV-SNP capable" without supporting this UEFI
> v2.9 memory type. In order for OVMF to be able to avoid pre-validating
> potentially hundreds of gibibytes of data before booting, it needs to
> know if the guest
Hi Richard
On 2022/6/21 上午12:23, Richard Henderson wrote:
On 6/20/22 02:33, Song Gao wrote:
+static int restore_sigcontext(CPULoongArchState *env,
+ struct target_sigcontext *sc)
+{
+ int i;
+ int ret = 0;
+ struct extctx_layout extctx;
+
+ memset(, 0,
On Mon, 2022-06-20 at 11:44 -0400, Peter Xu wrote:
> On Mon, Jun 20, 2022 at 11:23:53AM +0200, Juan Quintela wrote:
> > Once discussed this, what I asked in the past is that you are having too
> > much dirty memory on zero_copy. When you have a Multiterabyte guest, in
> > a single round you have
On Mon, 2022-06-20 at 11:23 +0200, Juan Quintela wrote:
> Leonardo Bras wrote:
> > When sending memory pages with MSG_ZEROCOPY, it's necessary to flush
> > to make sure all dirty pages are sent before a future version of them
> > happens to be sent.
> >
> > Currently, the flush happens every
On 6/19/22 08:15, Richard Henderson wrote:
> Nicely summarized by the reporter, but I thought it would be
> nicer to pull all of the logic into arm_pamax, rather than
> leave it separated.
Reported-by: He Zhe
I ran a quick test. qemu still hangs with these two commits applied.
One fact that
From: Nicholas Piggin
On linux, the AT_HWCAP bit PPC_FEATURE_ICACHE_SNOOP indicates
that we can use a simplified 3 instruction flush sequence.
Signed-off-by: Nicholas Piggin
Message-Id: <20220519141131.29839-1-npig...@gmail.com>
[rth: update after merging cacheflush.c and cacheinfo.c]
Combine the two files into cacheflush.c. There's a couple of bits
that would be helpful to share between the two, and combining them
seems better than exporting the bits.
Signed-off-by: Richard Henderson
---
util/cacheflush.c | 202 +-
Merge init_ctr_el0 into arch_cache_info. In flush_idcache_range,
use the pre-computed line sizes from the global variables.
Use CONFIG_DARWIN in preference to __APPLE__.
Signed-off-by: Richard Henderson
---
util/cacheflush.c | 44 +++-
1 file changed, 19
This is Nick's patch, with the merge of the two files
as I suggested, and the aarch64 cleanup I promised.
r~
Nicholas Piggin (1):
util/cacheflush: Optimize flushing when ppc host has coherent icache
Richard Henderson (2):
util: Merge cacheflush.c and cacheinfo.c
util/cacheflush: Merge
On 6/20/22 09:41, Matheus Kowalczuk Ferst wrote:
On 17/06/2022 07:12, Paolo Bonzini wrote:
Hi Matheus,
could you please test the tests-tcg-next branch at
https://gitlab.com/bonzini/qemu?
At be6090bcac10, it works if no BE toolchain is present. Otherwise, the
script probes
On Thu, Jun 9, 2022 at 2:42 PM Dao Lu wrote:
>
> Added support for RISC-V PAUSE instruction from Zihintpause extension,
> enabled by default.
>
> Tested-by: Heiko Stuebner
> Signed-off-by: Dao Lu
> ---
> target/riscv/cpu.c | 2 ++
> target/riscv/cpu.h
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented
as a unified counter. Thus, the predicate function doesn't need handle each
case separately.
Simplify the predicate function so that we just handle things differently
between RV32/RV64 and S/HS mode.
Reviewed-by: Bin Meng
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions,
and 'cofpmf' for Count OverFlow and Privilege Mode Filtering)
extension allows the perf to handle overflow interrupts and filtering
support. This patch provides a framework for programmable
counters to leverage the extension.
From: Atish Patra
mcycle/minstret are actually WARL registers and can be written with any
given value. With SBI PMU extension, it will be used to store a initial
value provided from supervisor OS. The Qemu also need prohibit the counter
increment if mcountinhibit is set.
Support mcycle/minstret
From: Atish Patra
As per the privilege specification v1.11, mcountinhibit allows to start/stop
a pmu counter selectively.
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu_bits.h |
Qemu virt machine can support few cache events and cycle/instret counters.
It also supports counter overflow for these events.
Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine
capabilities. There are some dummy nodes added for testing as well.
Acked-by: Alistair Francis
The sscofpmf extension was ratified as a part of priv spec v1.12.
Mark the csr_ops accordingly.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 90 ++
1 file changed, 60 insertions(+), 30 deletions(-)
diff --git
The RISC-V privilege specification provides flexibility to implement
any number of counters from 29 programmable counters. However, the QEMU
implements all the counters.
Make it configurable through pmu config parameter which now will indicate
how many programmable counters should be implemented
From: Atish Patra
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as
From: Atish Patra
Qemu can monitor the following cache related PMU events through
tlb_fill functions.
1. DTLB load/store miss
3. ITLB prefetch miss
Increment the PMU counter in tlb_fill function.
Reviewed-by: Alistair Francis
Signed-off-by: Atish Patra
Signed-off-by: Atish Patra
---
The latest version of the SBI specification includes a Performance Monitoring
Unit(PMU) extension[1] which allows the supervisor to start/stop/configure
various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level
extensions, and 'cofpmf' for Count OverFlow and Privilege Mode
From: Atish Patra
Currently, the predicate function for PMU related CSRs only works if
virtualization is enabled. It also does not check mcounteren bits before
before cycle/minstret/hpmcounterx access.
Support supervisor mode access in the predicate function as well.
Reviewed-by: Alistair
From: Atish Patra
With SBI PMU extension, user can use any of the available hpmcounters to
track any perf events based on the value written to mhpmevent csr.
Add read/write functionality for these csrs.
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Signed-off-by: Atish Patra
From: Atish Patra
The predicate function calculates the counter index incorrectly for
hpmcounterx. Fix the counter index to reflect correct CSR number.
Fixes: e39a8320b088 ("target/riscv: Support the Virtual Instruction fault")
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
> On Jun 18, 2022, at 3:05 AM, Samuel Thibault wrote:
>
> Peter Delevoryas, le mer. 15 juin 2022 18:05:26 -0700, a ecrit:
>> With this change, you can now request the out-of-band MAC address from
>> slirp in fby35-bmc:
>>
>>wget
>>
> On Jun 18, 2022, at 3:05 AM, Samuel Thibault wrote:
>
> Peter Delevoryas, le mer. 15 juin 2022 18:05:25 -0700, a ecrit:
>> This lets you set the manufacturer's ID for a slirp netdev, which can be
>> queried from the guest through the Get Version ID NC-SI command. For
>> example, by setting
Currently QEMU ignores madvise(MADV_DONTNEED), which break apps that
rely on this for zeroing out memory [1]. Improve the situation by doing
a passthrough when the range in question is a host-page-aligned
anonymous mapping.
This is based on the patches from Simon Hausmann [2] and Chris Fallin
For SEV-SNP, an OS is "SEV-SNP capable" without supporting this UEFI
v2.9 memory type. In order for OVMF to be able to avoid pre-validating
potentially hundreds of gibibytes of data before booting, it needs to
know if the guest OS can support its use of the new type of memory in
the memory map.
On 6/9/22 03:36, Peter Maydell wrote:
On Wed, 8 Jun 2022 at 03:43, Richard Henderson
wrote:
Semihosting is not enabled for nios2-linux-user.
True, but maybe it ought to be (in an ideal world)?
No, I think ideally there'd be no semihosting for user-only.
If you can write to semihosting,
> On Jun 18, 2022, at 3:03 AM, Samuel Thibault wrote:
>
> Hello,
>
> Peter Delevoryas, le mer. 15 juin 2022 18:05:24 -0700, a ecrit:
>> I think we probably need a new Slirp release
>> (4.8.0) and a switch statement here instead, right?
>>
>> So that we can preserve the behavior for 4.7.0?
>
On Jun 20, 2022, at 12:16 AM, Markus Armbruster
mailto:arm...@redhat.com>> wrote:
Peter Delevoryas mailto:p...@fb.com>> writes:
This lets you set the manufacturer's ID for a slirp netdev, which can be
queried from the guest through the Get Version ID NC-SI command. For
example, by setting the
On 6/13/22 12:07, Hanna Reitz wrote:
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
Now nodes are removed during block-graph update transactions now? Look
at bdrv_replace_child_tran: bdrv_unref() is simply postponed to commit
phase.
What is the problem with it?
We want to make
Changes from v1:
- squashed first 2 commits into 1, because adding PPC_MEM_TLBIE to
P9/P10's insns_flags and moving only tlbie (and not tlbiel) to
decode tree breaks PowerPC64 instruction decoder initialization.
Leandro Lupori (2):
target/ppc: Move tlbie[l] to decode tree
target/ppc:
Also decode RIC, PRS and R operands.
Signed-off-by: Leandro Lupori
---
target/ppc/cpu_init.c| 4 +-
target/ppc/insn32.decode | 8 ++
target/ppc/translate.c | 64 +-
target/ppc/translate/storage-ctrl-impl.c.inc | 87
This initial version supports the invalidation of one or all
TLB entries. Flush by PID/LPID, or based in process/partition
scope is not supported, because it would make using the
generic QEMU TLB implementation hard. In these cases, all
entries are flushed.
Signed-off-by: Leandro Lupori
---
On 6/13/22 10:46, Hanna Reitz wrote:
On 30.03.22 23:28, Vladimir Sementsov-Ogievskiy wrote:
To be used in further commit.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
block.c | 48
1 file changed, 48 insertions(+)
diff --git a/block.c
On Mon, Jun 20, 2022 at 1:13 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/20/22 10:42, Warner Losh wrote:
> > These implement both the old-pre INO64 mknod variations, as well as the
> > now current INO64 variant. To implement the old stuff, we use some
> > linker magic to
Retreieve the refresh rate of the display and reflect it with
dpy_set_ui_info() and update_displaychangelistener(), allowing the
guest and DisplayChangeListener to consume the information.
Signed-off-by: Akihiko Odaki
---
meson.build | 3 ++-
ui/cocoa.m | 12
2 files changed, 14
Check if each page dir/table base address is properly aligned and
log a guest error if not, as real hardware behave incorrectly in
this case.
These checks are only performed when DEBUG_MMU is defined, to avoid
hurting the performance.
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c
Check if the number and size of Radix levels are valid on
POWER9/POWER10 CPUs, according to the supported Radix Tree
Configurations described in their User Manuals.
Signed-off-by: Leandro Lupori
---
target/ppc/mmu-radix64.c | 36 +---
1 file changed, 29
Check if partition and process tables are properly aligned, in
their size, according to PowerISA 3.1B, Book III 6.7.6 programming
note. Hardware and KVM also raise an exception in these cases.
Signed-off-by: Leandro Lupori
---
hw/ppc/spapr.c | 5 +
hw/ppc/spapr_hcall.c |
On PowerPC64 using Radix MMU, when partition or process table is not
properly aligned, according to their size, an exception must be raised
(DSI/ISI/HDSI/HISI) and the "Bad Radix Config" bit must be set in the
appropriate register.
Hardware and KVM already do this, but TCG was missing this part.
On Mon, Jun 20, 2022 at 12:28 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/20/22 10:42, Warner Losh wrote:
> > +static abi_long do_bsd_readlink(CPUArchState *env, abi_long arg1,
> > +abi_long arg2, abi_long arg3)
> > +{
> > +abi_long ret;
> > +void *p1, *p2;
On 3/23/22 10:17, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Reorg TCG AccelOpsClass initialization to emphasis icount
mode share more code with single-threaded TCG.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops.c | 15 ---
1 file changed, 8
On 3/23/22 10:17, Philippe Mathieu-Daudé wrote:
From: Philippe Mathieu-Daudé
Move TCG cflags initialization to thread handler.
Remove the duplicated assert checks.
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tcg-accel-ops-mttcg.c | 5 ++---
accel/tcg/tcg-accel-ops-rr.c| 7
On 3/22/22 02:50, Bin Meng wrote:
CPUClass::memory_rw_debug() holds a callback for GDB memory access.
If not provided, cpu_memory_rw_debug() is used by the GDB stub.
Drop avr_cpu_memory_rw_debug() which does nothing special.
Signed-off-by: Bin Meng
Queued to tcg-next, for lack of anything
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 48 +++
bsd-user/freebsd/os-syscall.c | 16
2 files changed, 64 insertions(+)
Reviewed-by: Richard Henderson
r~
On 6/20/22 12:22, Alexander Graf wrote:
Some features such as running in EL3 or running M profile code are
incompatible with virtualization as QEMU implements it today. To prevent
users from picking invalid configurations on other virt solutions like
Hvf, let's run the same checks there too.
On 6/20/22 12:22, Alexander Graf wrote:
We need to fetch the name of the current accelerator in flexible error
messages more going forward. Let's create a helper that gives it to us
without casting in the target code.
Signed-off-by: Alexander Graf
---
accel/accel-common.c | 8
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 46 +++
bsd-user/freebsd/os-syscall.c | 16
2 files changed, 62 insertions(+)
Reviewed-by: Richard Henderson
r~
* Laurent Vivier (lviv...@redhat.com) wrote:
> "-netdev socket" only supports inet sockets.
>
> It's not a complex task to add support for unix sockets, but
> the socket netdev parameters are not defined to manage well unix
> socket parameters.
>
> As discussed in:
>
> "socket.c added support
On 6/20/22 10:42, Warner Losh wrote:
+/*
+ * XXX arg4 should be locked, but it isn't clear how to do that
+ * since it's it may be not be a NULL-terminated string.
it's it.
Unless you meant https://www.itsiticecream.com/ ;-)
Reviewed-by: Richard Henderson
r~
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 32
bsd-user/freebsd/os-syscall.c | 12
2 files changed, 44 insertions(+)
Reviewed-by: Richard Henderson
r~
We need to fetch the name of the current accelerator in flexible error
messages more going forward. Let's create a helper that gives it to us
without casting in the target code.
Signed-off-by: Alexander Graf
---
accel/accel-common.c | 8
include/qemu/accel.h | 1 +
softmmu/vl.c
Some features such as running in EL3 or running M profile code are
incompatible with virtualization as QEMU implements it today. To prevent
users from picking invalid configurations on other virt solutions like
Hvf, let's run the same checks there too.
Resolves:
Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5cb9f9f02c..13b008547e 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 27 +++
bsd-user/freebsd/os-syscall.c | 8
2 files changed, 35 insertions(+)
Reviewed-by: Richard Henderson
r~
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 19 +++
bsd-user/freebsd/os-syscall.c | 8
2 files changed, 27 insertions(+)
Reviewed-by: Richard Henderson
r~
There's no reason to set CPACR_EL1.ZEN if SVE disabled.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 75295a14a3..5cb9f9f02c 100644
--- a/target/arm/cpu.c
+++
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 13 +
bsd-user/freebsd/os-syscall.c | 4
2 files changed, 17 insertions(+)
Reviewed-by: Richard Henderson
r~
On 6/20/22 10:42, Warner Losh wrote:
Signed-off-by: Stacey Son
Signed-off-by: Warner Losh
---
bsd-user/bsd-file.h | 32
bsd-user/freebsd/os-syscall.c | 12
2 files changed, 44 insertions(+)
Reviewed-by: Richard Henderson
r~
On 6/20/22 10:42, Warner Losh wrote:
These implement both the old-pre INO64 mknod variations, as well as the
now current INO64 variant. To implement the old stuff, we use some
linker magic to bind to the old versions of these functions.
Signed-off-by: Stacey Son
Signed-off-by: Michal Meloun
Add "sve" to the sve prctl functions, to distinguish
them from the coming "sme" prctls with similar names.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_prctl.h | 8
linux-user/syscall.c | 12 ++--
2 files changed, 10 insertions(+), 10
On 08:59 Mon 20 Jun , Richard Henderson wrote:
> On 6/20/22 07:24, Luc Michel wrote:
> > Hi,
> >
> > This series implements a clean way for semihosted exit syscalls to
> > terminate QEMU with a given return code.
> >
> > Until now, exit syscalls implementations consisted in calling exit()
>
Signed-off-by: Richard Henderson
---
linux-user/aarch64/cpu_loop.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c
index 3b273f6299..4af6996d57 100644
--- a/linux-user/aarch64/cpu_loop.c
+++
On 6/20/22 04:27, Mark Cave-Ayland wrote:
On 18/06/2022 12:01, Daniel Henrique Barboza wrote:
It is not advisable to execute an object_dynamic_cast() to poke into
bus->qbus.parent and follow it up with a C cast into the PnvPHB type we
think we got.
A better way is to access the PnvPHB
On 6/20/22 10:42, Warner Losh wrote:
+static abi_long do_bsd_readlink(CPUArchState *env, abi_long arg1,
+abi_long arg2, abi_long arg3)
+{
+abi_long ret;
+void *p1, *p2;
+
+LOCK_PATH(p1, arg1);
+p2 = lock_user(VERIFY_WRITE, arg2, arg3, 0);
+if (p2 == NULL) {
+
Note that SME remains effectively disabled for user-only,
because we do not yet set CPACR_EL1.SMEN. This needs to
wait until the kernel ABI is implemented.
Signed-off-by: Richard Henderson
---
docs/system/arm/emulation.rst | 4
target/arm/cpu64.c| 11 +++
2 files
Signed-off-by: Richard Henderson
---
target/arm/helper-sve.h| 2 ++
target/arm/sve.decode | 1 +
target/arm/sve_helper.c| 16
target/arm/translate-sve.c | 2 ++
4 files changed, 21 insertions(+)
diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h
These prctl set the Streaming SVE vector length, which may
be completely different from the Normal SVE vector length.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_prctl.h | 48 +++
linux-user/syscall.c | 16 +++
2 files changed,
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 18 +++
target/arm/sve.decode | 5 ++
target/arm/translate-sve.c | 102 +
target/arm/vec_helper.c| 24 +
4 files changed, 149 insertions(+)
diff --git
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 8fbe98d72f..9ff79da4be 100644
--- a/linux-user/aarch64/signal.c
+++ b/linux-user/aarch64/signal.c
@@ -340,6
On 6/20/22 17:36, Joao Martins wrote:
> On 6/20/22 15:27, Igor Mammedov wrote:
>> On Fri, 17 Jun 2022 14:33:02 +0100
>> Joao Martins wrote:
>>> On 6/17/22 13:32, Igor Mammedov wrote:
On Fri, 17 Jun 2022 13:18:38 +0100
Joao Martins wrote:
> On 6/16/22 15:23, Igor Mammedov wrote:
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 5 +++
target/arm/sme.decode | 9 +
target/arm/sme_helper.c| 67 ++
target/arm/translate-sme.c | 33 +++
4 files changed, 114 insertions(+)
diff --git
This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16.
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 16
target/arm/sme.decode | 10 +
target/arm/sme_helper.c| 82 ++
target/arm/translate-sme.c | 14 +++
We cannot reuse the SVE functions for LD[1-4] and ST[1-4],
because those functions accept only a Zreg register number.
For SME, we want to pass a pointer into ZA storage.
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 82 +
target/arm/sme.decode | 9 +
Signed-off-by: Richard Henderson
---
linux-user/aarch64/target_cpu.h | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-user/aarch64/target_cpu.h b/linux-user/aarch64/target_cpu.h
index 97a477bd3e..f90359faf2 100644
--- a/linux-user/aarch64/target_cpu.h
+++
Move the checks out of the parsing loop and into the
restore function. This more closely mirrors the code
structure in the kernel, and is slightly clearer.
Reject rather than silently skip incorrect VL and SVE record sizes.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 51
Signed-off-by: Richard Henderson
---
linux-user/elfload.c | 20
1 file changed, 20 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index f7eae357f4..8135960305 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -601,6 +601,18 @@ enum {
Fold the return value setting into the goto, so each
point of failure need not do both.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/linux-user/aarch64/signal.c
We can reuse the SVE functions for LDR and STR, passing in the
base of the ZA vector and a zero offset.
Signed-off-by: Richard Henderson
---
target/arm/sme.decode | 7 +++
target/arm/translate-sme.c | 23 +++
2 files changed, 30 insertions(+)
diff --git
This new behaviour is in the ARM pseudocode function
AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32
via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which
the trap would be delivered is in AArch64 mode.
Given that ARMv9 drops support for AArch32 outside EL0,
the trap EL detection ought
Set the SM bit in the SVE record on signal delivery, create the ZA record.
Restore SM and ZA state according to the records present on return.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 162 +---
1 file changed, 151 insertions(+), 11
Signed-off-by: Richard Henderson
---
target/arm/sve.decode | 20 +
target/arm/translate-sve.c | 57 ++
2 files changed, 77 insertions(+)
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index bbdaac6ac7..bf561c270a 100644
---
Mirror the properties for SVE. The main difference is
that any arbitrary set of powers of 2 may be supported,
and not the stricter constraints that apply to SVE.
Include a property to control FEAT_SME_FA64, as failing
to restrict the runtime to the proper subset of insns
could be a major point
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 2 ++
target/arm/translate-a64.h | 1 +
target/arm/sme.decode | 4
target/arm/sme_helper.c| 25 +
target/arm/translate-a64.c | 14 ++
target/arm/translate-sme.c | 13
In parse_user_sigframe, the kernel rejects duplicate sve records,
or records that are smaller than the header. We were silently
allowing these cases to pass, dropping the record.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 5 -
1 file changed, 4 insertions(+), 1
We can handle both exception entry and exception return by
hooking into aarch64_sve_change_el.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index
We can reuse the SVE functions for implementing moves to/from
horizontal tile slices, but we need new ones for moves to/from
vertical tile slices.
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 11
target/arm/helper-sve.h| 2 +
target/arm/translate-a64.h | 9 +++
Drop the aa32-only inline fallbacks,
and just use a couple of ifdefs.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 --
target/arm/internals.h | 3 +++
target/arm/cpu.c | 2 ++
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 5 +++
target/arm/sme.decode | 11 +
target/arm/sme_helper.c| 90 ++
target/arm/translate-sme.c | 30 +
4 files changed, 136 insertions(+)
diff --git
Make sure to zero the currently reserved fields.
Signed-off-by: Richard Henderson
---
linux-user/aarch64/signal.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c
index 7da0e36c6d..3cef2f44cf 100644
---
These SME instructions are nominally within the SVE decode space,
so we add them to sve.decode and translate-sve.c.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 1 +
target/arm/sve.decode | 5 -
target/arm/translate-a64.c | 15 +++
Pull the three sve_vq_* values into a structure.
This will be reused for SME.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 29 ++---
target/arm/cpu64.c | 22 +++---
target/arm/helper.c | 2 +-
target/arm/kvm64.c
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 2 ++
target/arm/sme.decode | 1 +
target/arm/sme_helper.c| 74 ++
target/arm/translate-sme.c | 2 ++
4 files changed, 79 insertions(+)
diff --git a/target/arm/helper-sme.h
Add a TCGv_ptr base argument, which will be cpu_env for SVE.
We will reuse this for SME save and restore array insns.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 3 +++
target/arm/translate-sve.c | 48 --
2 files changed, 39
These two instructions are aliases of MSR (immediate).
Use the two helpers to properly implement svcr_write.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 +
target/arm/helper-sme.h| 21 +
target/arm/helper.h| 1 +
We will need these functions in translate-sme.c.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 38 ++
target/arm/translate-sve.c | 36
2 files changed, 38 insertions(+), 36
Signed-off-by: Richard Henderson
---
target/arm/helper-sme.h| 2 ++
target/arm/sme.decode | 2 ++
target/arm/sme_helper.c| 52 ++
target/arm/translate-sme.c | 29 +
4 files changed, 85 insertions(+)
diff --git
Place this late in the resettable section of the structure,
to keep the most common element offsets from being > 64k.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 8
target/arm/machine.c | 34 ++
2 files
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