Re: AST2600 support in QEMU

Hello, On 8/10/22 04:37, Joel Stanley wrote: Hello Shivi, I've added others to cc who may have some input. On Tue, 9 Aug 2022 at 21:38, Shivi Fotedar wrote: Hello, we are looking for support for few features for AST2600 in QEMU, specifically PCIe RC support so BMC can talk to downstream

Re: [PATCH v8 3/3] target/riscv: Add vstimecmp support

On Tue, Aug 9, 2022 at 6:33 PM Weiwei Li wrote: > > 在 2022/8/10 上午3:34, Atish Kumar Patra 写道: > > > > > On Tue, Aug 9, 2022 at 12:01 AM Weiwei Li wrote: > >> >> 在 2022/8/9 上午1:20, Atish Kumar Patra 写道: >> >> >> >> On Sun, Aug 7, 2022 at 6:50 PM Weiwei Li wrote: >> >>> >>> 在 2022/8/4 上午9:42,

Re: [PATCH v8 10/12] vhost_net: add NetClientState->load() callback

On Wed, Aug 10, 2022 at 1:40 AM Eugenio Pérez wrote: > > It allows per-net client operations right after device's successful > start. In particular, to load the device status. > > Vhost-vdpa net will use it to add the CVQ buffers to restore the device > status. > > Signed-off-by: Eugenio Pérez

Re: [PATCH v8 07/12] vdpa: add net_vhost_vdpa_cvq_info NetClientInfo

On Wed, Aug 10, 2022 at 1:39 AM Eugenio Pérez wrote: > > Next patches will add a new info callback to restore NIC status through > CVQ. Since only the CVQ vhost device is needed, create it with a new > NetClientInfo. > > Signed-off-by: Eugenio Pérez Acked-by: Jason Wang > --- > v5: Create a

Re: [PATCH v8 11/12] vdpa: Add virtio-net mac address via CVQ at start

On Wed, Aug 10, 2022 at 1:40 AM Eugenio Pérez wrote: > > This is needed so the destination vdpa device see the same state a the > guest set in the source. > > Signed-off-by: Eugenio Pérez > --- > v8: > * Delete unneeded copy from device's in buffer. > > v6: > * Map and unmap command buffers at

Re: [PATCH v8 06/12] vhost_net: Add NetClientInfo stop callback

On Wed, Aug 10, 2022 at 1:39 AM Eugenio Pérez wrote: > > Used by the backend to perform actions after the device is stopped. > > In particular, vdpa net use it to unmap CVQ buffers to the device, > cleaning the actions performend in prepare(). Should be "performed". Other than this, Acked-by:

Re: [PATCH v8 08/12] vdpa: Move command buffers map to start of net device

On Wed, Aug 10, 2022 at 1:39 AM Eugenio Pérez wrote: > > As this series will reuse them to restore the device state at the end of > a migration (or a device start), let's allocate only once at the device > start so we don't duplicate their map and unmap. > > Signed-off-by: Eugenio Pérez

Re: [PATCH v8 05/12] vhost_net: Add NetClientInfo prepare callback

On Wed, Aug 10, 2022 at 1:39 AM Eugenio Pérez wrote: > > This is used by the backend to perform actions before the device is > started. > > In particular, vdpa net use it to map CVQ buffers to the device, so it > can send control commands using them. > > Signed-off-by: Eugenio Pérez > --- So

Re: AST2600 support in QEMU

Hello Shivi, I've added others to cc who may have some input. On Tue, 9 Aug 2022 at 21:38, Shivi Fotedar wrote: > > Hello, we are looking for support for few features for AST2600 in QEMU, > specifically > > PCIe RC support so BMC can talk to downstream devices for management > functions. I

Re: [PATCH v8 3/3] target/riscv: Add vstimecmp support

在 2022/8/10 上午3:34, Atish Kumar Patra 写道: On Tue, Aug 9, 2022 at 12:01 AM Weiwei Li > wrote: 在 2022/8/9 上午1:20, Atish Kumar Patra 写道: On Sun, Aug 7, 2022 at 6:50 PM Weiwei Li mailto:liwei...@iscas.ac.cn>> wrote: 在 2022/8/4 上午9:42, Atish

[PATCH for-7.1] cutils: Add missing dyld(3) include on macOS

Commit 06680b15b4 moved qemu_*_exec_dir() to cutils but forgot to move the macOS dyld(3) include, resulting in the following error (when building with Homebrew GCC on macOS Monterey 12.4): [313/1197] Compiling C object libqemuutil.a.p/util_cutils.c.o FAILED: libqemuutil.a.p/util_cutils.c.o

Re: [PULL 0/2] Trivial branch for 7.1 patches

) Pull request trivial branch 20220809 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate. r~ Markus Armbruster (1): contrib/vhost-user-blk: Clean up deallocation of VuVirtqElement Qiang Liu (1

AST2600 support in QEMU

Hello, we are looking for support for few features for AST2600 in QEMU, specifically * PCIe RC support so BMC can talk to downstream devices for management functions. * MCTP controller to run MCTP protocol on top of PCIe or I2C. * I2C slave so BMC can talk to host CPU QEMU for IPMI

Re: [PATCH v3 3/5] hw/core: use qemu_fdt_setprop_strings()

On Tue, 9 Aug 2022 at 19:50, Ben Dooks wrote: > > On Mon, Aug 01, 2022 at 12:30:22PM +0100, Peter Maydell wrote: > > On Wed, 27 Jul 2022 at 23:39, Ben Dooks wrote: > > > > > > Change to using the qemu_fdt_setprop_strings() helper in > > > hw/core code. > > > > > > Signed-off-by: Ben Dooks > > >

Re: [PATCH v8 3/3] target/riscv: Add vstimecmp support

On Tue, Aug 9, 2022 at 12:01 AM Weiwei Li wrote: > > 在 2022/8/9 上午1:20, Atish Kumar Patra 写道: > > > > On Sun, Aug 7, 2022 at 6:50 PM Weiwei Li wrote: > >> >> 在 2022/8/4 上午9:42, Atish Patra 写道: >> > vstimecmp CSR allows the guest OS or to program the next guest timer >> > interrupt directly.

Re: [PATCH v3 5/5] hw/arm: change to use qemu_fdt_setprop_strings()

On 09/08/2022 20:22, Peter Maydell wrote: On Tue, 9 Aug 2022 at 19:48, Ben Dooks wrote: On Mon, Aug 01, 2022 at 12:37:33PM +0100, Peter Maydell wrote: On Wed, 27 Jul 2022 at 23:44, Ben Dooks wrote: @@ -285,8 +280,6 @@ static void fdt_add_gem_nodes(VersalVirt *s) static void

Re: [PATCH v3 5/5] hw/arm: change to use qemu_fdt_setprop_strings()

On Tue, 9 Aug 2022 at 19:48, Ben Dooks wrote: > > On Mon, Aug 01, 2022 at 12:37:33PM +0100, Peter Maydell wrote: > > On Wed, 27 Jul 2022 at 23:44, Ben Dooks wrote: > > > @@ -285,8 +280,6 @@ static void fdt_add_gem_nodes(VersalVirt *s) > > > > > > static void fdt_add_zdma_nodes(VersalVirt *s) >

Re: [PULL 0/1] target-arm queue

repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220809 for you to fetch changes up to c7f26ded6d5065e4116f630f6a490b55f6c5f58e: icount: Take iothread lock when running QEMU timers (2022-08-09 10:55:14 +0100

[PATCH v4 6/6] hw/arm: change to use qemu_fdt_setprop_strings()

Change to using qemu_fdt_setprop_strings() instead of using \0 separated string arrays. Note, also there were a few places where qemu_fdt_setprop_string() can be used in the same areas. Signed-off-by: Ben Dooks --- v4: - fixed checkpatch errors with string - fixed patch subject ---

[PATCH v4 4/6] hw/core: use qemu_fdt_setprop_strings()

Change to using the qemu_fdt_setprop_strings() helper in hw/core code. Signed-off-by: Ben Dooks --- hw/core/guest-loader.c | 13 + 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c index c61ebc4144..7b8e32e06f 100644 ---

Re: add qemu_fdt_setprop_strings() and use it in most places

On Tue, Aug 09, 2022 at 07:56:34PM +0100, Ben Dooks wrote: > Add a helper for qemu_fdt_setprop_strings() to take a set of strings > to put into a device-tree, which removes several open-coded methods > such as setting an char arr[] = {..} or setting char val[] = "str\0str2"; > > > This is

[PATCH v4 1/6] device_tree: add qemu_fdt_setprop_strings() helper

Add a helper to set a property from a set of strings to reduce the following code: static const char * const clint_compat[2] = { "sifive,clint0", "riscv,clint0" }; qemu_fdt_setprop_string_array(fdt, nodename, "compatible", (char **)_compat, ARRAY_SIZE(clint_compat));

[PATCH v4 2/6] hw/core: don't check return on qemu_fdt_setprop_string_array()

The qemu_fdt_setprop_string_array() does not return error codes and will call exit() if any of the fdt calls fails (and should print an error with the node being altered). This is done to prepare for the change for qemu_fdt_setprop_strings() helper which does not return any error codes

add qemu_fdt_setprop_strings() and use it in most places

Add a helper for qemu_fdt_setprop_strings() to take a set of strings to put into a device-tree, which removes several open-coded methods such as setting an char arr[] = {..} or setting char val[] = "str\0str2"; This is for hw/arm, hw/mips and hw/riscv as well as a couple of cores. It is

[PATCH v4 5/6] hw/mips: use qemu_fdt_setprop_strings()

Change to using qemu_fdt_setprop_strings() helper in hw/mips. Signed-off-by: Ben Dooks Reviewed-by: Peter Maydell --- hw/mips/boston.c | 8 ++-- 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index d2ab9da1a0..759f6daafe 100644 ---

[PATCH v4 3/6] hw/riscv: use qemu_fdt_setprop_strings() for string arrays

Use the qemu_fdt_setprop_strings() in sifve_u.c to simplify the code. Signed-off-by: Ben Dooks --- hw/riscv/sifive_u.c | 18 +- hw/riscv/spike.c| 7 ++- hw/riscv/virt.c | 32 3 files changed, 15 insertions(+), 42 deletions(-) diff

Re: [PATCH v3 3/5] hw/core: use qemu_fdt_setprop_strings()

On Mon, Aug 01, 2022 at 12:30:22PM +0100, Peter Maydell wrote: > On Wed, 27 Jul 2022 at 23:39, Ben Dooks wrote: > > > > Change to using the qemu_fdt_setprop_strings() helper in > > hw/core code. > > > > Signed-off-by: Ben Dooks > > --- > > Reviewed-by: Peter Maydell I've had to make a second

Re: [PATCH v3 5/5] hw/arm: change to use qemu_fdt_setprop_strings()

On Mon, Aug 01, 2022 at 12:37:33PM +0100, Peter Maydell wrote: > On Wed, 27 Jul 2022 at 23:44, Ben Dooks wrote: > > > > Change to using qemu_fdt_setprop_strings() instead of using > > \0 separated string arrays. > > > > Signed-off-by: Ben Dooks > > --- > > hw/arm/boot.c | 8 +++---

Re: [PATCH v3 1/2] Update AVX512 support for xbzrle_encode_buffer function

On 8/8/22 00:48, ling xu wrote: This commit update runtime check of AVX512, and implements avx512 of xbzrle_encode_buffer function to accelerate xbzrle encoding speed. Compared with C version of xbzrle_encode_buffer function, avx512 version can achieve almost 60%-70% performance improvement on

Re: [PATCH v3 2/2] Test code for AVX512 support for xbzrle_encode_buffer

On 8/8/22 00:48, ling xu wrote: Signed-off-by: ling xu Co-authored-by: Zhou Zhao Co-authored-by: Jun Jin --- tests/unit/test-xbzrle.c | 307 --- 1 file changed, 290 insertions(+), 17 deletions(-) diff --git a/tests/unit/test-xbzrle.c

Re: [PATCH v3 1/2] Update AVX512 support for xbzrle_encode_buffer function

On 8/9/22 00:51, Xu, Ling1 wrote: Hi, Juan, Thanks for your advice. We have revised our code including: 1) change "IS_CPU_SUPPORT_AVX512BW" to "is_cpu_support_avx512bw" to indicate that variable isn't global variable; You can remove this variable entirely... 2) use a function

Re: [PATCH v4 24/24] ppc/ppc405: Add check on minimum RAM size

On Tue, 9 Aug 2022, Cédric Le Goater wrote: The check on invalid RAM size is now performed in the SDRAM controller but not all values will boot a machine. A minimum of 2*16 is required. 2*16 or 16 MiB? The code has the latter which does not match commit message. Regards, BALATON Zoltan

Re: [PATCH RFC 0/7] hostmem: NUMA-aware memory preallocation using ThreadContext

On 09.08.22 12:56, Joao Martins wrote: > On 7/21/22 13:07, David Hildenbrand wrote: >> This is a follow-up on "util: NUMA aware memory preallocation" [1] by >> Michal. >> >> Setting the CPU affinity of threads from inside QEMU usually isn't >> easily possible, because we don't want QEMU -- once

Re: [PATCH v4 20/24] ppc/ppc405: Use an embedded PPCUIC model in SoC state

On Tue, 9 Aug 2022, Cédric Le Goater wrote: Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater Reviewed-by: BALATON Zoltan --- hw/ppc/ppc405.h| 3 ++- hw/ppc/ppc405_uc.c | 26 +- 2 files changed, 15 insertions(+), 14 deletions(-) diff --git

[PATCH v8 12/12] vdpa: Delete CVQ migration blocker

We can restore the device state in the destination via CVQ now. Remove the migration blocker. Signed-off-by: Eugenio Pérez Acked-by: Jason Wang --- include/hw/virtio/vhost-vdpa.h | 1 - hw/virtio/vhost-vdpa.c | 14 -- net/vhost-vdpa.c | 2 -- 3 files

Re: [PATCH v4 22/24] ppc/ppc4xx: Fix sdram trace events

On Tue, 9 Aug 2022, Cédric Le Goater wrote: Signed-off-by: Cédric Le Goater Reviewed-by: BALATON Zoltan --- hw/ppc/ppc4xx_devs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 8a8a87b03b28..c06c20b195cd 100644 ---

[PATCH v8 08/12] vdpa: Move command buffers map to start of net device

As this series will reuse them to restore the device state at the end of a migration (or a device start), let's allocate only once at the device start so we don't duplicate their map and unmap. Signed-off-by: Eugenio Pérez --- net/vhost-vdpa.c | 123

[PATCH v8 07/12] vdpa: add net_vhost_vdpa_cvq_info NetClientInfo

Next patches will add a new info callback to restore NIC status through CVQ. Since only the CVQ vhost device is needed, create it with a new NetClientInfo. Signed-off-by: Eugenio Pérez --- v5: Create a new NetClientInfo instead of reusing the dataplane one. --- net/vhost-vdpa.c | 12

Re: [PATCH v4 23/24] ppc/ppc405: QOM'ify SDRAM

On Tue, 9 Aug 2022, Cédric Le Goater wrote: This is an initial change of the SDRAM controller preserving the compatibility with the current modeling. Further cleanup will be possible after conversion of the ppc4xx_sdram_banks() and ppc4xx_sdram_init() routines of the sam460ex and bamboo

[PATCH v8 05/12] vhost_net: Add NetClientInfo prepare callback

This is used by the backend to perform actions before the device is started. In particular, vdpa net use it to map CVQ buffers to the device, so it can send control commands using them. Signed-off-by: Eugenio Pérez --- v8: Rename NetClientInfo prepare callback to start, so it aligns with

Re: [PATCH v4 04/24] ppc/ppc405: Move SRAM under the ref405ep machine

On 8/9/22 18:53, BALATON Zoltan wrote: On Tue, 9 Aug 2022, Cédric Le Goater wrote: It doesn't belong to the generic machine nor the SoC. Fix a typo in the name while we are at it. Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 12 ++-- 1 file changed, 6 insertions(+), 6

Re: [PATCH v4 21/24] ppc/ppc405: Use an explicit I2C object

On Tue, 9 Aug 2022, Cédric Le Goater wrote: Having an explicit I2C model object will help if one day we want to add I2C devices on the bus from the machine init routine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 2 ++ hw/ppc/ppc405_uc.c | 10

[PATCH v8 02/12] vhost: use SVQ element ndescs instead of opaque data for desc validation

Since we're going to allow SVQ to add elements without the guest's knowledge and without its own VirtQueueElement, it's easier to check if an element is a valid head checking a different thing than the VirtQueueElement. Signed-off-by: Eugenio Pérez Acked-by: Jason Wang ---

[PATCH v8 11/12] vdpa: Add virtio-net mac address via CVQ at start

This is needed so the destination vdpa device see the same state a the guest set in the source. Signed-off-by: Eugenio Pérez --- v8: * Delete unneeded copy from device's in buffer. v6: * Map and unmap command buffers at the start and end of device usage. v5: * Rename s/start/load/ * Use

[PATCH v8 09/12] vdpa: extract vhost_vdpa_net_cvq_add from vhost_vdpa_net_handle_ctrl_avail

So we can reuse it to inject state messages. Signed-off-by: Eugenio Pérez Acked-by: Jason Wang -- v7: * Remove double free error v6: * Do not assume in buffer sent to the device is sizeof(virtio_net_ctrl_ack) v5: * Do not use an artificial !NULL VirtQueueElement * Use only out size instead of

[PATCH v8 04/12] vhost: Do not depend on !NULL VirtQueueElement on vhost_svq_flush

Since QEMU will be able to inject new elements on CVQ to restore the state, we need not to depend on a VirtQueueElement to know if a new element has been used by the device or not. Instead of check that, check if there are new elements only using used idx on vhost_svq_flush. Signed-off-by:

[PATCH v8 10/12] vhost_net: add NetClientState->load() callback

It allows per-net client operations right after device's successful start. In particular, to load the device status. Vhost-vdpa net will use it to add the CVQ buffers to restore the device status. Signed-off-by: Eugenio Pérez --- v5: Rename start / load, naming it more specifically. ---

[PATCH v8 03/12] vhost: Delete useless read memory barrier

As discussed in previous series [1], this memory barrier is useless with the atomic read of used idx at vhost_svq_more_used. Deleting it. [1] https://lists.nongnu.org/archive/html/qemu-devel/2022-07/msg02616.html Signed-off-by: Eugenio Pérez Acked-by: Jason Wang ---

[PATCH v8 01/12] vhost: stop transfer elem ownership in vhost_handle_guest_kick

It was easier to allow vhost_svq_add to handle the memory. Now that we will allow qemu to add elements to a SVQ without the guest's knowledge, it's better to handle it in the caller. Signed-off-by: Eugenio Pérez Acked-by: Jason Wang --- hw/virtio/vhost-shadow-virtqueue.c | 10 -- 1

[PATCH v8 06/12] vhost_net: Add NetClientInfo stop callback

Used by the backend to perform actions after the device is stopped. In particular, vdpa net use it to unmap CVQ buffers to the device, cleaning the actions performend in prepare(). Signed-off-by: Eugenio Pérez --- include/net/net.h | 2 ++ hw/net/vhost_net.c | 3 +++ 2 files changed, 5

[PATCH v8 00/12] NIC vhost-vdpa state restore via Shadow CVQ

CVQ of net vhost-vdpa devices can be intercepted since the addition of x-svq. The virtio-net device model is updated. The migration was blocked because although the state can be megrated between VMM it was not possible to restore on the destination NIC. This series add support for SVQ to inject

Re: [PATCH v4 07/24] ppc/ppc405: QOM'ify CPU

Since maybe there will be another version, this patch is still misnamed, I think it's not QOMifying but embeds the cpu in the soc. Regards, BALATON Zoltan On Tue, 9 Aug 2022, Cédric Le Goater wrote: Drop the use of ppc4xx_init() and duplicate a bit of code related to clocks in the SoC

Re: [PATCH v4 19/24] ppc/ppc405: QOM'ify FPGA

On Tue, 9 Aug 2022, Cédric Le Goater wrote: Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 55 +- 1 file changed, 38 insertions(+), 17 deletions(-) diff --git a/hw/ppc/ppc405_boards.c

Re: [PATCH v4 18/24] ppc/ppc405: QOM'ify MAL

On Tue, 9 Aug 2022, Cédric Le Goater wrote: The Memory Access Layer (MAL) controller is currently modeled as a DCR device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt the sam460ex machine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater ---

Re: [PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model

On Tue, 9 Aug 2022, Cédric Le Goater wrote: The Device Control Registers (DCR) of on-SoC devices are accessed by software through the use of the mtdcr and mfdcr instructions. These are converted in transactions on a side band bus, the DCR bus, which connects the on-SoC devices to the CPU.

Re: [PATCH v4 06/24] ppc/ppc405: Start QOMification of the SoC

On Tue, 9 Aug 2022, Cédric Le Goater wrote: This moves all the code previously done in the ppc405ep_init() routine under ppc405_soc_realize(). We can also adjust the number of banks now that we have control on ppc4xx_sdram_init(). Signed-off-by: Cédric Le Goater Reviewed-by: BALATON Zoltan

Re: [PATCH v4 07/24] ppc/ppc405: QOM'ify CPU

On Tue, 9 Aug 2022, Cédric Le Goater wrote: Drop the use of ppc4xx_init() and duplicate a bit of code related to clocks in the SoC realize routine. We will clean that up in the following patches. ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe this could be done in model

Re: [PATCH v2 2/2] util/aio-win32: Correct the event array size in aio_poll()

On Tue, Aug 9, 2022 at 8:43 PM Bin Meng wrote: > From: Bin Meng > > WaitForMultipleObjects() can only wait for MAXIMUM_WAIT_OBJECTS > object handles. Correct the event array size in aio_poll() and > add a assert() to ensure it does not cause out of bound access. > > Signed-off-by: Bin Meng >

Re: [PATCH v4 4/6] vdpa: Add asid parameter to vhost_vdpa_dma_map/unmap

On Tue, Aug 9, 2022 at 9:21 AM Jason Wang wrote: > > On Sat, Aug 6, 2022 at 12:39 AM Eugenio Pérez wrote: > > > > So the caller can choose which ASID is destined. > > > > No need to update the batch functions as they will always be called from > > memory listener updates at the moment. Memory

Re: Re: [RFC] hw/nvme: Use irqfd to send interrupts

On Wed, Aug 10, 2022 at 12:48:53AM +0800, 樊金昊 wrote: >> The driver will create the cq with an allocated vector, but it's not >> activated >> until after the driver wires it up to a handler. I think that's what you're >> observing with the incomplete MSIx table entry on creation. > > Also, I'm

Re: [PATCH v2 1/2] util/main-loop: Fix maximum number of wait objects for win32

Hi On Tue, Aug 9, 2022 at 8:43 PM Bin Meng wrote: > From: Bin Meng > > The maximum number of wait objects for win32 should be > MAXIMUM_WAIT_OBJECTS, not MAXIMUM_WAIT_OBJECTS + 1. > > Fix the logic in qemu_add_wait_object() to avoid adding > the same HANDLE twice. > > Please make that a

Re: [PATCH v4 05/24] ppc/ppc405: Introduce a PPC405 SoC

On Tue, 9 Aug 2022, Cédric Le Goater wrote: It is an initial model to start QOMification of the PPC405 board. QOM'ified devices will be reintroduced one by one. Start with the memory regions, which name prefix is changed to "ppc405". Also, initialize only one RAM bank. The second bank is a

[PULL 1/2] contrib/vhost-user-blk: Clean up deallocation of VuVirtqElement

From: Markus Armbruster We allocate VuVirtqElement with g_malloc() in virtqueue_alloc_element(), but free it with free() in vhost-user-blk.c. Harmless, but use g_free() anyway. One of the calls is guarded by a "not null" condition. Useless, because it cannot be null (it's dereferenced right

[PULL 2/2] xlnx_dp: drop unsupported AUXCommand in xlnx_dp_aux_set_command

From: Qiang Liu In xlnx_dp_aux_set_command, when the command leads to the default branch, xlxn-dp will abort and then crash. This patch removes this abort and drops this operation. Fixes: 58ac482 ("introduce xlnx-dp") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/411 Reported-by:

[PULL 0/2] Trivial branch for 7.1 patches

-for-7.1-pull-request for you to fetch changes up to 9390da5ef29a5e0f98e5b482dceeeb287c452f17: xlnx_dp: drop unsupported AUXCommand in xlnx_dp_aux_set_command (2022-08-08 11:40:06 +0200) Pull request trivial branch 20220809

Re: [PATCH v4 04/24] ppc/ppc405: Move SRAM under the ref405ep machine

On Tue, 9 Aug 2022, Cédric Le Goater wrote: It doesn't belong to the generic machine nor the SoC. Fix a typo in the name while we are at it. Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git

Re: Re: [RFC] hw/nvme: Use irqfd to send interrupts

The driver will create the cq with an allocated vector, but it's not activated until after the driver wires it up to a handler. I think that's what you're observing with the incomplete MSIx table entry on creation. Also, I'm wondering if this is inconsistent with the NVMe spec. In Section

[PATCH v2 2/2] util/aio-win32: Correct the event array size in aio_poll()

From: Bin Meng WaitForMultipleObjects() can only wait for MAXIMUM_WAIT_OBJECTS object handles. Correct the event array size in aio_poll() and add a assert() to ensure it does not cause out of bound access. Signed-off-by: Bin Meng Reviewed-by: Stefan Weil --- Changes in v2: - change 'count'

Re: [PULL] Net patches

On 8/9/22 02:08, Jason Wang wrote: The following changes since commit ca5f3d4df1b47d7f66a109cdb504e83dfd7ec433: Merge tag 'pull-la-20220808' of https://gitlab.com/rth7680/qemu into staging (2022-08-08 19:51:12 -0700) are available in the git repository at:

[PATCH v2 1/2] util/main-loop: Fix maximum number of wait objects for win32

From: Bin Meng The maximum number of wait objects for win32 should be MAXIMUM_WAIT_OBJECTS, not MAXIMUM_WAIT_OBJECTS + 1. Fix the logic in qemu_add_wait_object() to avoid adding the same HANDLE twice. Signed-off-by: Bin Meng --- Changes in v2: - fix the logic in qemu_add_wait_object() to

Re: [PATCH 1/2] util/main-loop: Fix maximum number of wait objects for win32

On Tue, Aug 9, 2022 at 9:15 PM Marc-André Lureau wrote: > > Hi > > On Fri, Aug 5, 2022 at 6:57 PM Bin Meng wrote: >> >> From: Bin Meng >> >> The maximum number of wait objects for win32 should be >> MAXIMUM_WAIT_OBJECTS, not MAXIMUM_WAIT_OBJECTS + 1. >> >> Signed-off-by: Bin Meng > > > Nack, >

Re: Re: [RFC] hw/nvme: Use irqfd to send interrupts

The driver will create the cq with an allocated vector, but it's not activated until after the driver wires it up to a handler. I think that's what you're observing with the incomplete MSIx table entry on creation. Agreed. I digged through pci_request_irq()'s call chain and found

Re: [PATCH 2/2] util/aio-win32: Correct the event array size in aio_poll()

On Fri, Aug 5, 2022 at 11:09 PM Stefan Weil wrote: > > Am 05.08.22 um 16:56 schrieb Bin Meng: > > > From: Bin Meng > > > > WaitForMultipleObjects() can only wait for MAXIMUM_WAIT_OBJECTS > > object handles. Correct the event array size in aio_poll() and > > add a assert() to ensure it does not

Re: [RFC] hw/nvme: Use irqfd to send interrupts

On Mon, Aug 08, 2022 at 10:23:03AM +0800, Jinhao Fan wrote: > at 12:35 PM, Jinhao Fan wrote: > > > static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq) > > { > > if (cq->irq_enabled) { > > if (msix_enabled(&(n->parent_obj))) { > > +/* Initialize CQ irqfd */ > > +

Re: [BUG] cxl can not create region

On Tue, 9 Aug 2022 21:07:06 +0800 Bobo WL wrote: > Hi Jonathan > > Thanks for your reply! > > On Mon, Aug 8, 2022 at 8:37 PM Jonathan Cameron > wrote: > > > > Probably not related to your problem, but there is a disconnect in QEMU / > > kernel assumptionsaround the presence of an HDM decoder

[PATCH v4 24/24] ppc/ppc405: Add check on minimum RAM size

The check on invalid RAM size is now performed in the SDRAM controller but not all values will boot a machine. A minimum of 2*16 is required. Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git

[PATCH v4 21/24] ppc/ppc405: Use an explicit I2C object

Having an explicit I2C model object will help if one day we want to add I2C devices on the bus from the machine init routine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 2 ++ hw/ppc/ppc405_uc.c | 10 -- 2 files changed, 10

[PATCH v4 23/24] ppc/ppc405: QOM'ify SDRAM

This is an initial change of the SDRAM controller preserving the compatibility with the current modeling. Further cleanup will be possible after conversion of the ppc4xx_sdram_banks() and ppc4xx_sdram_init() routines of the sam460ex and bamboo machines. The size and base address of the RAM banks

[PATCH v4 22/24] ppc/ppc4xx: Fix sdram trace events

Signed-off-by: Cédric Le Goater --- hw/ppc/ppc4xx_devs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 8a8a87b03b28..c06c20b195cd 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -143,7 +143,7 @@ static void

[PATCH v4 14/24] ppc/ppc405: QOM'ify EBC

EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init() helper and adapt the sam460ex machine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 17 +- hw/ppc/ppc405_uc.c | 57

[PATCH v4 18/24] ppc/ppc405: QOM'ify MAL

The Memory Access Layer (MAL) controller is currently modeled as a DCR device with 4 IRQs. Also drop the ppc4xx_mal_init() helper and adapt the sam460ex machine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 1 + include/hw/ppc/ppc4xx.h |

[PATCH v4 17/24] ppc/ppc405: QOM'ify PLB

PLB is currently modeled as a simple DCR device. Also drop the ppc4xx_plb_init() helper and adapt the sam460ex machine. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 14 +-- hw/ppc/ppc405_uc.c | 59

[PATCH v4 19/24] ppc/ppc405: QOM'ify FPGA

Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 55 +- 1 file changed, 38 insertions(+), 17 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 3677793adc75..4ff6715f3533

[PATCH v4 13/24] ppc/ppc405: QOM'ify DMA

The DMA controller is currently modeled as a DCR device with a couple of IRQs. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 19 ++ hw/ppc/ppc405_uc.c | 142 - 2 files changed, 82 insertions(+), 79

[PATCH v4 16/24] ppc/ppc405: QOM'ify POB

POB is currently modeled as a simple DCR device. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 12 +++ hw/ppc/ppc405_uc.c | 51 ++ 2 files changed, 41 insertions(+), 22 deletions(-) diff --git

[PATCH v4 11/24] ppc/ppc405: QOM'ify OCM

The OCM controller is currently modeled as a simple DCR device with a couple of memory regions. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 16 ++ hw/ppc/ppc405_uc.c | 73 +++--- 2 files changed,

[PATCH v4 12/24] ppc/ppc405: QOM'ify GPIO

The GPIO controller is currently modeled as a simple SysBus device with a unique memory region. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 21 +++ hw/ppc/ppc405_uc.c | 51 +

[PATCH v4 15/24] ppc/ppc405: QOM'ify OPBA

The OPB arbitrer is currently modeled as a simple SysBus device with a unique memory region. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 12 hw/ppc/ppc405_uc.c | 48 +++--

[PATCH v4 08/24] ppc/ppc4xx: Introduce a DCR device model

The Device Control Registers (DCR) of on-SoC devices are accessed by software through the use of the mtdcr and mfdcr instructions. These are converted in transactions on a side band bus, the DCR bus, which connects the on-SoC devices to the CPU. Ideally, we should model these accesses with a DCR

[PATCH v4 10/24] ppc/ppc405: QOM'ify GPT

The GPT controller is currently modeled as a SysBus device with a unique memory region, a couple of IRQs and a timer. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h | 22 +++ hw/ppc/ppc405_uc.c | 91

[PATCH v4 07/24] ppc/ppc405: QOM'ify CPU

Drop the use of ppc4xx_init() and duplicate a bit of code related to clocks in the SoC realize routine. We will clean that up in the following patches. ppc_dcr_init() simply allocates default DCR handlers for the CPU. Maybe this could be done in model initializer of the CPU families needing it.

[PATCH v4 06/24] ppc/ppc405: Start QOMification of the SoC

This moves all the code previously done in the ppc405ep_init() routine under ppc405_soc_realize(). We can also adjust the number of banks now that we have control on ppc4xx_sdram_init(). Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 12 ++-- hw/ppc/ppc405_boards.c | 12 ++--

[PATCH v4 02/24] ppc/ppc405: Introduce a PPC405 generic machine

We will use this machine as a base to define the ref405ep and possibly the PPC405 hotfoot board as found in the Linux kernel. Reviewed-by: BALATON Zoltan Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 31 --- 1 file changed, 28 insertions(+), 3

[PATCH v4 20/24] ppc/ppc405: Use an embedded PPCUIC model in SoC state

Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h| 3 ++- hw/ppc/ppc405_uc.c | 26 +- 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 31c94e474209..8e67ad0b72c3 100644

[PATCH v4 03/24] ppc/ppc405: Move devices under the ref405ep machine

Reviewed-by: Daniel Henrique Barboza Reviewed-by: BALATON Zoltan Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 31 +++ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index

[PATCH v4 00/24] ppc: QOM'ify 405 board

Hello, Here is large series QOM'ifying the PPC405 board. It introduces a new generic machine and SoC models, converts the current device models to QOM and populates the SoC. The process is quite mechanical without too much issues to handle. The noisy part is the initial patch introducing the SoC

[PATCH v4 01/24] ppc/ppc405: Remove taihu machine

It has been deprecated since 7.0. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- docs/about/deprecated.rst | 9 -- docs/about/removed-features.rst | 6 + docs/system/ppc/embedded.rst| 1 - hw/ppc/ppc405_boards.c | 232

[PATCH v4 09/24] ppc/ppc405: QOM'ify CPC

The CPC controller is currently modeled as a DCR device. Now that all clock settings are handled at the CPC level, change the SoC "sys-clk" property to be an alias on the same property in the CPC model. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405.h

[PATCH v4 04/24] ppc/ppc405: Move SRAM under the ref405ep machine

It doesn't belong to the generic machine nor the SoC. Fix a typo in the name while we are at it. Signed-off-by: Cédric Le Goater --- hw/ppc/ppc405_boards.c | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index

[PATCH v4 05/24] ppc/ppc405: Introduce a PPC405 SoC

It is an initial model to start QOMification of the PPC405 board. QOM'ified devices will be reintroduced one by one. Start with the memory regions, which name prefix is changed to "ppc405". Also, initialize only one RAM bank. The second bank is a dummy one (zero size) which is here to match the

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