Hi Gerd,
On Tue, Sep 27, 2022 at 7:07 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Use g_mkdir() to create a directory on all platforms.
>
> Signed-off-by: Bin Meng
> Acked-by: Gerd Hoffmann
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Change to use g_mkdir()
>
> hw/usb/dev-mtp.c | 4
Hi Christian,
On Tue, Sep 27, 2022 at 7:07 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Use g_mkdir() to create a directory on all platforms.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Christian Schoenebeck
> ---
>
> (no changes since v2)
>
> Changes in v2:
> - Change to use g_mkdir()
>
>
Hi Kevin,
On Tue, Sep 27, 2022 at 7:07 PM Bin Meng wrote:
>
> From: Bin Meng
>
> There is a difference in the mkdir() call for win32 and non-win32
> platforms, and currently is handled in the codes with #ifdefs.
>
> glib provides a portable g_mkdir() API and we can use it to unify
> the codes
Hi Daniel,
On Tue, Sep 27, 2022 at 7:06 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Replace the existing logic to get the directory for temporary files
> with g_get_tmp_dir(), which works for win32 too.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Marc-André Lureau
> ---
>
> (no changes since v1)
Hi Alex, Richard,
On Tue, Sep 27, 2022 at 7:06 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Use g_get_tmp_dir() to get the directory to use for temporary files.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Marc-André Lureau
> Reviewed-by: Alex Bennée
> ---
>
> (no changes since v2)
>
> Changes in
Hi Alex,
On Tue, Sep 27, 2022 at 7:06 PM Bin Meng wrote:
>
> From: Bin Meng
>
> Use g_get_tmp_dir() to get the directory to use for temporary files.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Alex Bennée
> ---
>
> (no changes since v1)
>
Would you pick up this patch in your queue?
Regards,
On 9/21/22 06:31, Paolo Bonzini wrote:
On Tue, Sep 6, 2022 at 12:10 PM Richard Henderson
wrote:
static void gen_update_eip_cur(DisasContext *s)
{
gen_jmp_im(s, s->base.pc_next - s->cs_base);
+s->pc_save = s->base.pc_next;
s->pc_save is not valid after all gen_jmp_im() calls. Is
Hi, qemu
As I know, brom will pass 3 parameters to the next stage bootloader, ex:
openSBI.
a0 will pass hartid, a2 will pass fw_dynamic_info start address.
although a1 doesn't use directly in openSBI.
a1 read value is determined in compile time rather than read from the
original a1 that passes
On 9/21/22 06:09, Paolo Bonzini wrote:
On Tue, Sep 6, 2022 at 12:09 PM Richard Henderson
wrote:
-static inline void gen_jcc(DisasContext *s, int b,
- target_ulong val, target_ulong next_eip)
+static void gen_jcc(DisasContext *s, MemOp ot, int b, int diff)
{
-
On 9/21/22 06:06, Paolo Bonzini wrote:
On Tue, Sep 6, 2022 at 12:09 PM Richard Henderson
wrote:
Create a common helper for pc-relative branches.
The jmp jb insn was missing a mask for CODE32.
Signed-off-by: Richard Henderson
(Oops, my remark the previous patch should still have pointed to
This pull request doesn't build:
../meson.build:545:95: ERROR: Expecting endif got rparen.
gdbus_codegen_error = '@0@ uses gdbus-codegen, which does not support
control flow integrity')
https://gitlab.com/qemu-project/qemu/-/jobs/3112498668
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 41 +++---
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git a/target/arm/translate-a64.c
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 1 +
target/arm/translate.h | 19
target/arm/cpu.c | 23 +++---
target/arm/translate-a64.c | 37 ++-
target/arm/translate.c | 62 ++
5
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 37 +
1 file changed, 21 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Signed-off-by: Richard Henderson
---
target/arm/translate.h| 5 +++--
target/arm/translate-a64.c| 28 ++-
target/arm/translate-m-nocp.c | 6 ++---
target/arm/translate-mve.c| 2 +-
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/translate.c | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/target/arm/translate.c
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 40 --
target/arm/translate.c | 10 ++
2 files changed, 27 insertions(+), 23
In preparation for TARGET_TB_PCREL, reduce reliance on
absolute values by passing in pc difference.
Signed-off-by: Richard Henderson
---
target/arm/translate-a32.h | 2 +-
target/arm/translate.h | 6 ++--
target/arm/translate-a64.c | 32 +-
target/arm/translate-vfp.c | 2
A simple helper to retrieve the length of the current insn.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/translate.h | 5 +
target/arm/translate-vfp.c | 2 +-
target/arm/translate.c | 5 ++---
3 files changed, 8 insertions(+), 4 deletions(-)
This is the Arm specific changes required to reduce the
amount of translation for address space randomization.
Changes for v5:
* Minor updates for patch review, mostly using target_long
for pc displacements.
r~
Based-on: 20220930212622.108363-1-richard.hender...@linaro.org
("[PATCH v6
In preparation for TARGET_TB_PCREL, reduce reliance on absolute values.
Since we always pass dc->pc_curr, fold the arithmetic to zero displacement.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.c | 6 +++---
target/arm/translate.c | 10 +-
2 files changed, 8
> -Original Message-
> From: Richard Henderson
> Sent: Friday, September 30, 2022 4:26 PM
> To: qemu-devel@nongnu.org
> Cc: peter.mayd...@linux.org; alex.ben...@linux.org; Eduardo Habkost
> ; Marcel Apfelbaum
> ; Philippe Mathieu-Daudé
> ; Yanan Wang ; Michael
> Rolnik ; Edgar E.
> -Original Message-
> From: Matheus Tavares Bernardino
> Sent: Friday, September 30, 2022 3:08 PM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson
> Subject: [PATCH] Hexagon (gen_tcg_funcs.py): avoid duplicated tcg code on
> A_CVI_NEW
>
> Hexagon instructions with the A_CVI_NEW
Good grief: typo in the cc list, twice.
You'd think I'd know where I work by now...
r~
On 9/30/22 14:26, Richard Henderson wrote:
Changes for v6:
* CPUTLBEntryFull is now completely reviewed.
* Incorporated the CPUClass caching patches,
as I will add a new use of the cached value.
This function has two users, who use it incompatibly.
In tlb_flush_page_by_mmuidx_async_0, when flushing a
single page, we need to flush exactly two pages.
In tlb_flush_range_by_mmuidx_async_0, when flushing a
range of pages, we need to flush N+1 pages.
This avoids double-flushing of jmp cache
Let tb->page_addr[0] contain the offset within the page of the
start of the translation block. We need to recover this value
anyway at various points, and it is easier to discard the page
offset when it's not needed, which happens naturally via the
existing find_page shift.
Signed-off-by:
Use the pc coming from db->pc_first rather than the TB.
Use the cached host_addr rather than re-computing for the
first page. We still need a separate lookup for the second
page because it won't be computed for DisasContextBase until
the translator actually performs a read from the page.
The availability of tb->pc will shortly be conditional.
Introduce accessor functions to minimize ifdefs.
Pass around a known pc to places like tcg_gen_code,
where the caller must already have the value.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h| 6
Prepare for targets to be able to produce TBs that can
run in more than one virtual context.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 4 +++
accel/tcg/tb-jmp-cache.h | 5
include/exec/cpu-defs.h | 3 +++
include/exec/exec-all.h | 32 --
This bitmap is created and discarded immediately.
We gain nothing by its existence.
Reviewed-by: Alex Bennée
Signed-off-by: Richard Henderson
Message-Id: <20220822232338.1727934-2-richard.hender...@linaro.org>
---
accel/tcg/translate-all.c | 78 ++-
1 file
Populate this new method for all targets. Always match
the result that would be given by cpu_get_tb_cpu_state,
as we will want these values to correspond in the logs.
Signed-off-by: Richard Henderson
---
Cc: Eduardo Habkost (supporter:Machine core)
Cc: Marcel Apfelbaum (supporter:Machine
Wrap the bare TranslationBlock pointer into a structure.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/tb-hash.h | 1 +
accel/tcg/tb-jmp-cache.h | 24
include/exec/cpu-common.h | 1 +
include/hw/core/cpu.h | 15
Allow the target to cache items from the guest page tables.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/exec/cpu-defs.h | 9 +
1 file changed, 9 insertions(+)
diff --git
Now that we have collected all of the page data into
CPUTLBEntryFull, provide an interface to record that
all in one go, instead of using 4 arguments. This interface
allows CPUTLBEntryFull to be extended without having to
change the number of arguments.
Reviewed-by: Alex Bennée
Reviewed-by:
Bool is more appropriate type for the alloc parameter.
Reviewed-by: Alex Bennée
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/accel/tcg/translate-all.c
From: Alex Bennée
This is a heavily used function so lets avoid the cost of
CPU_GET_CLASS. On the romulus-bmc run it has a modest effect:
Before: 36.812 s ± 0.506 s
After: 35.912 s ± 0.168 s
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id:
This structure will shortly contain more than just
data for accessing MMIO. Rename the 'addr' member
to 'xlat_section' to more clearly indicate its purpose.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
Add an interface to return the CPUTLBEntryFull struct
that goes with the lookup. The result is not intended
to be valid across multiple lookups, so the user must
use the results immediately.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by:
From: Alex Bennée
The class cast checkers are quite expensive and always on (unlike the
dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To
avoid the overhead of repeatedly checking something which should never
change we cache the CPUClass reference for use in the hot code paths.
From: Alex Bennée
Before: 35.912 s ± 0.168 s
After: 35.565 s ± 0.087 s
Signed-off-by: Alex Bennée
Reviewed-by: Richard Henderson
Message-Id: <20220811151413.3350684-5-alex.ben...@linaro.org>
Signed-off-by: Cédric Le Goater
Message-Id: <20220923084803.498337-5-...@kaod.org>
Signed-off-by:
When PAGE_WRITE_INV is set when calling tlb_set_page,
we immediately set TLB_INVALID_MASK in order to force
tlb_fill to be called on the next lookup. Here in
probe_access_internal, we have just called tlb_fill
and eliminated true misses, thus the lookup must be valid.
This allows us to remove a
This field is only written, not read; remove it.
Reviewed-by: Alex Bennée
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
include/hw/core/cpu.h | 1 -
accel/tcg/cputlb.c| 7 +++
2 files changed, 3 insertions(+), 5 deletions(-)
diff
Changes for v6:
* CPUTLBEntryFull is now completely reviewed.
* Incorporated the CPUClass caching patches,
as I will add a new use of the cached value.
* Move CPUJumpCache out of include/hw/core.h. While looking at
Alex's review of the patch, I realized that adding the virtual
On 9/30/22 13:08, Matheus Tavares Bernardino wrote:
Hexagon instructions with the A_CVI_NEW attribute produce a vector value
that can be used in the same packet. The python function responsible for
generating code for such instructions has a typo ("if" instead of
"elif"), which makes
On 9/30/22 10:48, Peter Maydell wrote:
@@ -10289,20 +10289,113 @@ static int aa64_va_parameter_tcma(uint64_t tcr,
ARMMMUIdx mmu_idx)
}
}
+typedef enum GranuleSize {
+/* Same order as TG0 encoding */
+Gran4K,
+Gran64K,
+Gran16K,
+GranInvalid,
+} GranuleSize;
It
From: Bernhard Beschow
GCC issues a false positive warning, resulting in build failure with -Werror:
In file included from /usr/include/glib-2.0/glib.h:114,
from src/include/glib-compat.h:32,
from src/include/qemu/osdep.h:144,
from
-for-7.2-pull-request
for you to fetch changes up to a40ee29bbf3c169597d85f0871d189398b667d9f:
docs: Update TPM documentation for usage of a TPM 2 (2022-09-29 21:31:56
+0200)
Pull request trivial patches branch 20220930
On 9/30/22 10:48, Peter Maydell wrote:
FEAT_GTG is a change tho the ID register ID_AA64MMFR0_EL1 so that it
can report a different set of supported granule (page) sizes for
stage 1 and stage 2 translation tables. As of commit c20281b2a5048
we already report the granule sizes that way for '-cpu
Hexagon instructions with the A_CVI_NEW attribute produce a vector value
that can be used in the same packet. The python function responsible for
generating code for such instructions has a typo ("if" instead of
"elif"), which makes genptr_dst_write_ext() be executed twice, thus also
generating
On Donnerstag, 29. September 2022 18:32:37 CEST Marc-André Lureau wrote:
> From: Marc-André Lureau
>
> If slirp is not found during compile-time, and not manually disabled,
> print a friendly error message, as suggested in the "If your networking
> is failing after updating to the latest git
The imported files from the architecture library have added some
instruction attributes. Some of these will be used in a subsequent
patch for determing the size of a store.
Signed-off-by: Taylor Simpson
Acked-by: Richard Henderson
Message-Id: <20220920080746.26791-2-tsimp...@quicinc.com>
---
We have found cases where pkt_has_store_s[01] is set incorrectly.
This leads to generating an unnecessary store that is left over
from a previous packet.
Add an attribute to determine if an instruction is a scalar store
The attribute is attached to the fSTORE macro (hex_common.py)
Update the
The store width is needed for packet commit, so it is stored in
ctx->store_width. Currently, it is set when a store has a TCG
override instead of a QEMU helper. In the QEMU helper case, the
ctx->store_width is not set, we invoke a helper during packet commit
that uses the runtime store width.
The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:
Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into
staging (2022-09-28 17:04:11 -0400)
are available in the Git repository at:
https://github.com/quic/qemu tags/pull-hex-20220930
for you
Matheus Ferst writes:
> Export p9_interrupt_powersave and use it in p9_next_unmasked_interrupt.
>
> Signed-off-by: Matheus Ferst
> ---
> Temporarily putting the prototype in internal.h for lack of a better place,
> we will un-export p9_interrupt_powersave in future patches.
> ---
>
Matheus Ferst writes:
> No functional change intended.
>
> Signed-off-by: Matheus Ferst
> ---
> target/ppc/excp_helper.c | 9 +
> 1 file changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 603c956588..67e73f30ab 100644
>
FEAT_GTG is a change tho the ID register ID_AA64MMFR0_EL1 so that it
can report a different set of supported granule (page) sizes for
stage 1 and stage 2 translation tables. As of commit c20281b2a5048
we already report the granule sizes that way for '-cpu max', and now
we also correctly make
Arm CPUs support some subset of the granule (page) sizes 4K, 16K and
64K. The guest selects the one it wants using bits in the TCR_ELx
registers. If it tries to program these registers with a value that
is either reserved or which requests a size that the CPU does not
implement, the architecture
Arm CPUs support some subset of the granule (page) sizes 4K, 16K and
64K. The guest selects the one it wants using bits in the TCR_ELx
registers. If it tries to program these registers with a value that
is either reserved or which requests a size that the CPU does not
implement, the architecture
On 9/30/22 06:25, Peter Maydell wrote:
On Fri, 30 Sept 2022 at 14:23, Alex Bennée wrote:
Peter Maydell writes:
This is going to break previously working setups involving
the "filter logging to a particular address range" and also
anybody post-processing logfiles and expecting to see
the
On 30/09/2022 18.50, Christian Schoenebeck wrote:
On Mittwoch, 24. August 2022 17:11:16 CEST Thomas Huth wrote:
At the point in time we're going to release QEMU 7.2, all supported
host OS distributions will have a libslirp package available, so
there is no need anymore for us to ship the slirp
This reverts commit b6522938327141235b97ab38e40c6c4512587373.
Kevin Wolf NAKed this patch, because:
'file' is a required member (defined in BlockdevOptionsGenericFormat),
removing it makes the example invalid. 'data-file' is only an additional
optional member to be used for external
Markus Armbruster writes:
> Markus Armbruster writes:
>
>> Gentle reminder, Victor :)
>>
>> Markus Armbruster writes:
>>
>>> Markus Armbruster writes:
>>>
Kevin Wolf writes:
> Am 07.09.2022 um 17:03 hat Markus Armbruster geschrieben:
>> The following changes since commit
From: Lev Kujawski
Prior to this patch, cmd_exec_dev_diagnostic relied upon
ide_set_signature to clear the device register. While the
preservation of the drive bit by ide_set_signature is necessary for
the DEVICE RESET, IDENTIFY DEVICE, and READ SECTOR commands,
ATA/ATAPI-6 specifies that "DEV
From: Lev Kujawski
CHS-based disk utilities and operating systems may adjust the logical
geometry of a hard drive to cope with the expectations or limitations
of software using the ATA INITIALIZE_DEVICE_PARAMETERS command.
Prior to this patch, INITIALIZE_DEVICE_PARAMETERS was a nop that
always
From: Hanna Reitz
qcow2_do_open() is used by qcow2_co_invalidate_cache(), i.e. may be run
on an image that has been opened before. When reading the backing file
string from the image header, compare it against the existing
bs->backing_file, and update bs->auto_backing_file only if they differ.
From: Lev Kujawski
Eliminate the remaining TODOs in hw/ide/piix.c by:
* Using pci_set_{size} functions to write the PIIX PCI configuration
space instead of manipulating it directly as an array; and
* Documenting the default register values by reference to the
controlling specification.
From: Lev Kujawski
Change 'tmp_path' into an array of two members to accommodate another
disk image of size TEST_IMAGE_SIZE. This facilitates testing ATA
protocol aspects peculiar to secondary devices on the same controller.
Signed-off-by: Lev Kujawski
Message-Id:
From: Keith Busch
An iov length needs to be aligned to the logical block size, which may
be larger than the memory alignment.
Tested-by: Jens Axboe
Signed-off-by: Keith Busch
Message-Id: <20220929200523.3218710-3-kbu...@meta.com>
Reviewed-by: Kevin Wolf
Signed-off-by: Kevin Wolf
---
The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:
Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into
staging (2022-09-28 17:04:11 -0400)
are available in the Git repository at:
git://repo.or.cz/qemu/kevin.git tags/for-upstream
for you to
From: Hanna Reitz
Add a new test to see what happens when you migrate a VM with a backing
chain that has json:{} backing file strings, which, when opened, will be
resolved to plain filenames.
Signed-off-by: Hanna Reitz
Message-Id: <2022080316.20723-4-hre...@redhat.com>
Reviewed-by: Kevin
From: Keith Busch
There is only user of bdrv_qiov_is_aligned(), so move the alignment
function to there and make it static.
Signed-off-by: Keith Busch
Message-Id: <20220929200523.3218710-2-kbu...@meta.com>
Reviewed-by: Kevin Wolf
Signed-off-by: Kevin Wolf
---
include/block/block-io.h | 1 -
From: Lev Kujawski
Verify correction of EXECUTE DEVICE DIAGNOSTIC introduced in commit
72423831c3 (hw/ide/core: Clear LBA and drive bits for EXECUTE DEVICE
DIAGNOSTIC, 2022-05-28).
Signed-off-by: Lev Kujawski
Message-Id: <20220707031140.158958-4-lku...@member.fsf.org>
Signed-off-by: Kevin Wolf
From: lu zhipeng
Free feature_table if it is failed in bdrv_pread.
Signed-off-by: lu zhipeng
Message-Id: <20220921144515.1166-1-luzhip...@cestc.cn>
Reviewed-by: Kevin Wolf
Signed-off-by: Kevin Wolf
---
block/qcow2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/qcow2.c
From: "Denis V. Lunev"
Return codes of the following functions are never used in the code:
* bdrv_wait_serialising_requests_locked
* bdrv_wait_serialising_requests
* bdrv_make_request_serialising
Signed-off-by: Denis V. Lunev
CC: Kevin Wolf
CC: Hanna Reitz
CC: Stefan Hajnoczi
CC: Fam Zheng
From: Stefan Hajnoczi
The gluster protocol driver used to parse URIs (filenames) but was
extended with a richer JSON syntax in commit 6c7189bb29de
("block/gluster: add support for multiple gluster servers"). The gluster
drivers that have JSON parsing set .bdrv_needs_filename to false.
The
From: Hanna Reitz
Just like qcow2, qed invokes its open function in its
.bdrv_co_invalidate_cache() implementation. Therefore, just like done
for qcow2 in HEAD^, update auto_backing_file only if the backing file
string in the image header differs from the one we have read before.
From: Markus Armbruster
'?' for help is deprecated since commit c8057f951d "Support 'help' as
a synonym for '?' in command line options", v1.2.0. We neglected to
update output of qemu-img --help and the manual. Do that now.
Signed-off-by: Markus Armbruster
Message-Id:
From: "Denis V. Lunev"
Commit 5f76a7aac156ca75680dad5df4a385fd0b58f6b1 is looking harmless from
the first glance, but it has changed things a lot. 'libvirt' uses it to
detect that it should follow new initialization way and this changes
things considerably. With this procedure followed,
From: "Denis V. Lunev"
I believe that if the helper exists, it must be used always for reading
of the value. It breaks expectations in the other case.
Signed-off-by: Denis V. Lunev
CC: Kevin Wolf
CC: Hanna Reitz
CC: Stefan Hajnoczi
CC: Fam Zheng
CC: Ronnie Sahlberg
CC: Paolo Bonzini
CC:
From: Philippe Mathieu-Daudé
Commit d1258dd0c8 ("qcow2: autoloading dirty bitmaps") added the
set_readonly_helper() GFunc handler, correctly casting the gpointer
user_data in both the g_slist_foreach() caller and the handler.
Few commits later (commit 1b6b0562db), the handler is reused in
From: "Denis V. Lunev"
We would have one more place for block_acct_setup() calling, which should
not corrupt original value.
Signed-off-by: Denis V. Lunev
Reviewed-by: Vladimir Sementsov-Ogievskiy
CC: Peter Krempa
CC: Markus Armbruster
CC: John Snow
CC: Kevin Wolf
CC: Hanna Reitz
On Mittwoch, 24. August 2022 17:11:16 CEST Thomas Huth wrote:
> At the point in time we're going to release QEMU 7.2, all supported
> host OS distributions will have a libslirp package available, so
> there is no need anymore for us to ship the slirp submodule. Thus
> let's clean up the related
On Fri, Sep 30, 2022 at 4:42 PM Venu Busireddy
wrote:
> > > Immediately after a hotunplug event, qemu (without any action from
> > > the guest) processes a REPORT_LUNS command on the lun 0 of the device
> > > (haven't figured out what causes this).
> >
> > There is only one call to
Provide the Micron Xccela flash mt35xu01g with Octal command support.
Signed-off-by: Francisco Iglesias
---
hw/block/m25p80.c | 57 +++
1 file changed, 57 insertions(+)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index a8d2519141..79e26424ec
Hi,
On Tue, Sep 27, 2022 at 11:47 PM Sean Christopherson wrote:
>
> On Mon, Sep 26, 2022, Fuad Tabba wrote:
> > Hi,
> >
> > On Mon, Sep 26, 2022 at 3:28 PM Chao Peng
> > wrote:
> > >
> > > On Fri, Sep 23, 2022 at 04:19:46PM +0100, Fuad Tabba wrote:
> > > > > Then on the KVM side, its
On Fri, Sep 30, 2022 at 05:14:00PM +0100, Fuad Tabba wrote:
> Hi,
>
> <...>
>
> > diff --git a/mm/memfd_inaccessible.c b/mm/memfd_inaccessible.c
> > new file mode 100644
> > index ..2d33cbdd9282
> > --- /dev/null
> > +++ b/mm/memfd_inaccessible.c
> > @@ -0,0 +1,219 @@
> > +//
Hi,
<...>
> diff --git a/mm/memfd_inaccessible.c b/mm/memfd_inaccessible.c
> new file mode 100644
> index ..2d33cbdd9282
> --- /dev/null
> +++ b/mm/memfd_inaccessible.c
> @@ -0,0 +1,219 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include "linux/sbitmap.h"
> +#include
> +#include
Matheus Ferst writes:
> Split ppc_hw_interrupt into an interrupt masking method,
> ppc_next_unmasked_interrupt, and an interrupt processing method,
> ppc_deliver_interrupt.
>
> @@ -1822,20 +1782,106 @@ static void ppc_hw_interrupt(CPUPPCState *env)
> */
> if
From: "Maciej S. Szmigiero"
Resetting a guest that has Hyper-V VMBus support enabled triggers a QEMU
assertion failure:
hw/hyperv/hyperv.c:131: synic_reset: Assertion
`QLIST_EMPTY(>sint_routes)' failed.
This happens both on normal guest reboot or when using "system_reset" HMP
command.
The
Will merge early next week.
On Thu, Sep 29, 2022 at 05:29:58PM +0100, Peter Maydell wrote:
> Ping! This series has been reviewed.
>
> I can take it via target-arm.next if you'd prefer.
>
> thanks
> -- PMM
>
> On Thu, 18 Aug 2022 at 14:54, Peter Maydell wrote:
> >
> > This patchset fixes a
Am 30.09.2022 um 14:17 hat Emanuele Giuseppe Esposito geschrieben:
> Am 29/09/2022 um 17:30 schrieb Kevin Wolf:
> > Am 09.06.2022 um 15:44 hat Emanuele Giuseppe Esposito geschrieben:
> >> Remove usage of aio_context_acquire by always submitting work items
> >> to the current thread's ThreadPool.
>
Am 30.09.2022 um 12:00 hat Emanuele Giuseppe Esposito geschrieben:
>
>
> Am 29/09/2022 um 16:52 schrieb Kevin Wolf:
> > Am 09.06.2022 um 15:44 hat Emanuele Giuseppe Esposito geschrieben:
> >> From: Paolo Bonzini
> >>
> >> Remove usage of aio_context_acquire by always submitting asynchronous
>
Markus Armbruster writes:
> Gentle reminder, Victor :)
>
> Markus Armbruster writes:
>
>> Markus Armbruster writes:
>>
>>> Kevin Wolf writes:
>>>
Am 07.09.2022 um 17:03 hat Markus Armbruster geschrieben:
> The following changes since commit
>
This patch series fixes up and tries to remove some confusion around the
SEV reduced-phys-bits parameter.
Based on the "AMD64 Architecture Programmer's Manual Volume 2: System
Programming", section "15.34.6 Page Table Support" [1], a guest should
only ever see a maximum of 1 bit of physical
The value of the reduced-phys-bits parameter is propogated to the CPUID
information exposed to the guest. Update the current validation check to
account for the size of the CPUID field (6-bits), ensuring the value is
in the range of 1 to 63.
Maintain backward compatibility, to an extent, by
Am 07.07.2022 um 05:11 hat Lev Kujawski geschrieben:
> Eliminate the remaining TODOs in hw/ide/piix.c by:
> * Using pci_set_{size} functions to write the PIIX PCI configuration
> space instead of manipulating it directly as an array; and
> * Documenting the default register values by reference
Update the setting of CPUID 0x801F EBX to clearly document the ranges
associated with fields being set.
Fixes: 6cb8f2a663 ("cpu/i386: populate CPUID 0x8000_001F when SEV is active")
Signed-off-by: Tom Lendacky
---
target/i386/cpu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
A guest only ever experiences, at most, 1 bit of reduced physical
addressing. Update the documentation to reflect this as well as change
the example value on the reduced-phys-bits option.
Fixes: a9b4942f48 ("target/i386: add Secure Encrypted Virtualization (SEV)
object")
Signed-off-by: Tom
A guest only ever experiences, at most, 1 bit of reduced physical
addressing. Change the query-sev-capabilities json comment to use 1.
Fixes: 31dd67f684 ("sev/i386: qmp: add query-sev-capabilities command")
Signed-off-by: Tom Lendacky
---
qapi/misc-target.json | 2 +-
1 file changed, 1
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