On Wed, Feb 22, 2023 at 5:01 AM Jason Wang wrote:
>
>
> 在 2023/2/8 17:42, Eugenio Pérez 写道:
> > Devices with CVQ needs to migrate state beyond vq state. Leaving this
> > to future series.
>
>
> I may miss something but what is missed to support CVQ/MQ?
>
To restore all the device state set by
On Wed, Feb 22, 2023 at 4:56 AM Jason Wang wrote:
>
>
> 在 2023/2/8 17:42, Eugenio Pérez 写道:
> > This allows net to restart the device backend to configure SVQ on it.
> >
> > Ideally, these changes should not be net specific. However, the vdpa net
> > backend is the one with enough knowledge to
On 2/21/23 12:52, Alex Bennée wrote:
-# and BSD?
-specific_ss.add(when: 'CONFIG_LINUX_USER', if_true: files('user-target.c'))
+# The user-target is specialised by the guest
+specific_ss.add(when: 'CONFIG_USER_ONLY', if_true: files('user-target.c'))
Looks like should be folded to patch 10.
r~
On 2/21/23 12:52, Alex Bennée wrote:
+# and BSD?
+specific_ss.add(when: 'CONFIG_LINUX_USER', if_true: files('user-target.c'))
Certainly and bsd. It had been compiled before you moved it.
r~
John Snow writes:
> On Tue, Feb 21, 2023, 1:50 AM Markus Armbruster wrote:
>
>> John Snow writes:
>>
>> > Once upon a time, "sphinx-build" on certain RPM platforms invoked
>> > specifically a Python 2.x version, while "sphinx-build-3" was a distro
>> > shim for the Python 3.x version.
>> >
>>
Hi Xiaoyao,
Thanks, I've spent some time thinking about it here.
On Mon, Feb 20, 2023 at 02:59:20PM +0800, Xiaoyao Li wrote:
> Date: Mon, 20 Feb 2023 14:59:20 +0800
> From: Xiaoyao Li
> Subject: Re: [PATCH RESEND 04/18] i386/cpu: Fix number of addressable IDs
> in CPUID.04H
>
> On 2/13/2023
On 2/21/23 18:06, Thomas Huth wrote:
int postcopy_wake_shared(struct PostCopyFD *pcfd,
uint64_t client_addr,
RAMBlock *rb)
{
- assert(0);
- return -1;
+ g_assert_not_reached();
}
#endif
If we ever reconsider to allow
Hi, Peter
On 2023/2/22 上午4:36, Peter Xu wrote:
On 2023/2/21 上午11:38, Chuang Xu wrote:
I think we need a memory_region_transaction_commit_force() to force
commit
some transactions when load vmstate. This function is designed like this:
/*
* memory_region_transaction_commit_force() is
On 2/22/23 10:58 AM, Peter Xu wrote:
On Wed, Feb 22, 2023 at 10:44:07AM +1100, Gavin Shan wrote:
Peter, could you please give some hints for me to understand the atomic
and non-atomic update here? Ok, I will drop this part of changes in next
revision with the assumption that we have atomic
On 14/1/23 08:54, Sean Christopherson wrote:
On Fri, Dec 02, 2022, Chao Peng wrote:
The system call is currently wired up for x86 arch.
Building on other architectures (except for arm64 for some reason) yields:
CALL/.../scripts/checksyscalls.sh
:1565:2: warning: #warning syscall
On 2/22/23 3:27 AM, Peter Maydell wrote:
On Mon, 13 Feb 2023 at 00:40, Gavin Shan wrote:
When KVM device "kvm-arm-gicv3" or "arm-its-kvm" is used, we have to
enable the backup bitmap for the dirty ring. Otherwise, the migration
will fail because those two devices are using the backup bitmap
Currently we are wrongly accessing plugin_tb->mem_helper at
translation time from plugin_gen_disable_mem_helpers, which is
called before generating a TB exit, e.g. with exit_tb.
Recall that it is only during TB finalisation, i.e. when we go over
the TB post-translation to inject or remove plugin
在 2023/2/8 17:42, Eugenio Pérez 写道:
vhost-vdpa devices can return this features now that blockers have been
set in case some features are not met.
Expose VHOST_F_LOG_ALL only in that case.
Signed-off-by: Eugenio Pérez
---
Acked-by: Jason Wang
Thanks
hw/virtio/vhost-vdpa.c | 3 +--
On 22/02/2023 00.25, Philippe Mathieu-Daudé wrote:
In order to avoid warnings such commit c0a6665c3c ("target/i386:
Remove compilation errors when -Werror=maybe-uninitialized"),
replace all assert(0) and g_assert(0) by g_assert_not_reached().
Remove any code following g_assert_not_reached().
在 2023/2/8 17:42, Eugenio Pérez 写道:
Next patches enable devices to be migrated even if vdpa netdev has not
been started with x-svq. However, not all devices are migratable, so we
need to block migration if we detect that.
Block vhost-vdpa device migration if it does not offer _F_SUSPEND and
在 2023/2/8 17:42, Eugenio Pérez 写道:
Devices with CVQ needs to migrate state beyond vq state. Leaving this
to future series.
I may miss something but what is missed to support CVQ/MQ?
Thanks
Signed-off-by: Eugenio Pérez
---
net/vhost-vdpa.c | 6 ++
1 file changed, 6
在 2023/2/8 17:42, Eugenio Pérez 写道:
This allows net to restart the device backend to configure SVQ on it.
Ideally, these changes should not be net specific. However, the vdpa net
backend is the one with enough knowledge to configure everything because
of some reasons:
* Queues might need to
On 22/02/2023 00.25, Philippe Mathieu-Daudé wrote:
Since commit 262a69f428 ("osdep.h: Prohibit disabling assert()
in supported builds") we can not build QEMU with NDEBUG (or
G_DISABLE_ASSERT) defined, thus 'assert(0)' always aborts QEMU.
However some static analyzers / compilers doesn't notice
On Tue, Feb 21, 2023 at 3:08 PM Eugenio Perez Martin
wrote:
>
> On Tue, Feb 21, 2023 at 6:36 AM Jason Wang wrote:
> >
> >
> > 在 2023/2/8 17:42, Eugenio Pérez 写道:
> > > The function vhost.c:vhost_dev_stop calls vhost operation
> > > vhost_dev_start(false). In the case of vdpa it totally reset and
On Mon, Feb 20, 2023 at 3:04 PM Akihiko Odaki wrote:
>
> On 2023/02/20 16:01, Jason Wang wrote:
> >
> > 在 2023/2/6 20:30, Akihiko Odaki 写道:
> >> Hi Jason,
> >>
> >> Let me remind that every patches in this series now has Reviewed-by:
> >> or Acked-by: tag though I forgot to include tags the prior
On 2/14/2023 12:20 AM, Bernhard Beschow wrote:
Going through pc_memory_init() seems quite complicated for a simple
assignment.
...
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 5bde4533cc..00ba725656 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -143,6 +143,7 @@
Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF
to be set, and invalidate TLBs when NSE changes.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 5 +++--
target/arm/helper.c | 10 --
2 files changed, 11 insertions(+), 4
We will need 2 bits to represent ARMSecurityState.
Do not attempt to replace or widen secure, even though it
logically overlaps the new field -- there are uses within
e.g. hw/block/pflash_cfi01.c, which don't know anything
specific about ARM.
Reviewed-by: Peter Maydell
Signed-off-by: Richard
Test in_space instead of in_secure so that we don't switch
out of Root space. Handle the output space change immediately,
rather than try and combine the NSTable and NS bits later.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 27 ++-
1 file changed, 14
Add a cpu property to set GPCCR_EL3.L0GPTSZ, for testing
various possible configurations.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index
With RME, SEL2 must also be present to support secure state.
The NS bit is RES1 if SEL2 is not present.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3650234c73..ae8b3f6a48 100644
Integrate neighboring code from get_phys_addr_lpae which computed
starting level, as it is easier to validate when doing both at the
same time. Mirror the checks at the start of AArch{64,32}.S2Walk,
especially S2InvalidSL and S2InconsistentSL.
This reverts 49ba115bb74, which was incorrect --
M-profile doesn't have HCR_EL2. While we could test features
before each call, zero is a generally safe return value to
disable the code in the caller. This test is required to
avoid an assert in arm_is_secure_below_el3.
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 3 +++
1 file
Do not provide a fast-path for physical addresses,
as those will need to be validated for GPC.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 35 ++-
1 file changed, 14 insertions(+), 21 deletions(-)
diff --git
Add the missing field for ID_AA64PFR0, and the predicate.
Disable it if EL3 is forced off by the board or command-line.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 ++
target/arm/cpu.c | 4
2 files changed, 10 insertions(+)
diff --git
Add input and output space members to S1Translate.
Set and adjust them in S1_ptw_translate, and the
various points at which we drop secure state.
Initialize the space in get_phys_addr; for now
leave get_phys_addr_with_secure considering only
secure vs non-secure spaces.
Reviewed-by: Peter Maydell
With FEAT_RME, there are four physical address spaces.
For now, just define the symbols, and mention them in
the same spots as the other Phys indexes in ptw.c.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 2 +-
target/arm/cpu.h | 23
This was added in 7e98e21c098 as part of a reorg in which
one of the argument had been legally NULL, and this caught
actual instances. Now that the reorg is complete, this
serves little purpose.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 6 ++
1 file changed, 2 insertions(+),
In several places we use arm_is_secure_below_el3 and
arm_is_el3_or_mon separately from arm_is_secure.
These functions make no sense for m-profile, and
would indicate prior incorrect feature testing.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 -
1 file changed, 4
This is arbitrary, but used by the Huawei TF-A test code.
Signed-off-by: Richard Henderson
---
include/hw/arm/virt.h | 2 ++
hw/arm/virt.c | 43 +++
2 files changed, 45 insertions(+)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
While Root and Realm may read and write data from other spaces,
neither may execute from other pa spaces.
This happens for Stage1 EL3, EL2, EL2&0, but stage2 EL1&0.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 52 ++--
1 file changed, 46
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 12b1082537..7a2f804aeb 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2426,6 +2426,9 @@ static inline bool
Handle GPC Fault types in arm_deliver_fault, reporting as
either a GPC exception at EL3, or falling through to insn
or data aborts at various exception levels.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 +
target/arm/internals.h | 27
Introduce both the enumeration and functions to retrieve
the current state, and state outside of EL3.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 89 ++---
target/arm/helper.c | 60 ++
With Realm security state, bit 55 of a block or page descriptor during
the stage2 walk becomes the NS bit; during the stage1 walk the bit 5
NS bit is RES0. With Root security state, bit 11 of the block or page
descriptor during the stage1 walk becomes the NSE bit.
Rather than collecting an NS
The function takes the fields as filled in by
the Arm ARM pseudocode for TakeGPCException.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/syndrome.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index
This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS,
RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 19 +++
target/arm/helper.c | 83
This fixes a bug in which we failed to initialize
the result attributes properly after the memset.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index
Instead of passing this to get_phys_addr_lpae, stash it
in the S1Translate structure.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/arm/ptw.c
Place the check at the end of get_phys_addr_with_struct,
so that we check all physical results.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 249 +++
1 file changed, 232 insertions(+), 17 deletions(-)
diff --git
This is based on mainline, without any extra ARMv9-A dependencies
which are still under development. This is good enough to pass
all of the tests within
https://github.com/Huawei/Huawei_CCA_QEMU
Changes for v3:
* Incorporate fix for m-profile arm_cpu_get_phys_page_attrs_debug,
since
It will be helpful to have ARMMMUIdx_Phys_* to be in the same
relative order as ARMSecuritySpace enumerators. This requires
the adjustment to the nstable check. While there, check for being
in secure state rather than rely on clearing the low bit making
no change to non-secure state.
Reviewed-by:
From: Ilya Leoshkevich
Currently dying to one of the core_dump_signal()s deadlocks, because
dump_core_and_abort() calls start_exclusive() two times: first via
stop_all_tasks(), and then via preexit_cleanup() ->
qemu_plugin_user_exit().
There are a number of ways to solve this: resume after
If an instruction straddles a page boundary, and the first page
was ram, but the second page was MMIO, we would abort. Handle
this as if both pages are MMIO, by setting the ram_addr_t for
the first page to -1.
Reported-by: Sid Manning
Reported-by: Jørgen Hansen
Reviewed-by: Philippe
From: Ilya Leoshkevich
Follow what kernel's full_exception() is doing.
Reviewed-by: Richard Henderson
Signed-off-by: Ilya Leoshkevich
Message-Id: <20230214140829.45392-4-...@linux.ibm.com>
Signed-off-by: Richard Henderson
---
linux-user/microblaze/cpu_loop.c | 10 --
1 file changed,
The linux kernel's trap tables vector all unassigned trap
numbers to BAD_TRAP, which then raises SIGILL.
Tested-by: Ilya Leoshkevich
Reported-by: Ilya Leoshkevich
Signed-off-by: Richard Henderson
---
linux-user/sparc/cpu_loop.c | 8
1 file changed, 8 insertions(+)
diff --git
From: Pierrick Bouvier
ctr_el0 access is privileged on this platform and fails as an illegal
instruction.
Windows does not offer a way to flush data cache from userspace, and
only FlushInstructionCache is available in Windows API.
The generic implementation of flush_idcache_range uses,
Mirroring the upstream gdb xml files, the two stack boundary
registers are separated out.
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/cpu.h | 2 +
target/microblaze/cpu.c | 7 ++-
target/microblaze/gdbstub.c
On 2023/2/22 02:45, Daniel Henrique Barboza wrote:
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added code to set the tail elements to 1 in
the end of vext_ldst_stride(), vext_ldst_us(), vext_ldst_index() and
vext_ldff(). Aside from a
From: Pierrick Bouvier
Windows implementation of setjmp/longjmp is done in
C:/WINDOWS/system32/ucrtbase.dll. Alas, on arm64, it seems to *always*
perform stack unwinding, which crashes from generated code.
By using alternative implementation built in mingw, we avoid doing stack
unwinding and
From: Ilya Leoshkevich
fork()ed processes currently start with
current_cpu->in_exclusive_context set, which is, strictly speaking, not
correct, but does not cause problems (even assertion failures).
With one of the next patches, the code begins to rely on this value, so
fix it by always calling
The following changes since commit 79b677d658d3d35e1e776826ac4abb28cdce69b8:
Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
(2023-02-21 11:28:31 +)
are available in the Git repository at:
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20230221
for you
Jonathan Cameron wrote:
> This enum typedef used to be local to one file, so having a generic
> name wasn't a big problem even if it wasn't compliant with QEMU naming
> conventions. Now it is in cxl_device.h to support use outside of
> cxl-mailbox-utils.c rename it.
Same comment as 1/6 but
Jonathan Cameron wrote:
> Needs tidy up and rename to something more generic now it is
> in a header.
I'm not opposed to this change and patch 2 but I don't see where
CXLRetCode is being used outside of cxl-mailbox-utils.c in this series.
Despite that reservation I think this is a good
Jonathan Cameron wrote:
> Current implementation is very simple so many of the corner
> cases do not exist (e.g. fragmenting larger poison list entries)
>
> Signed-off-by: Jonathan Cameron
> ---
> hw/cxl/cxl-mailbox-utils.c | 77 +
> hw/mem/cxl_type3.c
Jonathan Cameron wrote:
> Very simple implementation to allow testing of corresponding
> kernel code. Note that for now we track each 64 byte section
> independently. Whilst a valid implementation choice, it may
> make sense to fuse entries so as to prove out more complex
> corners of the kernel
On 2/21/23 12:52, Alex Bennée wrote:
While we will continue to include this via cpu-defs it is useful to be
able to define this separately for 32 and 64 bit versions of an
otherwise target independent compilation unit.
Signed-off-by: Alex Bennée
---
include/exec/cpu-defs.h| 19
Jonathan Cameron wrote:
> Inject poison using qmp command cxl-inject-poison to add an entry to the
> poison list.
>
> For now, the poison is not returned CXL.mem reads, but only via the
> mailbox command Get Poison List.
>
> See CXL rev 3.0, sec 8.2.9.8.4.1 Get Poison list (Opcode 4300h)
>
>
On 2/21/23 12:52, Alex Bennée wrote:
Currently when we encounter a gdb that is old or not built with
multiarch in mind we fail rather messily. Try and improve the
situation by probing ahead of time and setting
HOST_GDB_SUPPORTS_ARCH=y in the relevant tcg configs. We can then skip
and give a more
On 2/21/23 12:52, Alex Bennée wrote:
This is a hangover from the original code. addr is misleading as it is
only really a register id. While len will never exceed
MAX_PACKET_LENGTH I've used size_t as that is what strlen returns.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard
On 2/21/23 12:52, Alex Bennée wrote:
We don't really need a table for mapping two symbols.
Signed-off-by: Alex Bennée
Suggested-by: Richard Henderson
---
gdbstub/softmmu.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
Reviewed-by: Richard Henderson
r~
On 2/21/23 12:52, Alex Bennée wrote:
This is mostly code motion but a number of things needed to be done
for this minimal patch set:
- move shared structures to internals.h
- splitting some functions into user and softmmu versions
- fixing a few casting issues to keep softmmu common
On 2/21/23 13:25, Philippe Mathieu-Daudé wrote:
Since commit 262a69f428 ("osdep.h: Prohibit disabling
assert() in supported builds") 'NDEBUG' can not be defined.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/scsi/mptsas.c | 2 --
hw/virtio/virtio.c | 2 --
2 files changed, 4 deletions(-)
On 2/21/23 13:25, Philippe Mathieu-Daudé wrote:
Since commit 262a69f428 ("osdep.h: Prohibit disabling
assert() in supported builds") 'NDEBUG' can not be defined,
so '#ifndef NDEBUG' is dead code. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
block/vvfat.c | 3 ---
1 file changed, 3
On 2/21/23 13:25, Philippe Mathieu-Daudé wrote:
Since commit 262a69f428 ("osdep.h: Prohibit disabling assert()
in supported builds") we can not build QEMU with NDEBUG (or
G_DISABLE_ASSERT) defined, thus 'assert(0)' always aborts QEMU.
However some static analyzers / compilers doesn't notice
On 2/21/23 13:25, Philippe Mathieu-Daudé wrote:
In order to avoid warnings such commit c0a6665c3c ("target/i386:
Remove compilation errors when -Werror=maybe-uninitialized"),
replace all assert(0) and g_assert(0) by g_assert_not_reached().
Remove any code following g_assert_not_reached().
See
Hi, Gavin,
On Wed, Feb 22, 2023 at 10:44:07AM +1100, Gavin Shan wrote:
> Peter, could you please give some hints for me to understand the atomic
> and non-atomic update here? Ok, I will drop this part of changes in next
> revision with the assumption that we have atomic update supported for
>
On 2/21/23 05:30, Pierrick Bouvier wrote:
Windows implementation of setjmp/longjmp is done in
C:/WINDOWS/system32/ucrtbase.dll. Alas, on arm64, it seems to *always*
perform stack unwinding, which crashes from generated code.
By using alternative implementation built in mingw, we avoid doing
On 2/21/23 05:30, Pierrick Bouvier wrote:
ctr_el0 access is privileged on this platform and fails as an illegal
instruction.
Windows does not offer a way to flush data cache from userspace, and
only FlushInstructionCache is available in Windows API.
The generic implementation of
On 2/22/23 4:46 AM, Peter Xu wrote:
On Mon, Feb 13, 2023 at 08:39:22AM +0800, Gavin Shan wrote:
In the last stage of live migration or memory slot removal, the
backup bitmap needs to be synchronized when it has been enabled.
Signed-off-by: Gavin Shan
---
accel/kvm/kvm-all.c | 11
On 2/21/23 12:30, Philippe Mathieu-Daudé wrote:
On 21/2/23 16:30, Pierrick Bouvier wrote:
When compiling for windows-arm64 using clang-15, it reports a sometimes
uninitialized variable. This seems to be a false positive, as a default
case guards switch expressions, preventing to return an
On 2/22/23 10:31 AM, Philippe Mathieu-Daudé wrote:
On 22/2/23 00:12, Gavin Shan wrote:
On 2/21/23 9:21 PM, Philippe Mathieu-Daudé wrote:
On 21/2/23 10:21, Gavin Shan wrote:
On 2/21/23 8:15 PM, Philippe Mathieu-Daudé wrote:
On 21/2/23 09:53, Gavin Shan wrote:
Linux kernel guest reports
On 22/2/23 00:12, Gavin Shan wrote:
On 2/21/23 9:21 PM, Philippe Mathieu-Daudé wrote:
On 21/2/23 10:21, Gavin Shan wrote:
On 2/21/23 8:15 PM, Philippe Mathieu-Daudé wrote:
On 21/2/23 09:53, Gavin Shan wrote:
Linux kernel guest reports warning when two CPUs in one socket have
been associated
Since commit 262a69f428 ("osdep.h: Prohibit disabling assert()
in supported builds") we can not build QEMU with NDEBUG (or
G_DISABLE_ASSERT) defined, thus 'assert(0)' always aborts QEMU.
However some static analyzers / compilers doesn't notice NDEBUG
can't be defined and emit warnings if code is
From: Pierrick Bouvier
When compiling for windows-arm64 using clang-15, it reports a sometimes
uninitialized variable. This seems to be a false positive, as a default
case guards switch expressions, preventing to return an uninitialized
value, but clang seems unhappy with assert(0) definition.
Save contributors to post a patch each time clang
produce a -Werror=maybe-uninitialized warning on
assert(0). Replace by g_assert_not_reached()() and
prohibit '[g_]assert(0)'. Remove NDEBUG.
Philippe Mathieu-Daudé (4):
scripts/checkpatch.pl: Do not allow assert(0)
bulk: Replace [g_]assert(0)
Since commit 262a69f428 ("osdep.h: Prohibit disabling
assert() in supported builds") 'NDEBUG' can not be defined.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/scsi/mptsas.c | 2 --
hw/virtio/virtio.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c
Since commit 262a69f428 ("osdep.h: Prohibit disabling
assert() in supported builds") 'NDEBUG' can not be defined,
so '#ifndef NDEBUG' is dead code. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
block/vvfat.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/block/vvfat.c
In order to avoid warnings such commit c0a6665c3c ("target/i386:
Remove compilation errors when -Werror=maybe-uninitialized"),
replace all assert(0) and g_assert(0) by g_assert_not_reached().
Remove any code following g_assert_not_reached().
See previous commit for rationale.
Signed-off-by:
On 2/22/23 4:36 AM, Peter Xu wrote:
On Mon, Feb 13, 2023 at 08:39:21AM +0800, Gavin Shan wrote:
The global dirty log synchronization is used when KVM and dirty ring
are enabled. There is a particularity for ARM64 where the backup
bitmap is used to track dirty pages in non-running-vcpu
On 2/22/23 3:30 AM, Peter Maydell wrote:
On Mon, 13 Feb 2023 at 00:39, Gavin Shan wrote:
Signed-off-by: Gavin Shan
---
linux-headers/asm-arm64/kvm.h | 1 +
linux-headers/linux/kvm.h | 2 ++
2 files changed, 3 insertions(+)
For this to be a non-RFC patch, this needs to be a proper
On 2/21/23 9:21 PM, Philippe Mathieu-Daudé wrote:
On 21/2/23 10:21, Gavin Shan wrote:
On 2/21/23 8:15 PM, Philippe Mathieu-Daudé wrote:
On 21/2/23 09:53, Gavin Shan wrote:
Linux kernel guest reports warning when two CPUs in one socket have
been associated with different NUMA nodes, using the
The underlying call uses vaddr and the comms API uses unsigned long
long which will always fit. We don't need to deal in target_ulong
here.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
gdbstub/gdbstub.c | 4 ++--
1 file changed, 2
Our GDB syscall support is the last chunk of code that needs target
specific support so move it to a new file. We take the opportunity to
move the syscall state into its own singleton instance and add in a
few helpers for the main gdbstub to interact with the module.
I also moved the gdb_exit()
Currently we only support replay for softmmu mode so it is a constant
false for user-mode.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
v3
- rename gdb_stub_can_revers -> gdb_can_reverse
---
gdbstub/internals.h | 1 +
gdbstub/gdbstub.c
This is a hangover from the original code. addr is misleading as it is
only really a register id. While len will never exceed
MAX_PACKET_LENGTH I've used size_t as that is what strlen returns.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
v3
The two implementations are different enough to encourage having a
specialisation and we can move some of the softmmu only stuff out of
gdbstub.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 19
gdbstub/gdbstub.c | 73
These inline helpers are all used by target specific code so move them
out of the general header so we don't needlessly pollute the rest of
the API with target specific stuff.
Note we have to include cpu.h in semihosting as it was relying on a
side effect before.
Reviewed-by: Taylor Simpson
Now we have removed any target specific bits from the core gdbstub
code we only need to build it twice. We have to jump a few meson hoops
to manually define the CONFIG_USER_ONLY symbol but it seems to work.
Signed-off-by: Alex Bennée
---
v3
- also include user and softmmu bits in the library
Currently when we encounter a gdb that is old or not built with
multiarch in mind we fail rather messily. Try and improve the
situation by probing ahead of time and setting
HOST_GDB_SUPPORTS_ARCH=y in the relevant tcg configs. We can then skip
and give a more meaningful message if we don't run the
We unfortunately handle the checking of packet acknowledgement
differently for user and softmmu modes. Abstract the user mode stuff
behind gdb_got_immediate_ack with a stub for softmmu.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Alex Bennée
---
While we will continue to include this via cpu-defs it is useful to be
able to define this separately for 32 and 64 bit versions of an
otherwise target independent compilation unit.
Signed-off-by: Alex Bennée
---
include/exec/cpu-defs.h| 19 +
include/exec/target_long.h | 42
We don't really need a table for mapping two symbols.
Signed-off-by: Alex Bennée
Suggested-by: Richard Henderson
---
gdbstub/softmmu.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c
index 864ecee38f..79674b8bea
This is needed for handling vcont packets as the way of calculating
max cpus vhanges between user and softmmu mode.
Reviewed-by: Richard Henderson
Signed-off-by: Alex Bennée
---
v3
- rm out of date comment
---
gdbstub/internals.h | 1 +
gdbstub/gdbstub.c | 11 +--
Most of the syscall code is config agnostic aside from the size of
target_ulong. In preparation for the next patch move the final bits of
specialisation into the appropriate user and softmmu helpers.
Signed-off-by: Alex Bennée
---
gdbstub/internals.h | 5 +
gdbstub/softmmu.c | 24
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