On Mon, Mar 6, 2023 at 11:36 AM Jason Wang wrote:
>
>
> 在 2023/2/8 10:57, Cindy Lu 写道:
> > 1.Add support for vIOMMU.
> > Add the new function to deal with iommu MR.
> > - during iommu_region_add register a specific IOMMU notifier,
> >and store all notifiers in a list.
> > - during
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC right after verifying that
On 09-03-23, 14:20, Viresh Kumar wrote:
> Hello,
>
> This patchset tries to update the vhost-user protocol to make it support
> special
> memory mapping required in case of Xen hypervisor.
>
> The first patch is mostly cleanup and second one introduces a new xen specific
> feature.
>
> V2->V3:
Commit 4f67543bb8c5 ("xen/pt: reserve PCI slot 2 for Intel igd-passthru")
uses slot_reserved_mask to reserve slot 2 for the Intel igd for the
xenfv machine when the guest is configured for igd-passthru.
Prior to that commit, a single 32-bit mask was sufficient to meet the
needs of the only
This patch provides accessor functions as replacements for direct
access to slot_reserved_mask according to the comment at the top
of include/hw/pci/pci_bus.h which advises that data structures for
PCIBus should not be directly accessed but instead be accessed using
accessor functions in pci.h.
This patch series consists of two patches. The first provides accessor
functions in pci.h to avoid direct access of slot_reserved_mask
according to the comment at the top of include/hw/pci/pci_bus.h. No
functional change is intended with this patch.
The second patch replaces slot_reserved_mask
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
We have one last case where we're changing env->misa_ext* during
validation. riscv_cpu_disable_priv_spec_isa_exts(), at the end of
riscv_cpu_validate_set_extensions(), will disable cpu->cfg.ext_h and
cpu->cfg.ext_v if priv_ver check fails.
On Wed, Mar 8, 2023 at 4:09 AM Philipp Tomsich wrote:
>
>
> After the original Zicond support was stuck/fell through the cracks on
> the mailing list at v3 (and a different implementation was merged in
> the meanwhile), we now refactor Zicond and then reuse it in
> XVentanaCondOps.
>
>
> Philipp
On Thu, Mar 9, 2023 at 5:15 PM Weiwei Li wrote:
>
> The patchset tries to:
>
> - Use riscv_cpu_cfg(env) instead of env_archcpu().cfg.
> - Use env_archcpu() to get RISCVCPU pointer from env directly
> - Use CPURISCVState as argument directly in riscv_cpu_update_mip and
> riscv_timer_write_timecmp
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
We have a chained dependency in riscv_cpu_validate_set_extensions()
related to RVV. If RVV is set, we enable other extensions such as
Zve64d, Zve64f and Zve32f, and these depends on misa bits RVD and RVF.
Thus, we're making RVV depend on RVD
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
We can set all RVG related extensions during realize time, before
validate_set_extensions() itself. It will also avoid re-enabling
RVG via write_misa() when the CSR start to using the same validation
code realize() does.
Note that we're
On 2023/3/15 00:49, Daniel Henrique Barboza wrote:
We're getting ready to use riscv_cpu_validate_set_extensions() to unify
the handling of write_misa() with the rest of the code base. But first
we need to deal with RVG.
The 'G' virtual extension enables a set of extensions in the CPU. At
this
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
first release candidate for the QEMU 8.0 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-8.0.0-rc0.tar.xz
Don't disable all big-endian tests, instead check whether $(CORE) is
supported by the configured $(QEMU) and enable tests if it is.
Signed-off-by: Max Filippov
Reviewed-by: Philippe Mathieu-Daudé
---
MAINTAINERS| 1 +
tests/tcg/xtensa/Makefile.softmmu-target |
v1: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg04372.html
v1 -> v2: Fix SSM and STOSM (Nina).
Fix LPSW (Nina).
Check bits 12 and 24 (Nina).
Improve the commit message (Nina).
Improve naming (David).
Hi,
Currently loading bad PSW flags does
Generate a specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addressing
mode.
Reported-by: Nina Schoetterl-Glausch
Signed-off-by: Ilya Leoshkevich
---
target/s390x/cpu.c | 26 ++
Add several small tests that check the PSW modification instructions:
* lpsw.S checks whether LPSW works correctly in the "happy" case.
* lpswe-early.S checks whether early exceptions are recognized and
whether the correct ILC and old PSW are stored when they happen.
* ssm-early.S,
Currently LPSW does not invert the mask bit 12 and incorrectly copies
the BA bit into the address.
Fix by generating code similar to what s390_cpu_load_normal() does.
Reported-by: Nina Schoetterl-Glausch
Co-developed-by: Nina Schoetterl-Glausch
Signed-off-by: Ilya Leoshkevich
---
On 15/03/2023 01:15, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> The RDMA code has return-path handling code, but it's only enabled
> if postcopy is enabled; if the 'return-path' migration capability
> is enabled, the return path is NOT setup but the core migration
On Tue, 2023-03-14 at 17:08 -0700, Max Filippov wrote:
> On Tue, Mar 14, 2023 at 4:41 PM Wilfred Mallawa
> wrote:
> >
> > On Tue, 2023-03-14 at 15:08 -0700, Max Filippov wrote:
> > > Linker script for xtensa tests must be preprocessed for a
> > > specific
> > > target, remove it as a part of
v1: https://lists.gnu.org/archive/html/qemu-devel/2023-03/msg04316.html
v1 -> v2: Address the middle of an array in the test (Richard).
Rebase - not 100% trivial, so not carrying Reviewed-bys.
Hi,
This series fixes EXECUTE of instructions like LARL, LGLR, etc.
Currently the address
Test EXECUTE and EXECUTE RELATIVE LONG with relative long instructions
as targets.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target| 1 +
tests/tcg/s390x/ex-relative-long.c | 159 +
2 files changed, 160 insertions(+)
create mode 100644
The code uses the wrong base for relative addressing: it should use the
target instruction address and not the EXECUTE's address.
Fix by storing the target instruction address in the new CPUS390XState
member and loading it from the code generated by gen_ri2().
Reported-by: Nina
On Tue, Mar 14, 2023 at 4:41 PM Wilfred Mallawa wrote:
>
> On Tue, 2023-03-14 at 15:08 -0700, Max Filippov wrote:
> > Linker script for xtensa tests must be preprocessed for a specific
> > target, remove it as a part of make clean.
> >
> > Signed-off-by: Max Filippov
> > ---
> >
On Wed, Mar 15, 2023 at 3:09 AM Peter Maydell wrote:
>
> The cadence UART attempts to avoid allowing the guset to set invalid
> baud rate register values in the uart_write() function. However it
> does the "mask to the size of the register field" and "check for
> invalid values" in the wrong
On Tue, 2023-03-14 at 15:08 -0700, Max Filippov wrote:
> Linker script for xtensa tests must be preprocessed for a specific
> target, remove it as a part of make clean.
>
> Signed-off-by: Max Filippov
> ---
> tests/tcg/xtensa/Makefile.softmmu-target | 1 +
> 1 file changed, 1 insertion(+)
On Tue, 2023-03-14 at 17:08 +, Peter Maydell wrote:
> The cadence UART attempts to avoid allowing the guset to set invalid
> baud rate register values in the uart_write() function. However it
> does the "mask to the size of the register field" and "check for
> invalid values" in the wrong
Add a small test for RXSBG with T=1 to prevent regressions.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target | 1 +
tests/tcg/s390x/rxsbg.c | 25 +
2 files changed, 26 insertions(+)
create mode 100644 tests/tcg/s390x/rxsbg.c
diff --git
Hi,
This series fixes ROTATE THEN SELECTED BITS when
test-results control is on. The problem is the incorrect translation,
which confuses the register allocator.
Patch 1 is the fix, patch 2 adds a test.
Best regards,
Ilya
Ilya Leoshkevich (2):
target/s390x: Fix R[NOX]SBG with T=1
RXSBG usage in the "filetests" test from the wasmtime testsuite makes
tcg_reg_alloc_op() attempt to temp_load() a TEMP_VAL_DEAD temporary,
causing an assertion failure:
0x01000a70: ec14 b040 3057 rxsbg%r1, %r4, 0xb0, 0x40, 0x30
OP after optimization and liveness analysis:
Linker script for xtensa tests must be preprocessed for a specific
target, remove it as a part of make clean.
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile.softmmu-target | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/tcg/xtensa/Makefile.softmmu-target
On Sat, Mar 11, 2023 at 3:42 PM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> This patch adds WDT to Allwinner-H3 and Orangepi-PC.
> WDT is added as an overlay to the Timer module memory area.
>
> Signed-off-by: Strahinja Jankovic
>
Reviewed-by: Niek Linnenbank
> ---
>
Replace python 2 format string with f-strings
Signed-off-by: Marco Liebel
---
target/hexagon/gen_analyze_funcs.py | 115 -
target/hexagon/gen_helper_funcs.py | 54 ++--
target/hexagon/gen_helper_protos.py | 10 +-
target/hexagon/gen_idef_parser_funcs.py | 8 +-
Hi Strahinja,
On Sat, Mar 11, 2023 at 3:42 PM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> This patch adds WDT to Allwinner-A10 and Cubieboard.
> WDT is added as an overlay to the Timer module memory map.
>
> Signed-off-by: Strahinja Jankovic
> ---
>
Hi Strahinja,
On Sat, Mar 11, 2023 at 3:41 PM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> This patch adds basic support for Allwinner WDT.
> Both sun4i and sun6i variants are supported.
> However, interrupt generation is not supported, so WDT can be used only to
> trigger system
QEMU main thread will wait until dest preempt channel established during
processing the LISTEN command (within the whole postcopy PACKAGED data), by
waiting on the semaphore postcopy_qemufile_dst_done.
That's racy, because it's possible that the dest QEMU main thread hasn't
yet accept()ed the new
On Tue, Mar 14, 2023 at 07:31:38PM +, Peter Maydell wrote:
> On Tue, 14 Mar 2023 at 16:46, Peter Xu wrote:
> > I've attached that simple fix. Peter, is it easy to verify it? I'm not
> > sure the reproducability, fine by me too if it's easier to just disable
> > preempt tests for 8.0
> -Original Message-
> From: Taylor Simpson
> Sent: Dienstag, 14. März 2023 18:54
> To: Marco Liebel (QUIC) ; qemu-
> de...@nongnu.org
> Subject: RE: [PATCH] Use f-strings in python scripts
>
>
>
> > -Original Message-
> > From: Marco Liebel (QUIC)
> > Sent: Monday, March 13,
Am 03.02.2023 um 14:17 hat Emanuele Giuseppe Esposito geschrieben:
> Just remove some AioContext lock in LinuxAioState and ThreadPool.
> Not related to anything specific, so I decided to send it as
> a separate patch.
>
> These patches are taken from Paolo's old draft series.
Thanks, applied to
Am 13.03.2023 um 01:37 hat Wilfred Mallawa geschrieben:
> From: Wilfred Mallawa
>
> Fixup a few minor typos
>
> Signed-off-by: Wilfred Mallawa
Thanks, applied to the block-next branch.
Kevin
Hi Strahinja,
Looks good! I re-ran the tests on my machine, and they work fine:
ARMBIAN_ARTIFACTS_CACHED=yes AVOCADO_ALLOW_LARGE_STORAGE=yes
./build/tests/venv/bin/avocado --show=app,console run -t
machine:orangepi-pc -t machine:cubieboard
tests/avocado/boot_linux_console.py
...
|console: Tue
On Tue, 14 Mar 2023 at 16:46, Peter Xu wrote:
> I've attached that simple fix. Peter, is it easy to verify it? I'm not
> sure the reproducability, fine by me too if it's easier to just disable
> preempt tests for 8.0 release.
If you all are happy that the fix is correct, I think the easiest
Am 14.03.23 um 12:50 schrieb Dorinda Bassey:
Hi Volker,
Thank you for the clarification. I see the problem now.
So is it safe to say that:
@@ -104,8 +104,9 @@ playback_on_process(void *data)
/* calculate the total no of bytes to read data from buffer */
req = b->requested *
ainer Ben Widawsky (2023-03-14 14:46:38 +0100)
>
>
> trivial branch pull request 20230314
>
> Update MAINTAINER file
> Fix typo in qemu-options.hx
>
>
Applied, thanks.
Please upd
On Mon, 13 Mar 2023 at 20:02, wrote:
>
> From: Marc-André Lureau
>
> The following changes since commit 284c52eec2d0a1b9c47f06c3eee46762c5fc0915:
>
> Merge tag 'win-socket-pull-request' of
> https://gitlab.com/marcandre.lureau/qemu into staging (2023-03-13 13:44:17
> +)
>
> are available
-13 13:44:17
> +)
>
> are available in the Git repository at:
>
> https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230314
>
> for you to fetch changes up to 0d581506de803204c5a321100afa270573382932:
>
> Fix incorrect register name in disassembler for
On Tue, Mar 14, 2023 at 6:08 PM Peter Maydell
wrote:
> The cadence UART attempts to avoid allowing the guset to set invalid
> baud rate register values in the uart_write() function. However it
> does the "mask to the size of the register field" and "check for
> invalid values" in the wrong
On 3/14/23 9:53 AM, Fan Ni wrote:
Replace the magic number 32 with CXL_RAS_ERR_HEADER_NUM for better code
readability and maintainability.
Signed-off-by: Fan Ni
Reviewed-by: Dave Jiang
---
include/hw/cxl/cxl_device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 3/14/23 06:47, Wu, Fei wrote:
On 3/13/2023 11:00 PM, Richard Henderson wrote:
On 3/13/23 07:13, Wu, Fei2 wrote:
Hi Richard,
Sorry for disturbing you. I'm doing some perf profiling on qemu-riscv64,
I see 10%+ faster to build stress-ng without the following patch. I know
it's incorrect to
* Peter Xu (pet...@redhat.com) wrote:
> On Tue, Mar 14, 2023 at 05:15:58PM +, Dr. David Alan Gilbert (git) wrote:
> > From: "Dr. David Alan Gilbert"
> >
> > The RDMA code has return-path handling code, but it's only enabled
> > if postcopy is enabled; if the 'return-path' migration
On Tue, 2023-03-14 at 12:00 +0100, Ilya Leoshkevich wrote:
> Generate specification exception if a reserved bit is set in the PSW
Generate a ...
> mask or if the PSW address is out of bounds dictated by the addresing
addresSing
> mode.
Does this approach also work with SET SYSTEM MASK and
On Tue, 14 Mar 2023, Fan Ni wrote:
Replace the magic number 32 with CXL_RAS_ERR_HEADER_NUM for better code
readability and maintainability.
Reviewed-by: Davidlohr Bueso
Signed-off-by: Fan Ni
---
include/hw/cxl/cxl_device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Tue, Mar 14, 2023 at 05:15:58PM +, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> The RDMA code has return-path handling code, but it's only enabled
> if postcopy is enabled; if the 'return-path' migration capability
> is enabled, the return path is NOT setup but
> -Original Message-
> From: Marco Liebel (QUIC)
> Sent: Monday, March 13, 2023 11:26 AM
> To: qemu-devel@nongnu.org
> Cc: Taylor Simpson ; Marco Liebel (QUIC)
>
> Subject: [PATCH] Use f-strings in python scripts
>
> Replace python 2 format string with f-strings
>
> Signed-off-by:
On Tue, Mar 14, 2023 at 12:46:34PM -0400, Peter Xu wrote:
> On Tue, Mar 14, 2023 at 10:11:53AM +, Dr. David Alan Gilbert wrote:
> > OK, I think I kind of see what's happening here, one for Peter Xu.
> > If I'm right it's a race something like:
> > a) The test harness tells the source it
On 14/03/2023 15.17, Peter Maydell wrote:
On Tue, 14 Mar 2023 at 14:14, Thomas Huth wrote:
On 14/03/2023 15.08, Peter Maydell wrote:
On Tue, 14 Mar 2023 at 14:01, Thomas Huth wrote:
On 14/03/2023 14.33, Peter Maydell wrote:
The postcopy/preempt tests seem to have a race which makes them
On 14/03/2023 18.08, Peter Maydell wrote:
The cadence UART attempts to avoid allowing the guset to set invalid
baud rate register values in the uart_write() function. However it
does the "mask to the size of the register field" and "check for
invalid values" in the wrong order, which means that
On 3/14/23 09:49, Daniel Henrique Barboza wrote:
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in
On 3/14/23 18:30, Cornelia Huck wrote:
Add 8.1 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
For ppc,
Reviewed-by: Cédric Le Goater
Thanks,
C.
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c
Add 8.1 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Signed-off-by: Cornelia Huck
---
hw/arm/virt.c | 9 -
hw/core/machine.c | 3 +++
hw/i386/pc.c | 3 +++
hw/i386/pc_piix.c | 16 +---
hw/i386/pc_q35.c | 14
From: "Dr. David Alan Gilbert"
The RDMA code has return-path handling code, but it's only enabled
if postcopy is enabled; if the 'return-path' migration capability
is enabled, the return path is NOT setup but the core migration
code still tries to use it and breaks.
Enable the RDMA return path
Am 09.03.2023 um 20:08 hat Stefan Hajnoczi geschrieben:
> v2:
> - Clarify NULL ctx argument in Patch 1 commit description [Kevin]
>
> AIO_WAIT_WHILE_UNLOCKED() is the future replacement for AIO_WAIT_WHILE(). Most
> callers haven't been converted yet because they rely on the AioContext lock. I
>
The cadence UART attempts to avoid allowing the guset to set invalid
baud rate register values in the uart_write() function. However it
does the "mask to the size of the register field" and "check for
invalid values" in the wrong order, which means that a malicious
guest can get a bogus value
On 3/13/23 16:38, Ilya Leoshkevich wrote:
Test EXECUTE and EXECUTE RELATIVE LONG with relative long instructions
as targets.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.target| 1 +
tests/tcg/s390x/ex-relative-long.c | 149 +
2 files
On Mon, 13 Mar 2023 at 07:13, Gavin Shan wrote:
>
> On 2/27/23 12:26 PM, Gavin Shan wrote:
> > This series intends to support dirty ring for live migration for arm64. The
> > dirty ring use discrete buffer to track dirty pages. For arm64, the
> > speciality
> > is to use backup bitmap to track
ping?
On 24/2/23 16:34, Philippe Mathieu-Daudé wrote:
First, IDE_DMA__COUNT represents the number of enumerated
values, but is incorrectly listed as part of the enum.
Second, IDE_DMA_CMD_str() is internal to core.c and only
takes sane enums from ide_dma_cmd. So no need to check the
'enval'
Cc'ing qemu-trivial@
On 24/2/23 22:41, Philippe Mathieu-Daudé wrote:
When modifying QAPI scripts and modifying C files along,
it makes sense to display QAPI changes first.
Signed-off-by: Philippe Mathieu-Daudé
---
Failed example:
On 3/14/2023 10:39 AM, Mark Cave-Ayland wrote:
> On 14/03/2023 14:21, Chuck Zmudzinski wrote:
>
> > On 3/14/2023 9:41 AM, Mark Cave-Ayland wrote:
> >> On 14/03/2023 13:26, Chuck Zmudzinski wrote:
> >>
> >>> On 3/14/2023 9:17 AM, Michael S. Tsirkin wrote:
> On Tue, Mar 14, 2023 at 12:43:12PM
On 14.03.23 12:00, Ilya Leoshkevich wrote:
Generate specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addresing
mode.
Reported-by: Nina Schoetterl-Glausch
Unofficially known to be broken (and ignored) for a long time :D
Replace the magic number 32 with CXL_RAS_ERR_HEADER_NUM for better code
readability and maintainability.
Signed-off-by: Fan Ni
---
include/hw/cxl/cxl_device.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index
Even after taking RVG off from riscv_cpu_validate_set_extensions(), the
function is still doing too much. It is validating misa bits, then
validating named extensions, and if the validation succeeds it's doing
more changes in both cpu->cfg and MISA bits.
It works for the support we have today,
Now that the function is a no-op if 'env.misa_ext != 0', and no one that
are setting misa_ext != 0 is calling it because set_misa() is setting
the cpu cfg accordingly, remove the now deprecated code and rename the
function to register_generic_cpu_props().
This function is now doing exactly what
set_misa() is setting all 'misa' related env states and nothing else.
But other functions, namely riscv_cpu_validate_set_extensions(), uses
the config object to do its job.
This creates a need to set the single letter extensions in the cfg
object to keep both in sync. At this moment this is being
We're getting ready to use riscv_cpu_validate_set_extensions() to unify
the handling of write_misa() with the rest of the code base. But first
we need to deal with RVG.
The 'G' virtual extension enables a set of extensions in the CPU. At
this moment, this is done at the start of our validation
We have one last case where we're changing env->misa_ext* during
validation. riscv_cpu_disable_priv_spec_isa_exts(), at the end of
riscv_cpu_validate_set_extensions(), will disable cpu->cfg.ext_h and
cpu->cfg.ext_v if priv_ver check fails.
This check can be done in riscv_cpu_validate_misa_ext().
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 18591aa53a..2752efe1eb
write_misa() must use as much common logic as possible. We want to open
code just the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC right after verifying that we're not updating RVG;
- mask the write using
We're now ready to split riscv_cpu_validate_set_extensions() in two.
None of these steps are going to touch env->misa_ext*.
riscv_cpu_validate_extensions() will take care of all validations based
on cpu->cfg values. cpu->cfg changes that are required for the
validation are being tolerated here.
The 'G' bit in misa_ext is a virtual extension that enables a set of
extensions (i, m, a, f, d, icsr and ifencei). We'll want to avoid
setting it for write_misa(). Add it so we can gate write_misa() properly
against it.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 4
write_misa() is able to use the same validation workflow
riscv_cpu_realize() uses. But it's still not capable of updating
cpu->cfg misa props yet.
We have no way of blocking future (and current) code from checking
env->misa_ext (via riscv_has_ext()) or reading cpu->cfg directly, so our
best
All these generic CPUs are using the latest priv available, at this
moment PRIV_VERSION_1_12_0:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll
make it easier to update everything
Similar to what we did with riscv_cpu_validate_misa_ext(), let's read
all MISA bits from a misa_ext val instead of reading from the cpu->cfg
object.
This will allow write_misa() to use riscv_cpu_validate_extensions().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 25
set_misa() will be tuned up to do more than it's already doing and it
will be redundant to what riscv_cpu_validate_set_extensions() does.
Note that we don't ever change env->misa_mlx in this function, so
set_misa() can be replaced by just assigning env->misa_ext and
env->misa_ext_mask to 'ext'.
We have a chained dependency in riscv_cpu_validate_set_extensions()
related to RVV. If RVV is set, we enable other extensions such as
Zve64d, Zve64f and Zve32f, and these depends on misa bits RVD and RVF.
Thus, we're making RVV depend on RVD and RVF.
Let's add this dependency in
We can set all RVG related extensions during realize time, before
validate_set_extensions() itself. It will also avoid re-enabling
RVG via write_misa() when the CSR start to using the same validation
code realize() does.
Note that we're setting both cfg->ext_N and env->misa_ext bits, instead
of
The setter is doing nothing special. Just set env->priv_ver directly.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
In the near future, write_misa() will use a variation of what we have
now as riscv_cpu_validate_set_extensions(). The pmp and epmp validation
will be required in write_misa() and it's already required here in
riscv_cpu_realize(), so move it to riscv_cpu_validate_set_extensions().
Signed-off-by:
Let's remove more code that is open coded in riscv_cpu_realize() and put
it into a helper. Let's also add an error message instead of just
asserting out if env->misa_mxl_max != env->misa_mlx.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 51
The extremely tedious code that sets cpu->cfg based on misa_ext, and
vice-versa, is scattered around riscv_cpu_validate_set_extensions() and
set_misa().
Introduce helpers to do this work, cleaning up the logic of both
functions a bit. While we're at it, add a note in cpu.h informing that
any
riscv_cpu_validate_v() consists of checking RVV related attributes, such
as vlen and elen, and setting env->vext_spec.
This can be done during riscv_cpu_validate_misa_ext() time, allowing us
to fail earlier if RVV constrains are not met.
Signed-off-by: Daniel Henrique Barboza
---
We're doing env->priv_spec validation and assignment at the start of
riscv_cpu_realize(), which is fine, but then we're doing a force disable
on extensions that aren't compatible with the priv version.
This second step is being done too early. The disabled extensions might be
re-enabled again in
Hello,
In this v2 the most notable changes were done after Liu Zhiwei review in
[1], in particular the comments made in patch 17. To allow for
write_misa() validation, without the need to store and restore cpu->cfg
state, more design changes were required in the existing validation
logic.
The
We have all MISA specific validations in riscv_cpu_validate_misa_ext(),
and we have a guarantee that env->misa_ext will always be in sync with
cpu->cfg at this point during realize time, so let's convert it to use a
'misa_ext' parameter instead of reading cpu->cfg.
This will prepare the function
We have 4 config settings being done in riscv_cpu_init(): ext_ifencei,
ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu"
device, which happens to be the parent device of every RISC-V cpu.
The result is that these 4 configs are being set every time, and every
other CPU should
In the process of creating the user-facing flags in
register_generic_cpu_props() we're also setting default values for the
cpu->cfg flags that represents MISA bits.
Leaving it as is will cause a discrepancy between users of this function
(at this moment the non-named CPUs) and named CPUs. Named
There is no need to init timers if we're not even sure that our
extensions are valid. Execute riscv_cpu_validate_set_extensions() before
riscv_timer_init().
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git
The RVV verification will error out if fails and it's being done at the
end of riscv_cpu_validate_set_extensions(). Let's put it in its own
function and do it earlier.
We'll move it out of riscv_cpu_validate_set_extensions() in the near future,
but for now this is enough to clean the code a bit.
On Tue, Mar 14, 2023 at 10:11:53AM +, Dr. David Alan Gilbert wrote:
> OK, I think I kind of see what's happening here, one for Peter Xu.
> If I'm right it's a race something like:
> a) The test harness tells the source it wants to enter postcopy
> b) The harness then waits for the source
On 3/14/23 04:00, Ilya Leoshkevich wrote:
Add a small test that checks whether early exceptions are recognized
and whether the correct ILC and old PSW are stored when they happen.
Signed-off-by: Ilya Leoshkevich
---
tests/tcg/s390x/Makefile.softmmu-target | 1 +
On 3/14/23 04:00, Ilya Leoshkevich wrote:
Generate specification exception if a reserved bit is set in the PSW
mask or if the PSW address is out of bounds dictated by the addresing
mode.
Reported-by: Nina Schoetterl-Glausch
Signed-off-by: Ilya Leoshkevich
---
target/s390x/cpu.c |
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