On 6/6/23 22:46, Richard Henderson wrote:
Two recent regressions, both related to recent tcg changes.
Our CI does not test TCI with --enable-debug-tcg, which given timeout
constraints is probably correct, but in this case resulted in an
infinite loop on aarch64 multiarch/memory.c with FEAT_LSE2
We require either 2 or 4 registers to hold int128_t.
Failure to do so results in a register allocation assert.
Signed-off-by: Richard Henderson
---
tcg/tci/tcg-target.c.inc | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/tcg/tci/tcg-target.c.inc
Two recent regressions, both related to recent tcg changes.
Our CI does not test TCI with --enable-debug-tcg, which given timeout
constraints is probably correct, but in this case resulted in an
infinite loop on aarch64 multiarch/memory.c with FEAT_LSE2 enabled.
r~
Richard Henderson (2):
Since adding MO_ATOM_MASK, the maximum MemOpIdx requires 15 bits,
which overflows the 12 bit field allocated for TCI memory ops.
Expand the field to 16 bits for 2-operand memory ops, and place
the value in TCG_REG_TMP for 3-operand memory ops (same as we
already do for 4-operand memory ops).
Hello Nick,
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -443,7 +443,7 @@ void spr_write_generic32(DisasContext *ctx, int sprn, int
gprn)
#endif
}
-void spr_write_CTRL(DisasContext *ctx, int sprn, int gprn)
+static void spr_write_CTRL_ST(DisasContext *ctx, int sprn,
and get rid of an unnecessary drive_get(IF_MTD) call.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index efc112ca37b0..8beed0c2a66e 100644
It will help in getting rid of some drive_get(IF_MTD) calls by
retrieving the BlockBackend directly from the m25p80 device.
Cc: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
include/hw/block/flash.h | 4
hw/block/m25p80.c| 6 ++
2
Simple routine to retrieve a DeviceState object on a SPI bus using its
address/cs. It will be useful for the board to wire the CS lines.
Cc: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/ssi.h | 2 ++
hw/ssi/ssi.c | 15
This to avoid address conflicts on the same SSI bus. Adapt machines
using multiple devices on the same bus to avoid breakage.
Cc: "Edgar E. Iglesias"
Cc: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
hw/arm/stellaris.c | 4 +++-
As mentioned in docs/devel/style.rst "Automatic memory deallocation":
* Variables declared with g_auto* MUST always be initialized,
otherwise the cleanup function will use uninitialized stack memory
This avoids QEMU to coredump when running the "hash test" command
under Zephyr.
Cc: Steven Lee
Cortex A7 CPUs with an FPU implementing VFPv4 without NEON support
have 16 64-bit FPU registers and not 32 registers. Let users set the
number of VFP registers with a CPU property.
The primary use case of this property is for the Cortex A7 of the
Aspeed AST2600 SoC.
Signed-off-by: Cédric Le
This should also avoid Coverity to report a memory leak warning when
the QEMU process exits. See CID 1508061.
Reviewed-by: Francisco Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
hw/arm/aspeed.c | 12 ++--
1 file changed, 6 insertions(+), 6
Currently, a set of default flash devices is created at machine init
and drives defined on the QEMU command line are associated to the FMC
and SPI controllers in sequence :
-drive file,format=raw,if=mtd
-drive file,format=raw,if=mtd
The CS lines are wired in the same creation loop. This
When the -nodefaults option is set, flash devices should be created
with :
-blockdev node-name=fmc0,driver=file,filename=./flash.img \
-device mx66u51235f,addr=0x0,bus=ssi.0,drive=fmc0 \
To be noted that in this case, the ROM will not be installed and the
initial boot sequence (U-Boot
Hello,
This series fixes issues spotted by Coverity and adds a couple of
improvements for the machine definition.
The first is to offer the capability to define all CS of all SPI
controllers without introducing new machine types, using a blockdev on
the command line :
-blockdev
This change completes commits 5aa281d757 ("aspeed: Introduce a
spi_boot region under the SoC") and 8b744a6a47 ("aspeed: Add a
boot_rom overlap region in the SoC spi_boot container") which
introduced a spi_boot container at the SoC level to map the boot rom
region as an overlap.
It also fixes a
Boards will use this new property to identify the device CS line and
wire the SPI controllers accordingly.
Cc: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Cédric Le Goater
---
include/hw/ssi/ssi.h | 3 +++
hw/ssi/ssi.c | 7 +++
2 files changed, 10
Most of the Aspeed machines use the UART5 device for the boot console,
and QEMU connects the first serial Chardev to this SoC device for this
purpose. See routine connect_serial_hds_to_uarts().
Nevertheless, some machines use another boot console, such as the fuji,
and commit 5d63d0c76c
On Tue, 6 Jun 2023 at 19:28, Thomas Huth wrote:
>
> The ppc64 tuxrun tests are currently failing if "slirp" has been
> disabled in the binary since they are using "-netdev user" now.
> We have to skip the test if this network backend is missing.
Do the boot tests require networking? I doubt they
On Wed, 7 Jun 2023 10:33:13 +0800, Yuquan Wang wrote:
>
> Please review the change.
> - sbsa-ref: Replace EHCI with XHCI on sysbus.
> This version updates relevant Kconfig and sbsa.rst file.
>
> Yuquan Wang (1):
> hw/arm/sbsa-ref: use XHCI to replace EHCI
>
>
>-Original Message-
>From: Peter Xu
>Sent: Tuesday, June 6, 2023 11:42 PM
>Subject: Re: [PATCH v2 2/4] intel_iommu: Fix a potential issue in VFIO dirty
>page sync
>
...
>> >> a/include/exec/memory.h b/include/exec/memory.h index
>> >> c3661b2276c7..eecc3eec6702 100644
>> >> ---
Hi,
> -Original Message-
> From: Daniel Henrique Barboza
> Sent: Tuesday, June 6, 2023 6:31 PM
> To: Wang, Xiao W ; qemu-devel@nongnu.org
> Cc: Palmer Dabbelt ; Alistair Francis
> ; Meng, Bin ; Weiwei
> Li ; Liu Zhiwei ; open
> list:RISC-V TCG CPUs
> Subject: Re: [PATCH]
Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
(32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
supported since QEMU 7.0, default to use SMBIOS 3.0 for newer machine
models. This is necessary to avoid the following message when launching
a VM
Into a helper function pc_machine_init_smbios() in preparation for
subsequent code to upgrade default SMBIOS entry point type.
Then, call the helper function from the pc_machine_initfn() to eliminate
duplicate code in pc_q35.c and pc_pixx.c. However, this changes the
ordering of when the
Since KVM_MAX_VCPUS is currently defined to 1024 for x86 as shown in
arch/x86/include/asm/kvm_host.h, update QEMU limits to the same number.
In case KVM could not support the specified number of vcpus, QEMU would
return the following error message:
qemu-system-x86_64: kvm_init_vcpu:
In order to support large number of vcpus, a newer 64-bit SMBIOS
entry point type is needed. Therefore, upgrade the default SMBIOS version
for PC machines to SMBIOS 3.0 for newer systems. Then increase the maximum
number of vCPUs for Q35 models to 1024, which is the limit for KVM.
Changes from
Please review the change.
- sbsa-ref: Replace EHCI with XHCI on sysbus.
This version updates relevant Kconfig and sbsa.rst file.
Yuquan Wang (1):
hw/arm/sbsa-ref: use XHCI to replace EHCI
docs/system/arm/sbsa.rst | 2 +-
hw/arm/Kconfig | 2 +-
hw/arm/sbsa-ref.c| 21
The current sbsa-ref cannot use EHCI controller which is only
able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
Hence, this uses system bus XHCI to provide a usb controller with
64-bit DMA capablity instead of EHCI.
Signed-off-by: Yuquan Wang
---
docs/system/arm/sbsa.rst | 2 +-
Igor,
On 6/6/2023 3:11 PM, Igor Mammedov wrote:
On Tue, 6 Jun 2023 09:35:41 +0200
Igor Mammedov wrote:
On Mon, 5 Jun 2023 16:39:05 -0500
Suravee Suthikulpanit wrote:
[...]
+/* For pc-i44fx-8.0 and older, use SMBIOS 2.8 by default */
+pcmc->default_smbios_ep_type =
On 6/6/2023 2:35 PM, Igor Mammedov wrote:
On Mon, 5 Jun 2023 16:39:05 -0500
Suravee Suthikulpanit wrote:
Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
(32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is now fully
supported since QEMU 7.0, default to
Igor,
On 6/6/2023 2:55 PM, Igor Mammedov wrote:
On Mon, 5 Jun 2023 16:39:06 -0500
Suravee Suthikulpanit wrote:
Since KVM_MAX_VCPUS is currently defined to 1024 for x86 as shown in
arch/x86/include/asm/kvm_host.h, update QEMU limits to the same number.
In case KVM could not support the
Igore,
On 6/6/2023 2:45 PM, Igor Mammedov wrote:
On Mon, 5 Jun 2023 16:39:04 -0500
Suravee Suthikulpanit wrote:
In preparation for subsequent code to upgrade default SMBIOS
entry point type. There is no functional change.
Signed-off-by: Suravee Suthikulpanit
---
hw/i386/pc.c | 12
On 6/6/23 07:31, Paolo Bonzini wrote:
+if ! test -f "$source_path/subprojects/keycodemapdb/README" \
+&& test -f "$download" = disabled
test -f x = y
is some sort of paste-o. Remove the -f, I'm sure.
r~
On 6/6/23 3:50 PM, Richard Henderson wrote:
On 6/6/23 11:51, Garhwal, Vikram wrote:
Hi Richard,
I fixed the tsan-build issue but now seeing another issue with
“—disable-tcg” option for cross builds xen. Here is the build failure
message:
"include/tcg/oversized-guest.h:10:10: fatal error:
On 6/6/23 11:51, Garhwal, Vikram wrote:
Hi Richard,
I fixed the tsan-build issue but now seeing another issue with “—disable-tcg” option for
cross builds xen. Here is the build failure message:
"include/tcg/oversized-guest.h:10:10: fatal error: tcg-target-reg-bits.h: No such file or
directory
Fixes the build for --disable-tcg.
This header is only needed for cross-hosting. Without CONFIG_TCG,
we know this is an AArch64 host, CONFIG_ATOMIC64 will be set, and
the TCG_OVERSIZED_GUEST block will never be compiled.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 5 +++--
1 file
We are not currently running a --disable-tcg test for arm64,
like we are for mips, ppc and s390x. We have a job for the
native aarch64 runner, but it is not run by default and it
is not helpful for normal developer testing without access
to qemu's private runner.
Use --without-default-features
Broken during my build tcg once series.
I thought we already had a test for this, but no, so add one.
r~
Richard Henderson (2):
target/arm: Only include tcg/oversized-guest.h if CONFIG_TCG
gitlab: Add cross-arm64-kvm-only
target/arm/ptw.c | 5 +++--
Sorry for reviving this old thread, I lost the best timing to follow up
on this while I was on vacation. I have been working on this and found
out some discrepancy, please see below.
On 4/5/23 04:37, Eugenio Perez Martin wrote:
Hi!
As mentioned in the last upstream virtio-networking meeting,
Hi Steve,
In the current design you have, we have to specify both the command line
parameter "-migrate-mode-enable cpr-reboot"
*and* issue the monitor command "migrate_set_parameter mode cpr-${mode}".
Is it possible to opt-in to the CPR mode just once over the monitor
instead of having to
Count exceptions which can be queried with info irq monitor command.
Signed-off-by: BALATON Zoltan
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c| 18 ++
target/ppc/excp_helper.c | 1 +
3 files changed, 20 insertions(+)
diff --git a/target/ppc/cpu.h
/qemu into
staging (2023-06-05 13:16:56 -0700)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230606
for you to fetch changes up to f9ac778898cb28307e0f91421aba34d43c34b679:
target/arm: trap DCC access in user mode
On 6/6/23 16:46, Loïc Lefort wrote:
On Tue, Jun 6, 2023 at 1:39 PM Himanshu Chauhan
wrote:
Smepmp is a ratified extension which qemu refers to as epmp.
Rename epmp to smepmp and add it to extension list so that
it is added to the isa string.
Signed-off-by: Himanshu Chauhan
---
On 6/6/23 12:29, Ilya Leoshkevich wrote:
The only concrete objection I have is the change of API, which could
be fixed with return
get_errno(openat(...)).
I believe both openat() and safe_openat() return -1 on error and set
errno, or am I missing something?
Oops, no, bad memory on my part --
On 6/6/23 16:28, Thomas Huth wrote:
The ppc64 tuxrun tests are currently failing if "slirp" has been
disabled in the binary since they are using "-netdev user" now.
We have to skip the test if this network backend is missing.
Fixes: 6ee3624236 ("improve code coverage for ppc64")
On 6/6/23 10:19, Andrew Jones wrote:
On Tue, May 30, 2023 at 04:46:10PM -0300, Daniel Henrique Barboza wrote:
We're going to change the handling of mvendorid/marchid/mimpid by the
KVM driver. Since these are always present in all CPUs let's put the
same validation for everyone.
It doesn't
On 6/6/23 10:13, Andrew Jones wrote:
On Tue, May 30, 2023 at 04:46:09PM -0300, Daniel Henrique Barboza wrote:
The absence of a satp mode in riscv_host_cpu_init() is causing the
following error:
$ sudo ./qemu/build/qemu-system-riscv64 -machine virt,accel=kvm \
-m 2G -smp 1 -nographic
On Tue, Jun 06, 2023 at 04:34:31PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Tue, Jun 06, 2023 at 11:45:49AM -0300, Fabiano Rosas wrote:
> >> The code in threadinfo.c is only used for the QMP command
> >> query-migrationthreads. Make it explicit that this is something
> >> related
On Tue, Jun 6, 2023 at 4:23 AM Paolo Bonzini wrote:
>
> Let pip decide whether a new version should be installed or the current
> one is okay. This ensures that the virtual environment is updated
> (either upgraded or downgraded) whenever a new version of a package is
> requested.
>
> The
On Tue, Jun 6, 2023 at 1:39 PM Himanshu Chauhan
wrote:
>
> Smepmp is a ratified extension which qemu refers to as epmp.
> Rename epmp to smepmp and add it to extension list so that
> it is added to the isa string.
>
> Signed-off-by: Himanshu Chauhan
> ---
> target/riscv/cpu.c | 9 +
On Mon, Jun 5, 2023 at 12:00 PM Paolo Bonzini wrote:
>
> This reverts commits eea2d141179 ("Makefile: remove $(TESTS_PYTHON)",
> 2023-05-26) and 9c6692db550 ("tests: Use configure-provided pyvenv for
> tests", 2023-05-18).
>
> Right now, there is a conflict between wanting a ">=" constraint when
On 6/6/23 12:24, Philippe Mathieu-Daudé wrote:
On 6/6/23 18:25, Richard Henderson wrote:
This test consistently fails on Azure cloud build hosts in
a way that suggests a timing problem in the test itself:
--- .../194.out
+++ .../194.out.bad
@@ -14,7 +14,6 @@
{"return": {}}
{"data":
On Mon, Jun 5, 2023 at 12:00 PM Paolo Bonzini wrote:
>
> Bumping avocado to version 101 has two issues. First, there are problems
> where Avocado is not logging of command lines or terminal output, and not
> collecting Python logs outside the avocado namespace.
>
> Second, the recent changes to
On 6/6/23 21:28, Thomas Huth wrote:
The ppc64 tuxrun tests are currently failing if "slirp" has been
disabled in the binary since they are using "-netdev user" now.
We have to skip the test if this network backend is missing.
Fixes: 6ee3624236 ("improve code coverage for ppc64")
Signed-off-by:
Peter Xu writes:
> On Tue, Jun 06, 2023 at 11:45:49AM -0300, Fabiano Rosas wrote:
>> The code in threadinfo.c is only used for the QMP command
>> query-migrationthreads. Make it explicit that this is something
>> related to QMP.
>>
>> The current names are also too generic for a piece of code
On Tue, 2023-06-06 at 11:24 -0700, Richard Henderson wrote:
> On 6/6/23 06:27, Ilya Leoshkevich wrote:
> > @@ -8518,7 +8522,11 @@ int do_guest_openat(CPUArchState *cpu_env,
> > int dirfd, const char *pathname,
> > return fd;
> > }
> >
> > - return safe_openat(dirfd,
The ppc64 tuxrun tests are currently failing if "slirp" has been
disabled in the binary since they are using "-netdev user" now.
We have to skip the test if this network backend is missing.
Fixes: 6ee3624236 ("improve code coverage for ppc64")
Signed-off-by: Thomas Huth
---
On 6/6/23 18:25, Richard Henderson wrote:
This test consistently fails on Azure cloud build hosts in
a way that suggests a timing problem in the test itself:
--- .../194.out
+++ .../194.out.bad
@@ -14,7 +14,6 @@
{"return": {}}
{"data": {"status": "setup"}, "event": "MIGRATION", "timestamp":
On 06/06/2023 18.25, Richard Henderson wrote:
This test consistently fails on Azure cloud build hosts in
a way that suggests a timing problem in the test itself:
--- .../194.out
+++ .../194.out.bad
@@ -14,7 +14,6 @@
{"return": {}}
{"data": {"status": "setup"}, "event": "MIGRATION",
On 6/6/23 07:30, Paolo Bonzini wrote:
The following changes since commit 369081c4558e7e940fa36ce59bf17b2e390f55d3:
Merge tag 'pull-tcg-20230605' ofhttps://gitlab.com/rth7680/qemu into
staging (2023-06-05 13:16:56 -0700)
are available in the Git repository at:
On 6/6/23 20:08, Warner Losh wrote:
On Tue, Jun 6, 2023 at 8:29 AM Richard Henderson
mailto:richard.hender...@linaro.org>> wrote:
On 6/6/23 07:12, Philippe Mathieu-Daudé wrote:
> Since commit 139c1837db ("meson: rename included C source files
> to .c.inc"), QEMU standard
hstate_inode() is hugetlbfs-specific, limiting
hugetlb_add_to_page_cache() to hugetlbfs.
hugetlb_filemap_add_folio() allows hstate to be specified and further
separates hugetlb from hugetlbfs.
Signed-off-by: Ackerley Tng
---
include/linux/hugetlb.h | 2 ++
mm/hugetlb.c| 13
hstate and subpool being retrievable from inode via hstate_inode() and
subpool_inode() respectively is a hugetlbfs concept.
hugetlb should be agnostic of hugetlbfs and hugetlb accounting
functions should accept hstate (required) and subpool (can be NULL)
independently of inode.
inode is still a
Refactor restore_reserve_on_error to allow resv_map to be passed
in. vma_resv_map() assumes the use of hugetlbfs in the way it
retrieves the resv_map from the vma and inode.
Introduce restore_reserve_on_error_vma() which retains original
functionality to simplify refactoring for now.
Add tests for 2MB and 1GB page sizes.
Signed-off-by: Ackerley Tng
---
.../testing/selftests/kvm/guest_memfd_test.c | 33 ++-
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/tools/testing/selftests/kvm/guest_memfd_test.c
This will allow preparation steps to be shared
Signed-off-by: Ackerley Tng
---
include/linux/mm.h | 1 +
mm/truncate.c | 24 ++--
2 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 1f79667824eb..7a8f6b810de0
vma_*_reservation functions rely on vma_resv_map(), which assumes on a
hugetlbfs concept of the resv_map being stored in a specific field of
the inode.
This refactor enables vma_*_reservation functions, now renamed
resv_map_*_reservation, to be used with non-hugetlbfs filesystems,
further
Cleanup in kvm_gmem_release() should be the reverse of
kvm_gmem_create_file().
Cleanup in kvm_gmem_evict_inode() should be the reverse of
kvm_gmem_create_inode().
Signed-off-by: Ackerley Tng
---
virt/kvm/guest_mem.c | 105 +--
1 file changed, 71
Parametrize alloc_hugetlb_folio_from_subpool() by resv_map to remove
the use of vma_resv_map() and decouple hugetlb with hugetlbfs.
Signed-off-by: Ackerley Tng
---
include/linux/hugetlb.h | 2 +-
mm/hugetlb.c| 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git
Hello,
This patchset builds upon a soon-to-be-published WIP patchset that Sean
published at https://github.com/sean-jc/linux/tree/x86/kvm_gmem_solo, mentioned
at [1].
The tree can be found at:
https://github.com/googleprodkernel/linux-cc/tree/gmem-hugetlb-rfc-v1
In this patchset, hugetlb
Parametrize remove_mapping_hugepages() and hugetlb_unreserve_pages()
by resv_map to remove the use of inode_resv_map() and decouple hugetlb
with hugetlbfs.
Signed-off-by: Ackerley Tng
---
fs/hugetlbfs/inode.c| 16 ++--
include/linux/hugetlb.h | 6 --
mm/hugetlb.c
subpool_inode() and hstate_inode() are hugetlbfs-specific.
By allowing subpool and hstate to be specified, hugetlb is further
modularized from hugetlbfs.
Signed-off-by: Ackerley Tng
---
include/linux/hugetlb.h | 3 +++
mm/hugetlb.c| 16
2 files changed, 15
Expose inode_resv_map() so that hugetlbfs can access its own resv_map.
Hide restore_reserve_on_error_vma(), that function is now only used
within mm/hugetlb.c.
Signed-off-by: Ackerley Tng
---
fs/hugetlbfs/inode.c| 2 +-
include/linux/hugetlb.h | 21 +++--
mm/hugetlb.c
First create a gmem inode, then create a gmem file using the inode,
then install the file into an fd.
Creating the file in layers separates inode concepts (struct kvm_gmem)
from file concepts and makes cleaning up in stages neater.
Signed-off-by: Ackerley Tng
---
virt/kvm/guest_mem.c | 86
Expose get_hstate_idx() so it can be used from KVM's guest_mem code
Signed-off-by: Ackerley Tng
---
fs/hugetlbfs/inode.c| 9 -
include/linux/hugetlb.h | 14 ++
2 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/fs/hugetlbfs/inode.c b/fs/hugetlbfs/inode.c
First stage of hugetlb support: add initialization and cleanup
routines
Signed-off-by: Ackerley Tng
---
include/uapi/linux/kvm.h | 25
virt/kvm/guest_mem.c | 88 +---
2 files changed, 108 insertions(+), 5 deletions(-)
diff --git
Adds support for various type of backing sources for private
memory (in the sense of confidential computing), similar to the
backing sources available for shared memory.
Signed-off-by: Ackerley Tng
---
.../testing/selftests/kvm/include/test_util.h | 14
Introduce kvm_gmem_hugetlb_get_folio(), then update
kvm_gmem_allocate() and kvm_gmem_truncate() to use hugetlb functions.
Signed-off-by: Ackerley Tng
---
virt/kvm/guest_mem.c | 215 +--
1 file changed, 188 insertions(+), 27 deletions(-)
diff --git
Update private_mem_conversions_test for various private memory backing
source types
Signed-off-by: Ackerley Tng
---
.../kvm/x86_64/private_mem_conversions_test.c | 38 ++-
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git
Zeroing of pages is generalizable to hugetlb and is not specific to
hugetlbfs.
Rename hugetlbfs_zero_partial_page => hugetlb_zero_partial_page, move
it to mm/hugetlb.c and expose it in linux/hugetlb.h.
Signed-off-by: Ackerley Tng
---
fs/hugetlbfs/inode.c| 27 ++-
TODO may want to move this to hugetlb
Signed-off-by: Ackerley Tng
---
fs/hugetlbfs/inode.c| 3 +--
include/linux/hugetlb.h | 4
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/fs/hugetlbfs/inode.c b/fs/hugetlbfs/inode.c
index 3dab50d3ed88..4f25df31ae80 100644
---
Hi Richard,
I fixed the tsan-build issue but now seeing another issue with “—disable-tcg”
option for cross builds xen. Here is the build failure message:
"include/tcg/oversized-guest.h:10:10: fatal error: tcg-target-reg-bits.h: No
such file or directory
10 | #include "tcg-target-reg-bits.h”
06.06.2023 16:57, Christian Schoenebeck wrote:
..
+++ b/fsdev/virtfs-proxy-helper.c
+static int open_regular(const char *pathname, int flags, mode_t mode) {
+int fd;
+struct stat stbuf;
+
+fd = open(pathname, flags, mode);
+if (fd < 0) {
+return fd;
+}
+
+/*
On Tue, Jun 06, 2023 at 11:45:50AM -0300, Fabiano Rosas wrote:
> This doubly linked list is common for all the multifd and migration
> threads so we need to avoid concurrent access.
>
> Add a mutex to protect the data from concurrent access. This fixes a
> crash when removing two MigrationThread
On Tue, Jun 06, 2023 at 11:45:49AM -0300, Fabiano Rosas wrote:
> The code in threadinfo.c is only used for the QMP command
> query-migrationthreads. Make it explicit that this is something
> related to QMP.
>
> The current names are also too generic for a piece of code that
> doesn't affect the
On 5/23/23 03:15, Philippe Mathieu-Daudé wrote:
While reviewing, the ROUND_UP() macro is easier to figure out.
Besides, the comment confirms we want to round up here.
Signed-off-by: Philippe Mathieu-Daudé
---
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
From: Shashi Mallela
Included creation of ITS as part of SBSA platform GIC
initialization.
Signed-off-by: Shashi Mallela
---
hw/arm/sbsa-ref.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index
In 2021 Shashi Mallela sent v8 of GIC ITS patchset [1]. At that time it
was decided to do platform versioning first.
1.
https://lore.kernel.org/qemu-devel/20210812165341.40784-8-shashi.mall...@linaro.org/
Now we are going through our list of changes for SBSA Reference Platform
and GIC ITS is
On 6/6/23 06:27, Ilya Leoshkevich wrote:
@@ -8518,7 +8522,11 @@ int do_guest_openat(CPUArchState *cpu_env, int dirfd,
const char *pathname,
return fd;
}
-return safe_openat(dirfd, path(pathname), flags, mode);
+if (safe) {
+return safe_openat(dirfd,
We need GIC ITS information in DeviceTree so TF-A can pass it to EDK2.
Bumping platform version to 0.2 as this is important hardware change.
Signed-off-by: Marcin Juszkiewicz
---
hw/arm/sbsa-ref.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/arm/sbsa-ref.c
On Tue, Jun 6, 2023 at 8:29 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 6/6/23 07:12, Philippe Mathieu-Daudé wrote:
> > Since commit 139c1837db ("meson: rename included C source files
> > to .c.inc"), QEMU standard procedure for included C files is to
> > use *.c.inc.
> >
> >
On 6/6/23 06:27, Ilya Leoshkevich wrote:
/proc/self/smaps is an extension of /proc/self/maps: it provides the
same lines, plus additional information about each range.
GDB uses /proc/self/smaps when available, which means that
generate-core-file tries it first before falling back to
On 06/06/2023 16:05, Peter Xu wrote:
> On Tue, Jun 06, 2023 at 11:03:11AM -0400, Peter Xu wrote:
>> On Tue, Jun 06, 2023 at 12:22:16PM +0100, Joao Martins wrote:
>>> On 05/06/2023 17:57, Peter Xu wrote:
On Tue, May 30, 2023 at 06:59:25PM +0100, Joao Martins wrote:
> Much like
On Tue, 6 Jun 2023 at 18:16, Richard Henderson
wrote:
>
> The computation is documented as unused in this case,
> but triggers an ubsan error:
>
> ../accel/tcg/ldst_atomicity.c.inc:837:33: runtime error: shift exponent -32
> is negative
> SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior
Hi,
Can you please rebase on top of Alistair's riscv-to-apply.next and re-send?
Some patches can't be applied cleanly, in particular patch 2, which conflicts
with Weiwei's "target/riscv: Split RISCVCPUConfig declarations from cpu.h
into cpu_cfg.h" that landed into riscv-to-apply.next a few
The computation is documented as unused in this case,
but triggers an ubsan error:
../accel/tcg/ldst_atomicity.c.inc:837:33: runtime error: shift exponent -32 is
negative
SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior
../accel/tcg/ldst_atomicity.c.inc:837:33 in
Signed-off-by: Richard
Philippe Mathieu-Daudé writes:
> Since commit 139c1837db ("meson: rename included C source files
> to .c.inc"), QEMU standard procedure for included C files is to
> use *.c.inc.
>
> Besides, since commit 6a0057aa22 ("docs/devel: make a statement
> about includes") this is documented as the
Philippe Mathieu-Daudé writes:
> Follow the convention to use the .inc extension for .c/.h files
> re-included, as docummented in Coding Style since commit 6a0057aa22:
>
> If you do use template header files they should be named with
> the ``.c.inc`` or ``.h.inc`` suffix to make it
On Tue, 6 Jun 2023, Igor Mammedov wrote:
On Sun, 28 May 2023 15:57:50 +0200 (CEST)
BALATON Zoltan wrote:
On pegasos2 which has ACPI as part of VT8231 south bridge the board
firmware writes PM control register by accessing the second byte so
addr will be 1. This wasn't handled correctly and
Jun Sun writes:
> It seems to me that we are OK with random as default behavior but we should
> print out the seed (and abstract it into
> a shared function across arches).
>
> Happy to re-work the patch if my understanding is correct.
Works for me. Please respin.
--
Alex Bennée
1 - 100 of 329 matches
Mail list logo
