Thanks for the review! :)
> All new source files must start with a license-and-copyright
comment.
> ... snip ...
> Generally in QEMU we prefer to typedef the function type,
not the pointer-to-function type.
> ... snip ...
> You should probably mark all these asm statements as 'volatile'
> to
From: Marcin Juszkiewicz
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Thomas Huth
Message-id: 20230607092112.655098-1-marcin.juszkiew...@linaro.org
Signed-off-by: Peter Maydell
---
hw/arm/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index
The nrf51_timer has a free-running counter which we implement using
the pattern of using two fields (update_counter_ns, counter) to track
the last point at which we calculated the counter value, and the
counter value at that time. Then we can find the current counter
value by converting the
On Mon, Jun 05, 2023 at 06:41:07PM +0800, Sam Li wrote:
> By adding zone operations and zoned metadata, the zoned emulation
> capability enables full emulation support of zoned device using
> a qcow2 file. The zoned device metadata includes zone type,
> zoned device state and write pointer of each
From: Marcin Juszkiewicz
We plan to add more hardware information into DeviceTree to limit amount
of hardcoded values in firmware.
Signed-off-by: Marcin Juszkiewicz
Message-id: 20230531171834.236569-1-marcin.juszkiew...@linaro.org
[PMM: fix format nits, add text about platform version fields
Convert the LDR and STR instructions which use a 12-bit immediate
offset to decodetree. We can reuse the existing LDR and STR
trans functions for these.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-14-peter.mayd...@linaro.org
---
On Mon, 19 Jun 2023 at 15:31, John Högberg wrote:
>
> Thanks for the review! :)
>
> > All new source files must start with a license-and-copyright
> comment.
> > ... snip ...
> > Generally in QEMU we prefer to typedef the function type,
> not the pointer-to-function type.
> > ... snip ...
> > You
Convert the LDR and STR instructions which take a register
plus register offset to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-15-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode | 22 +
Convert the "Load register (literal)" instruction class to
decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-11-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode | 13 ++
target/arm/tcg/translate-a64.c | 76
Convert the instructions in the load/store memory tags instruction
group to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-21-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode | 25 +++
target/arm/tcg/translate-a64.c | 360
Convert the load/store register pair insns (LDP, STP,
LDNP, STNP, LDPSW, STGP) to decodetree.
Signed-off-by: Peter Maydell
Message-id: 20230602155223.2040685-12-peter.mayd...@linaro.org
Reviewed-by: Richard Henderson
---
target/arm/tcg/a64.decode | 61 +
In disas_ldst_reg_imm9() we missed one place where a call to
a gen_mte_check* function should now be passed the memop we
have created rather than just being passed the size. Fix this.
Fixes: 0a9091424d ("target/arm: Pass memop to gen_mte_check1*")
Signed-off-by: Peter Maydell
Reviewed-by:
Convert the instructions in the load/store register (pointer
authentication) group ot decodetree: LDRAA, LDRAB.
Signed-off-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-17-peter.mayd...@linaro.org
---
The LDG instruction loads the tag from a memory address (identified
by [Xn + offset]), and then merges that tag into the destination
register Xt. We implemented this correctly for the case when
allocation tags are enabled, but didn't get it right when ATA=0:
instead of merging the tag bits into
QEMU allows qemu_irq lines to transfer arbitrary integers. However
the convention is that for a simple IRQ line the values transferred
are always 0 and 1. The A10 SD controller device instead assumes a
0-vs-non-0 convention, which happens to work with the interrupt
controller it is wired up to.
From: Sergey Kambalin
Signed-off-by: Sergey Kambalin
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230612223456.33824-4-phi...@linaro.org
Message-Id: <20230531155258.8361-1-sergey.kamba...@auriga.com>
[PMD: Split from bigger patch: 4/4]
Signed-off-by:
Convert the insns in the atomic memory operations group to
decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-16-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode | 15
target/arm/tcg/translate-a64.c | 153
Convert the ASIMD load/store single structure insns to decodetree.
Signed-off-by: Peter Maydell
Message-id: 20230602155223.2040685-20-peter.mayd...@linaro.org
Reviewed-by: Richard Henderson
---
target/arm/tcg/a64.decode | 34 +
target/arm/tcg/translate-a64.c | 219
From: Sergey Kambalin
Replace magic property values by a proper definition,
removing redundant comments.
Signed-off-by: Sergey Kambalin
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Message-id: 20230612223456.33824-3-phi...@linaro.org
Message-Id:
Convert the instructions in the load/store exclusive (STXR,
STLXR, LDXR, LDAXR) and load/store ordered (STLR, STLLR,
LDAR, LDLAR) to decodetree.
Note that for STLR, STLLR, LDAR, LDLAR this fixes an under-decoding
in the legacy decoder where we were not checking that the RES1 bits
in the Rs and
Convert the instructions in the ASIMD load/store multiple structures
instruction classes to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-19-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode | 20 +++
Convert the load and store instructions which use a 9-bit
immediate offset to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-13-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode | 69 +++
In commit 2c5fa0778c3b430 we fixed an endianness bug in the Allwinner
A10 PIC model; however in the process we introduced a regression.
This is because the old code was robust against the incoming 'level'
argument being something other than 0 or 1, whereas the new code was
not.
In particular, the
From: Sergey Kambalin
Signed-off-by: Sergey Kambalin
Signed-off-by: Philippe Mathieu-Daudé
Acked-by: Richard Henderson
Message-id: 20230612223456.33824-2-phi...@linaro.org
Message-Id: <20230531155258.8361-1-sergey.kamba...@auriga.com>
[PMD: Split from bigger patch: 1/4]
Signed-off-by:
From: Sergey Kambalin
Signed-off-by: Sergey Kambalin
Signed-off-by: Philippe Mathieu-Daudé
Message-id: 20230612223456.33824-5-phi...@linaro.org
Message-Id: <20230531155258.8361-1-sergey.kamba...@auriga.com>
[PMD: Split from bigger patch: 3/4]
Signed-off-by: Philippe Mathieu-Daudé
[PMM: added
Convert the instructions in the LDAPR/STLR (unscaled immediate)
group to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-18-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode | 10 +++
target/arm/tcg/translate-a64.c | 132
Convert the various instructions in the hint instruction space
to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-3-peter.mayd...@linaro.org
---
target/arm/tcg/a64.decode | 31
target/arm/tcg/translate-a64.c | 277
Convert the load/store exclusive pair (LDXP, STXP, LDAXP, STLXP),
compare-and-swap pair (CASP, CASPA, CASPAL, CASPL), and compare-and
swap (CAS, CASA, CASAL, CASL) instructions to decodetree.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id:
Convert the insns in the "Barriers" instruction class to
decodetree: CLREX, DSB, DMB, ISB and SB.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-4-peter.mayd...@linaro.org
Reviewed-by: Philippe Mathieu-Daudé
---
target/arm/tcg/a64.decode |
The atomic memory operations are supposed to return the old memory
data value in the destination register. This value is not
sign-extended, even if the operation is the signed minimum or
maximum. (In the pseudocode for the instructions the returned data
value is passed to ZeroExtend() to create
Convert the MSR (immediate) insn to decodetree. Our implementation
has basically no commonality between the different destinations,
so we decode the destination register in a64.decode.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id:
Convert the CFINV, XAFLAG and AXFLAG insns to decodetree.
The old decoder handles these in handle_msr_i(), but
the architecture defines them as separate instructions
from MSR (immediate).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id:
into
staging (2023-06-16 12:30:16 +0200)
are available in the Git repository at:
https://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20230619
for you to fetch changes up to 074259c0f2ac40042dce766d870318cc22f388eb:
hw/misc/bcm2835_property: Handle CORE_CLK_ID firmware
Convert the exception generation instructions SVC, HVC, SMC, BRK and
HLT to decodetree.
The old decoder decoded the halting-debug insnns DCPS1, DCPS2 and
DCPS3 just in order to then make them UNDEF; as with DRPS, we don't
bother to decode them, but document the patterns in a64.decode.
From: Martin Kaiser
The Linux kernel added a flood check for RX data recently in commit
496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This
check uses the wake bit in the UART status register 2. The wake bit
indicates that the receiver detected a start bit on the RX line. If
Convert MSR (reg), MRS, SYS, SYSL to decodetree. For QEMU these are
all essentially the same instruction (system register access).
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Message-id: 20230602155223.2040685-7-peter.mayd...@linaro.org
Reviewed-by: Philippe Mathieu-Daudé
---
In the recent refactoring we missed a few places which should be
calling finalize_memop_asimd() for ASIMD loads and stores but
instead are just calling finalize_memop(); fix these.
For the disas_ldst_single_struct() and disas_ldst_multiple_struct()
cases, this is not a behaviour change because
The microblaze architecture does not reorder instructions.
While there is an MBAR wait-for-data-access instruction,
this concerns synchronizing with DMA.
This should have been defined when enabling MTTCG.
Cc: Alistair Francis
Cc: Edgar E. Iglesias
Fixes: d449561b130 ("configure: microblaze:
We now issue host memory barriers to match the guest memory order.
Continue to disable MTTCG only if the guest has not been ported.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-all.c | 39 ++-
1 file changed, 10 insertions(+), 29 deletions(-)
diff
v1:
https://lore.kernel.org/qemu-devel/20210316220735.2048137-1-richard.hender...@linaro.org/
v2:
https://lore.kernel.org/qemu-devel/20230306015710.1868853-1-richard.hender...@linaro.org/
Changes for v3:
* Update for tcg-built-once.
* Require TCG_GUEST_DEFAULT_MO if TARGET_SUPPORTS_MTTCG.
Bring the helpers into line with the rest of tcg in respecting
guest memory ordering.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 34 ++
accel/tcg/cputlb.c| 10 ++
accel/tcg/user-exec.c | 10 ++
3 files changed, 54
Reduce the set of required barriers to those needed by
the host right from the beginning.
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 7aadb37756..574001c221 100644
--- a/tcg/tcg-op.c
The virtio devices require proper memory ordering between
the vcpus and the iothreads.
Signed-off-by: Richard Henderson
---
tcg/tcg-op.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index c07de5d9f8..7aadb37756 100644
---
One cannot test for feature aa32_simd_r32 without first
testing if AArch32 mode is supported at all. This leads to
qemu-system-aarch64: ARM CPUs must have both VFP-D32 and Neon or neither
for Apple M1 cpus.
We already have a check for ARMv8-A never setting vfp-d32 true,
so restructure the code
On 9/6/23 04:23, Richard Henderson wrote:
Add a primitive for InvSubBytes + InvShiftRows +
AddRoundKey + InvMixColumns.
Signed-off-by: Richard Henderson
---
host/include/generic/host/aes-round.h | 3 +++
include/crypto/aes-round.h| 21 +
crypto/aes.c
On 6/19/23 15:41, Peter Maydell wrote:
On Mon, 19 Jun 2023 at 13:47, Mads Ynddal wrote:
Sorry, if this has already been acknowledged, but I couldn't find it on the
mailinglist.
This commit seems to break compatibility with macOS accelerator hvf when
virtualizing ARM CPUs.
It breaks the VM
Il dom 18 giu 2023, 23:51 Paolo Bonzini ha scritto:
> TCG supports both 32-bit and 64-bit SYSCALL, so expose it
> with "-cpu max" even for 32-bit emulators.
>
Nope, this is broken... My bad for assuming that glibc will use syscall if
available—that doesn't happen because the syscall instruction
> ARM's "Vector Floating Point" unit has many implementation with different
> features: VFPv3-D16/D32, *FP16, VFPv4-D16/D32, Neon, etc. The test might
> be too strict and could possibly be removed.
>
> Could you send us the result of 'cat /proc/cpuinfo' on the host ?
>
> Thanks,
>
> C.
The
On 9/6/23 04:23, Richard Henderson wrote:
This implements the VNCIPHER instruction.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/6/23 04:23, Richard Henderson wrote:
These arrays are no longer used, replaced by AES_SH_*, AES_ISH_*.
Signed-off-by: Richard Henderson
---
include/crypto/aes.h | 4
crypto/aes.c | 14 --
2 files changed, 18 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Mon, 19 Jun 2023 at 14:26, Richard Henderson
wrote:
>
> Otherwise we hit the default assert not reached.
> Handle it as MO_ATOM_NONE, because of size and misalignment.
> We already handle this correctly in do_ld16_beN.
>
> Signed-off-by: Richard Henderson
> ---
>
> Fixes an abort booting
On Mon, 19 Jun 2023 at 13:47, Mads Ynddal wrote:
>
> Sorry, if this has already been acknowledged, but I couldn't find it on the
> mailinglist.
>
> This commit seems to break compatibility with macOS accelerator hvf when
> virtualizing ARM CPUs.
>
> It breaks the VM on boot-up with the message
On Mon, 12 Jun 2023 at 23:34, Philippe Mathieu-Daudé wrote:
>
> v2:
> https://lore.kernel.org/qemu-devel/20230612115950.5002-1-sergey.kamba...@auriga.com/
>
> This is a respin of Sergey's patch but
> - split in multiple patches
> - removing redundant comments
Applied to target-arm.next (with
On Mon, 12 Jun 2023 at 23:35, Philippe Mathieu-Daudé wrote:
>
> From: Sergey Kambalin
>
> Signed-off-by: Sergey Kambalin
> Message-Id: <20230531155258.8361-1-sergey.kamba...@auriga.com>
> [PMD: Split from bigger patch: 3/4]
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> TOCHECK: seems
W dniu 19.06.2023 o 14:55, Peter Maydell pisze:
On Tue, 6 Jun 2023 at 19:24, Marcin Juszkiewicz
wrote:
We need GIC ITS information in DeviceTree so TF-A can pass it to EDK2.
Bumping platform version to 0.2 as this is important hardware change.
We should fold this patch into the previous
On Mon, 12 Jun 2023 at 10:40, ~jhogberg wrote:
>
> From: John Högberg
>
> https://gitlab.com/qemu-project/qemu/-/issues/1034
>
> Signed-off-by: John Högberg
> diff --git a/tests/tcg/aarch64/icivau.c b/tests/tcg/aarch64/icivau.c
> new file mode 100644
> index 00..ff80d3d868
> ---
Otherwise we hit the default assert not reached.
Handle it as MO_ATOM_NONE, because of size and misalignment.
We already handle this correctly in do_ld16_beN.
Signed-off-by: Richard Henderson
---
Fixes an abort booting debian11 with -cpu max.
r~
---
accel/tcg/cputlb.c | 1 +
1 file changed,
On 9/6/23 04:23, Richard Henderson wrote:
This array is no longer used.
Signed-off-by: Richard Henderson
---
include/crypto/aes.h | 7 --
crypto/aes.c | 264 ---
2 files changed, 271 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/6/23 04:23, Richard Henderson wrote:
These arrays are no longer used outside of aes.c.
Signed-off-by: Richard Henderson
---
include/crypto/aes.h | 25 -
crypto/aes.c | 33 +
2 files changed, 21 insertions(+), 37
On 6/19/23 14:47, Mads Ynddal wrote:
Sorry, if this has already been acknowledged, but I couldn't find it on the
mailinglist.
This commit seems to break compatibility with macOS accelerator hvf when
virtualizing ARM CPUs.
It breaks the VM on boot-up with the message "ARM CPUs must have both
On 19/6/23 12:36, Peter Maydell wrote:
On Thu, 15 Jun 2023 at 15:24, Martin Kaiser wrote:
The Linux kernel added a flood check for RX data recently in commit
496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This
check uses the wake bit in the UART status register 2. The wake
From: Foxes Hung
Signed-off-by: Foxes Hung
---
gdbstub/syscalls.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gdbstub/syscalls.c b/gdbstub/syscalls.c
index 02e3a8f74c..4c6b5f728b 100644
--- a/gdbstub/syscalls.c
+++ b/gdbstub/syscalls.c
@@ -126,7 +126,7 @@ void
On Tue, 6 Jun 2023 at 19:24, Marcin Juszkiewicz
wrote:
>
> We need GIC ITS information in DeviceTree so TF-A can pass it to EDK2.
>
> Bumping platform version to 0.2 as this is important hardware change.
>
> Signed-off-by: Marcin Juszkiewicz
>
> ---
> hw/arm/sbsa-ref.c | 9 -
> 1 file
On Tue, 6 Jun 2023 at 19:24, Marcin Juszkiewicz
wrote:
>
> From: Shashi Mallela
>
> Included creation of ITS as part of SBSA platform GIC
> initialization.
>
> Signed-off-by: Shashi Mallela
Marcin, this should have your signed-off-by too because
the patch came to us via you.
> +static void
W dniu 19.06.2023 o 14:41, Peter Maydell pisze:
I'm going to apply this to target-arm.next with this squashed in
to fix a few grammar/format nits and add some text from the comment
in the source file about the platform version part.
Thanks.
My English grammar sucks so I am glad that you
Hi,
> Adding a new command requires new feature flag (and maybe it should be in
> the <0x1000 range instead)
>
> But I am not sure we need a new message at the virtio-gpu level. Gerd, wdyt?
>
> Maybe it's not a good place to reset all GPU resources during QEMU reset()
> after all, if it's
On Wed, 7 Jun 2023 at 03:34, Yuquan Wang wrote:
>
> The current sbsa-ref cannot use EHCI controller which is only
> able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
> Hence, this uses system bus XHCI to provide a usb controller with
> 64-bit DMA capablity instead of EHCI.
Sorry, if this has already been acknowledged, but I couldn't find it on the
mailinglist.
This commit seems to break compatibility with macOS accelerator hvf when
virtualizing ARM CPUs.
It breaks the VM on boot-up with the message "ARM CPUs must have both VFP-D32
and Neon or neither". I haven't
On Wed, 31 May 2023 at 18:18, Marcin Juszkiewicz
wrote:
>
> We plan to add more hardware information into DeviceTree to limit amount
> of hardcoded values in firmware.
>
> Signed-off-by: Marcin Juszkiewicz
I'm going to apply this to target-arm.next with this squashed in
to fix a few
On Thu, Jun 08, 2023 at 01:49:27PM -0700, Mike Kravetz wrote:
> This effectively reverts commit 16c243e99d33 ("udmabuf: Add support
> for mapping hugepages (v4)"). Recently, Junxiao Chang found a BUG
> with page map counting as described here [1]. This issue pointed out
> that the udmabuf driver
On Tue, Jun 13, 2023 at 05:58:57PM -0300, Daniel Henrique Barboza wrote:
> If we don't set a proper cbom_blocksize|cboz_blocksize in the FDT the
> Linux Kernel will fail to detect the availability of the CBOM/CBOZ
> extensions, regardless of the contents of the 'riscv,isa' DT prop.
>
> The FDT is
Simply fix the #vcpus_count to @vcpus_count in CPUArchId comments. Whlie
at it, reorder the parameters in comments to match the sequence of
parameters which defined in the CPUArchId.
Reviewed-by: Igor Mammedov
Signed-off-by: Shaoqin Huang
---
include/hw/boards.h | 4 ++--
1 file changed, 2
On 13/06/2023 12:50, Markus Armbruster wrote:
Mark Cave-Ayland writes:
On 01/06/2023 10:00, Markus Armbruster wrote:
Mark Cave-Ayland writes:
On 31/05/2023 16:00, Markus Armbruster wrote:
Philippe Mathieu-Daudé writes:
On 31/5/23 14:53, Mark Cave-Ayland wrote:
Also change the
On 05/06/2023 13:41, Philippe Mathieu-Daudé wrote:
On 4/6/23 15:14, Mark Cave-Ayland wrote:
This will allow the q800-glue.h header to be included separately so that the
GLUE device can be referenced externally.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Laurent Vivier
---
MAINTAINERS
On Sat, 10 Jun 2023 at 04:51, Akihiko Odaki wrote:
>
> On 2022/12/01 20:00, Akihiko Odaki wrote:
> > On 2022/12/01 19:40, Peter Maydell wrote:
> >> On Thu, 1 Dec 2022 at 10:27, Akihiko Odaki
> >> wrote:
> >>>
> >>> A register access error typically means something seriously wrong
> >>> happened
On Wed, 14 Jun 2023 at 14:02, Chris Laplante wrote:
>
> Hi all,
>
> I am working on improving nRF51 emulation. Specifically I want to implement
> the special "System OFF" mode. System OFF is a power saving mode. In this
> mode, the system can only be woken up by a reset or a handful of
> On 15-Jun-2023, at 4:56 PM, Igor Mammedov wrote:
>
> On Thu, 15 Jun 2023 10:46:45 +0530
> Ani Sinha wrote:
>
>> PCIE root ports and other upstream ports only allow one device on slot 0.
>> When hotplugging a device on a pcie root port, make sure that the device
>> address passed always
On Fri, Jun 19, 2023, Stefan Hajnoczi wrote:
>On Fri, Jun 16, 2023 at 03:58:27PM +0900, Jeuk Kim wrote:
>> This commit adds support for ufs logical unit.
>> The LU handles processing for the SCSI command,
>> unit descriptor query request.
>>
>> This commit enables the UFS device to process
>> IO
Hi Zhenzhong,
On 19/06/2023 11:44, Zhenzhong Duan wrote:
External email: Use caution opening links or attachments
This patch refactors vfio_migration_realize() and its dependend code
as follows:
1. Change vfio_block_*_migration() to be only a checker.
2. It's redundant in
On Fri, Jun 19, 2023, Stefan Hajnoczi wrote:
>On Fri, Jun 16, 2023 at 03:58:25PM +0900, Jeuk Kim wrote:
>> This commit makes the UFS device support query
>> and nop out transfer requests.
>>
>> The next patch would be support for UFS logical
>> unit and scsi command transfer request.
>>
>>
Hi Chris,
On 14/6/23 04:27, Chris Laplante wrote:
Hi all,
I am working on improving nRF51 emulation. Specifically I want to implement the special
"System OFF" mode. System OFF is a power saving mode. In this mode, the system
can only be woken up by a reset or a handful of peripherals (most
On Mon, 12 Jun 2023 at 14:18, Aaron Lindsay
wrote:
>
> On Jun 09 13:49, Richard Henderson wrote:
> > On 6/9/23 10:23, Aaron Lindsay wrote:
> > > --- a/target/arm/hvf/hvf.c
> > > +++ b/target/arm/hvf/hvf.c
> > > @@ -847,6 +847,7 @@ static bool
> > >
On 9/6/23 04:23, Richard Henderson wrote:
This implements the VNCIPHERLAST instruction.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/6/23 04:23, Richard Henderson wrote:
This implements the AESDECLAST instruction.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 9/6/23 04:23, Richard Henderson wrote:
This implements the VCIPHERLAST instruction.
Signed-off-by: Richard Henderson
---
target/ppc/int_helper.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 19/6/23 12:43, Philippe Mathieu-Daudé wrote:
On 9/6/23 04:23, Richard Henderson wrote:
This implements the AESENCLAST instruction.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
void
On 9/6/23 04:23, Richard Henderson wrote:
This implements the AESENCLAST instruction.
Signed-off-by: Richard Henderson
---
target/i386/ops_sse.h | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
void glue(helper_aesenclast, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg
On 9/6/23 04:23, Richard Henderson wrote:
Move the code from tcg/. Fix a bug in that PPC_FEATURE2_ARCH_3_10
is actually spelled PPC_FEATURE2_ARCH_3_1.
This is rather confusing.
Signed-off-by: Richard Henderson
---
host/include/ppc/host/cpuinfo.h | 29
On Thu, 15 Jun 2023 at 15:24, Martin Kaiser wrote:
>
> The Linux kernel added a flood check for RX data recently in commit
> 496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This
> check uses the wake bit in the UART status register 2. The wake bit
> indicates that the receiver
Stefan Hajnoczi 于2023年6月19日周一 18:10写道：
>
> On Mon, Jun 05, 2023 at 06:41:06PM +0800, Sam Li wrote:
> > To configure the zoned format feature on the qcow2 driver, it
> > requires following arguments: the device size, zoned profile,
> > zoned model, zone size, zone capacity, number of conventional
On Wed, 7 Jun 2023 at 10:21, Marcin Juszkiewicz
wrote:
>
> Signed-off-by: Marcin Juszkiewicz
> Reviewed-by: Thomas Huth
>
> ---
> hw/arm/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
Applied to target-arm.next, thanks.
-- PMM
On Wed, 7 Jun 2023 at 08:25, Chen Baozi wrote:
>
>
> > On Jun 7, 2023, at 10:33, Yuquan Wang wrote:
> >
> > The current sbsa-ref cannot use EHCI controller which is only
> > able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB.
> > Hence, this uses system bus XHCI to provide a usb
On Mon, Jun 05, 2023 at 06:41:06PM +0800, Sam Li wrote:
> To configure the zoned format feature on the qcow2 driver, it
> requires following arguments: the device size, zoned profile,
> zoned model, zone size, zone capacity, number of conventional
> zones, limits on zone resources (max append
On Fri, Jun 16, 2023 at 03:58:27PM +0900, Jeuk Kim wrote:
> This commit adds support for ufs logical unit.
> The LU handles processing for the SCSI command,
> unit descriptor query request.
>
> This commit enables the UFS device to process
> IO requests.
Is UFS a SCSI Host Bus Adapter capable of
On Fri, Jun 16, 2023, Stefan Hajnoczi wrote:
>On Fri, Jun 16, 2023 at 03:58:21PM +0900, Jeuk Kim wrote:
>> Universal Flash Storage (UFS) is a high-performance mass storage device
>> with a serial interface. It is primarily used as a high-performance
>> data storage device for embedded
On Fri, 16 Jun 2023 14:10:24 -0400
Gregory Price wrote:
> On Fri, Jun 16, 2023 at 03:43:31PM +0800, Yuquan Wang wrote:
> > Hi, Gregory
> >
> > There is one confusion about CXL in QEMU I hope to consult.
> > If you have some time to look at this email, I would have better
> > understanding of
On Tue, Jun 13, 2023 at 05:58:56PM -0300, Daniel Henrique Barboza wrote:
> There are 2 places in which we need to get a pointer to a certain
> property of the cpu->cfg struct based on property offset. Next patch
> will add a couple more.
>
> Create a helper to avoid repeating this code over and
On Tue, Jun 13, 2023 at 05:58:54PM -0300, Daniel Henrique Barboza wrote:
> The isa_edata_arr[] is used by riscv_isa_string_ext() to create the
> riscv,isa DT attribute. isa_edata_arr[] is kept in sync with the TCG
> property vector riscv_cpu_extensions[], i.e. all TCG properties from
> this vector
*** Expose a multi touch device interface for the UI DBus backend ***
Bilal Elmoussaoui (2):
ui/touch: Move event handling to a common helper
ui/dbus: Expose a touch device interface
include/ui/console.h | 15 ++
ui/console.c | 65
So that clients making use of the DBus backend could
send touch events through the new org.qemu.Display1.Touch
interface
Signed-off-by: Bilal Elmoussaoui
Reviewed-by: Marc-André Lureau
Signed-off-by: Bilal Elmoussaoui
---
ui/dbus-console.c| 59 +++-
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