Re: [PATCH 1/2] vhost-user: fix lost reconnect

On 22 Aug 2023, at 8:38 AM, Raphael Norwitz wrote: On Aug 17, 2023, at 2:40 AM, Li Feng wrote: 2023年8月14日 下午8:11，Raphael Norwitz 写道： Why can’t we rather fix this by adding a “event_cb” param to vhost_user_async_close and then call qemu_chr_fe_set_handlers in vhost_user_async_close_bh()?

Re: [PATCH 2/2] vhost: Add Error parameter to vhost_scsi_common_start()

On 21 Aug 2023, at 8:09 PM, Markus Armbruster wrote: Li Feng writes: 2023年8月14日 下午8:11，Raphael Norwitz 写道： Thanks for the cleanup! A few comments. On Aug 4, 2023, at 1:29 AM, Li Feng wrote: Add a Error parameter to report the real error, like vhost-user-blk. Signed-off-by: Li Feng ---

Re: [RFC v2 PATCH] record-replay: support SMP target machine

On 11.08.2023 04:47, Nicholas Piggin wrote: RR CPU switching is driven by timers and events so it is deterministic like everything else. Record a CPU switch event and use that to drive the CPU switch on replay. Signed-off-by: Nicholas Piggin --- This is still in RFC phase because so far I've

Re: [PATCH v4 10/15] hw/loongarch: Remove restriction of la464 cores in the virt machine

On 8/21/23 20:27, Song Gao wrote: Allow virt machine to be used with la132 instead of la464. Co-authored-by: Jiajie Chen Signed-off-by: Song Gao --- hw/loongarch/virt.c | 5 - 1 file changed, 5 deletions(-) Reviewed-by: Richard Henderson r~

Re: [PATCH v4 09/15] target/loongarch: Add LoongArch32 cpu la132

On 8/21/23 20:27, Song Gao wrote: From: Jiajie Chen Add LoongArch32 cpu la132. Due to lack of public documentation of la132, it is currently a synthetic LoongArch32 cpu model. Details need to be added in the future. Signed-off-by: Jiajie Chen Signed-off-by: Song Gao ---

[PATCH v4 3/9] target/arm: Add feature detection for FEAT_Pauth2 and extensions

From: Aaron Lindsay Rename isar_feature_aa64_pauth_arch to isar_feature_aa64_pauth_qarma5 to distinguish the other architectural algorithm qarma3. Add ARMPauthFeature and isar_feature_pauth_feature to cover the other pauth conditions. Signed-off-by: Aaron Lindsay Message-Id:

[PATCH v4 5/9] target/arm: Implement FEAT_PACQARMA3

Implement the QARMA3 cryptographic algorithm for PAC calculation. Implement a cpu feature to select the algorithm and document it. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20230609172324.982888-4-aa...@os.amperecomputing.com> [rth:

[PATCH v4 8/9] targer/arm: Inform helpers whether a PAC instruction is 'combined'

From: Aaron Lindsay An instruction is a 'combined' Pointer Authentication instruction if it does something in addition to PAC -- for instance, branching to or loading an address from the authenticated pointer. Knowing whether a PAC operation is 'combined' is needed to implement

[PATCH v4 2/9] target/arm: Add ID_AA64ISAR2_EL1

From: Aaron Lindsay Signed-off-by: Aaron Lindsay [PMM: drop the HVF part of the patch and just comment that we need to do something when the register appears in that API] Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 1 +

[PATCH v4 4/9] target/arm: Don't change pauth features when changing algorithm

We have cpu properties to adjust the pauth algorithm for the purpose of speed of emulation. Retain the set of pauth features supported by the cpu even as the algorithm changes. This already affects the neoverse-v1 cpu, which has FEAT_EPAC. Signed-off-by: Richard Henderson ---

[PATCH v4 6/9] target/arm: Implement FEAT_EPAC

From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20230609172324.982888-5-aa...@os.amperecomputing.com> Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c| 2 +-

[PATCH v4 7/9] target/arm: Implement FEAT_Pauth2

From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Message-Id: <20230609172324.982888-6-aa...@os.amperecomputing.com> Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/tcg/cpu64.c| 2 +-

[PATCH v4 0/9] Implement Most ARMv8.3 Pointer Authentication Features

This is an update of Aaron's v3 [1]. There are a fair number of changes beyond a mere rebase: * Updates to the test cases which fail with the new features. * Updates to the documentation. * Preserve pauth feature set when changing pauth algorithm. * Rearrange feature detection: - Add

[PATCH v4 9/9] target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE

From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson Message-Id: <20230609172324.982888-8-aa...@os.amperecomputing.com> [rth: Simplify fpac comparison, reusing cmp_mask] Signed-off-by: Richard Henderson --- docs/system/arm/emulation.rst | 2 ++

[PATCH v4 1/9] tests/tcg/aarch64: Adjust pauth tests for FEAT_FPAC

With FEAT_FPAC, AUT* instructions that fail authentication do not produce an error value but instead fault. For pauth-2, install a signal handler and verify it gets called. For pauth-4 and pauth-5, we are explicitly testing the error value, so there's nothing to test with FEAT_FPAC, so exit

Re: [PATCH v3 0/8] target/loongarch: Cleanups in preparation of loongarch32 support

在 2023/8/21 下午8:59, Philippe Mathieu-Daudé 写道: Series fully reviewed. v3: - Do not rename loongarch_la464_initfn (rth) - Added R-b v2: - Do no rename loongarch_cpu_get/set_pc (rth) - Rebased Jiajie's patches for convenience - Added rth's R-b Jiajie, this series contains few notes I took while

[PATCH v4 05/15] target/loongarch: Truncate high 32 bits of address in VA32 mode

From: Jiajie Chen When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by: Jiajie Chen Co-authored-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/cpu.h

[PATCH v4 06/15] target/loongarch: Sign extend results in VA32 mode

From: Jiajie Chen In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/translate.c | 8

[PATCH v4 01/15] target/loongarch: Support LoongArch32 TLB entry

From: Jiajie Chen The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h| 9 + target/loongarch/tlb_helper.c | 17

[PATCH v4 04/15] target/loongarch: Add LA64 & VA32 to DisasContext

From: Jiajie Chen Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/cpu.h | 13

[PATCH v4 00/15] Add some checks before translating instructions

Based-on: https://patchew.org/QEMU/20230821125959.28666-1-phi...@linaro.org/ Hi, This series adds some checks before translating instructions This includes: CPUCFG[1].IOCSR CPUCFG[2].FP CPUCFG[2].FP_SP CPUCFG[2].FP_DP CPUCFG[2].LSPW CPUCFG[2].LAM CPUCFG[2].LSX And this series adds [1]

[PATCH v4 08/15] target/loongarch: Add avail_64 to check la64-only instructions

The la32 instructions listed in Table 2 at https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Co-authored-by: Jiajie Chen Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/translate.h | 3

[PATCH v4 07/15] target/loongarch: Add a check parameter to the TRANS macro

The default check parmeter is ALL. Suggested-by: Richard Henderson Signed-off-by: Song Gao Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/loongarch/translate.h |6 +- target/loongarch/insn_trans/trans_arith.c.inc | 84 +-

[PATCH v4 03/15] target/loongarch: Support LoongArch32 VPPN

From: Jiajie Chen VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h| 6 -- target/loongarch/tlb_helper.c | 23 ++- 2 files changed, 22

[PATCH v4 12/15] target/loongarch: Add avail_LSPW to check LSPW instructions

Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/translate.h | 1 + target/loongarch/insn_trans/trans_privileged.c.inc | 8 2 files changed, 9 insertions(+) diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index

[PATCH v4 14/15] target/loongarch: Add avail_LSX to check LSX instructions

Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/translate.h|2 + target/loongarch/insn_trans/trans_lsx.c.inc | 1482 ++- 2 files changed, 823 insertions(+), 661 deletions(-) diff --git a/target/loongarch/translate.h

[PATCH v4 10/15] hw/loongarch: Remove restriction of la464 cores in the virt machine

Allow virt machine to be used with la132 instead of la464. Co-authored-by: Jiajie Chen Signed-off-by: Song Gao --- hw/loongarch/virt.c | 5 - 1 file changed, 5 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index e19b042ce8..af15bf5aaa 100644 --- a/hw/loongarch/virt.c

[PATCH v4 13/15] target/loongarch: Add avail_LAM to check atomic instructions

Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/translate.h | 1 + .../loongarch/insn_trans/trans_atomic.c.inc | 72 +-- 2 files changed, 37 insertions(+), 36 deletions(-) diff --git a/target/loongarch/translate.h

[PATCH v4 02/15] target/loongarch: Support LoongArch32 DMW

From: Jiajie Chen LA32 uses a different encoding for CSR.DMW and a new direct mapping mechanism. Signed-off-by: Jiajie Chen Reviewed-by: Richard Henderson Signed-off-by: Song Gao --- target/loongarch/cpu-csr.h| 7 +++ target/loongarch/tlb_helper.c | 26 +++--- 2

[PATCH v4 09/15] target/loongarch: Add LoongArch32 cpu la132

From: Jiajie Chen Add LoongArch32 cpu la132. Due to lack of public documentation of la132, it is currently a synthetic LoongArch32 cpu model. Details need to be added in the future. Signed-off-by: Jiajie Chen Signed-off-by: Song Gao --- target/loongarch/cpu.c | 30

[PATCH v4 15/15] target/loongarch: Add avail_IOCSR to check iocsr instructions

Signed-off-by: Song Gao Reviewed-by: Richard Henderson --- target/loongarch/translate.h | 2 +- .../loongarch/insn_trans/trans_privileged.c.inc | 16 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/loongarch/translate.h

[PATCH v4 11/15] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions

Signed-off-by: Song Gao Acked-by: Richard Henderson --- target/loongarch/translate.h | 4 + target/loongarch/translate.c | 1 + .../loongarch/insn_trans/trans_farith.c.inc | 96 --- target/loongarch/insn_trans/trans_fcmp.c.inc | 8 ++

Re: [PATCH] hw/loongarch: Fix ACPI processor id off-by-one error

在 2023/8/21 09:29, Jiajie Chen 写道: > > On 2023/8/21 09:24, bibo mao wrote: >> + Add xianglai >> >> Good catch. >> >> In theory, it is logical id, and it can be not equal to physical id. >> However it must be equal to _UID in cpu dsdt table which is missing >> now. > > Yes, the logical id can

Re: [PATCH 1/2] vhost-user: fix lost reconnect

> On Aug 17, 2023, at 2:40 AM, Li Feng wrote: > > >> 2023年8月14日 下午8:11，Raphael Norwitz 写道： >> >> Why can’t we rather fix this by adding a “event_cb” param to >> vhost_user_async_close and then call qemu_chr_fe_set_handlers in >> vhost_user_async_close_bh()? >> >> Even if calling

Re: [PATCH v7 9/9] docs/system: add basic virtio-gpu documentation

On Fri, Aug 18, 2023 at 11:13 PM Akihiko Odaki wrote: > On 2023/08/19 10:17, Gurchetan Singh wrote: > > > > > > On Fri, Aug 18, 2023 at 5:08 AM Akihiko Odaki > > wrote: > > > > On 2023/08/18 8:47, Gurchetan Singh wrote: > > > > > > > > > On

[PATCH v10 6/9] gfxstream + rutabaga: add initial support for gfxstream

This adds initial support for gfxstream and cross-domain. Both features rely on virtio-gpu blob resources and context types, which are also implemented in this patch. gfxstream has a long and illustrious history in Android graphics paravirtualization. It has been powering graphics in the

[PATCH v10 2/9] virtio-gpu: CONTEXT_INIT feature

From: Antonio Caggiano The feature can be enabled when a backend wants it. Signed-off-by: Antonio Caggiano Reviewed-by: Marc-André Lureau Signed-off-by: Gurchetan Singh Tested-by: Alyssa Ross Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Akihiko Odaki --- hw/display/virtio-gpu-base.c

[PATCH v10 1/9] virtio: Add shared memory capability

From: "Dr. David Alan Gilbert" Define a new capability type 'VIRTIO_PCI_CAP_SHARED_MEMORY_CFG' to allow defining shared memory regions with sizes and offsets of 2^32 and more. Multiple instances of the capability are allowed and distinguished by a device-specific 'id'. Signed-off-by: Dr. David

[PATCH v10 7/9] gfxstream + rutabaga: meson support

- Add meson detection of rutabaga_gfx - Build virtio-gpu-rutabaga.c + associated vga/pci files when present Signed-off-by: Gurchetan Singh Tested-by: Alyssa Ross Tested-by: Emmanouil Pitsidianakis Reviewed-by: Emmanouil Pitsidianakis --- v3: Fix alignment issues (Akihiko)

[PATCH v10 5/9] gfxstream + rutabaga prep: added need defintions, fields, and options

This modifies the common virtio-gpu.h file have the fields and defintions needed by gfxstream/rutabaga, by VirtioGpuRutabaga. Signed-off-by: Gurchetan Singh Tested-by: Alyssa Ross Tested-by: Emmanouil Pitsidianakis Reviewed-by: Emmanouil Pitsidianakis --- v1: void *rutabaga --> struct

[PATCH v10 9/9] docs/system: add basic virtio-gpu documentation

This adds basic documentation for virtio-gpu. Suggested-by: Akihiko Odaki Signed-off-by: Gurchetan Singh Tested-by: Alyssa Ross Tested-by: Emmanouil Pitsidianakis Reviewed-by: Emmanouil Pitsidianakis --- v2: - Incorporated suggestions by Akihiko Odaki - Listed the currently supported

[PATCH v10 3/9] virtio-gpu: hostmem

From: Gerd Hoffmann Use VIRTIO_GPU_SHM_ID_HOST_VISIBLE as id for virtio-gpu. Signed-off-by: Antonio Caggiano Tested-by: Alyssa Ross Acked-by: Michael S. Tsirkin --- hw/display/virtio-gpu-pci.c| 14 ++ hw/display/virtio-gpu.c| 1 + hw/display/virtio-vga.c| 33

[PATCH v10 8/9] gfxstream + rutabaga: enable rutabaga

This change enables rutabaga to receive virtio-gpu-3d hypercalls when it is active. Signed-off-by: Gurchetan Singh Tested-by: Alyssa Ross Tested-by: Emmanouil Pitsidianakis Reviewed-by: Emmanouil Pitsidianakis --- v3: Whitespace fix (Akihiko) v9: reorder virtio_gpu_have_udmabuf() after

[PATCH v10 4/9] virtio-gpu: blob prep

From: Antonio Caggiano This adds preparatory functions needed to: - decode blob cmds - tracking iovecs Signed-off-by: Antonio Caggiano Signed-off-by: Dmitry Osipenko Signed-off-by: Gurchetan Singh Tested-by: Alyssa Ross Tested-by: Emmanouil Pitsidianakis Reviewed-by: Emmanouil

Re: [PATCH v2 32/58] i386/tdx: Track RAM entries for TDX VM

On Fri, Aug 18, 2023 at 05:50:15AM -0400, Xiaoyao Li wrote: > diff --git a/target/i386/kvm/tdx.h b/target/i386/kvm/tdx.h > index e9d2888162ce..9b3c427766ef 100644 > --- a/target/i386/kvm/tdx.h > +++ b/target/i386/kvm/tdx.h > @@ -15,6 +15,17 @@ typedef struct TdxGuestClass { >

Re: [PATCH v2 19/58] qom: implement property helper for sha384

On Mon, Aug 21, 2023 at 10:25:35AM +0100, "Daniel P. Berrangé" wrote: > On Fri, Aug 18, 2023 at 05:50:02AM -0400, Xiaoyao Li wrote: > > From: Isaku Yamahata > > > > Implement property_add_sha384() which converts hex string <-> uint8_t[48] > > It will be used for TDX which uses sha384 for

Re: [PATCH v2 08/58] i386/tdx: Adjust the supported CPUID based on TDX restrictions

On Fri, Aug 18, 2023 at 05:49:51AM -0400, Xiaoyao Li wrote: > diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c > index 56cb826f6125..3198bc9fd5fb 100644 > --- a/target/i386/kvm/tdx.c > +++ b/target/i386/kvm/tdx.c ... > +static inline uint32_t host_cpuid_reg(uint32_t function, > +

virtio queue numbering and optional queues

Hello virtio folks, I noticed a mismatch between the way the specification defines device-specific virtqueue indexes and the way device and driver implementers have interpreted the specification. As a practical example, consider the traditional memory balloon device [1]. The first two queues

Re: [PATCH v2 45/58] i386/tdx: Limit the range size for MapGPA

On Fri, Aug 18, 2023 at 05:50:28AM -0400, Xiaoyao Li wrote: > From: Isaku Yamahata > > If the range for TDG.VP.VMCALL is too large, process the limited > size and return retry error. It's bad for VMM to take too long time, > e.g. second order, with blocking vcpu execution. It results in too

Re: [PATCH v6 00/12] Add VIRTIO sound card

Am 21.08.23 um 08:10 schrieb Manos Pitsidianakis: Hello Volker, On Sun, 20 Aug 2023 14:46, Volker Rümelin wrote: I tested the virtio-sound-pci device. It seems the device works unreliably. Audio playback has a lot of dropouts. I can actually hear my mouse moving around. Audio recording with

trace_exec_tb(tb, pc) does not have cpu index

Hi. I am wondering why trace events like trace_exec_tb(tb, pc) do not have cpu index, how to make sense of the trace in case of multiple vCPUs? I have changed it to trace_exec_tb(tb, pc, cpu->cpu_index) to read my trace, and now wondering should not it be there by default? Am I missing

Re: [PATCH 0/2] block-backend: process I/O in the current AioContext

On Fri, Aug 18, 2023 at 05:24:22PM +0200, Kevin Wolf wrote: > Am 15.08.2023 um 18:05 hat Stefan Hajnoczi geschrieben: > > Switch blk_aio_*() APIs over to multi-queue by using > > qemu_get_current_aio_context() instead of blk_get_aio_context(). This change > > will allow devices to process I/O in

Re: [PATCH v2] target/riscv: Update CSR bits name for svadu extension

On Wed, Aug 16, 2023 at 10:20 AM Weiwei Li wrote: > > The Svadu specification updated the name of the *envcfg bit from > HADE to ADUE. > > Signed-off-by: Weiwei Li > Signed-off-by: Junqiang Wang Thanks! Applied to riscv-to-apply.next Alistair > --- > > v2: > * rename hade variable name to

Re: [PATCH 2/3] hw/char: riscv_htif: replace exit(0) with proper shutdown

On Fri, Aug 18, 2023 at 5:03 AM Clément Chigot wrote: > > This replaces the exit(0) call by a shutdown request, ensuring a proper > cleanup of Qemu. Otherwise, some connections like gdb could be broken > without being correctly flushed. > > Signed-off-by: Clément Chigot Reviewed-by: Alistair

Re: [PATCH 1/3] hw/misc/sifive_test.c: replace exit(0) with proper shutdown

On Fri, Aug 18, 2023 at 5:03 AM Clément Chigot wrote: > > This replaces the exit(0) call by a shutdown request, ensuring a proper > cleanup of Qemu. Otherwise, some connections like gdb could be broken > without being correctly flushed. > > Signed-off-by: Clément Chigot Reviewed-by: Alistair

Re: [PATCH v6 01/12] Add virtio-sound device stub

Am 21.08.23 um 08:06 schrieb Manos Pitsidianakis: Hello Volker! On Sun, 20 Aug 2023 12:33, Volker Rümelin wrote: I think the virtio-snd.c code, the trace events and the Kconfig VIRTIO_SND should be moved to hw/audio. The code for nearly all audio devices is in this directory. This would be

Re: [PATCH v3 00/19] crypto: Provide clmul.h and host accel

On 8/21/23 11:08, Ard Biesheuvel wrote: OK, I did the OpenSSL benchmark this time, using a x86_64 cross build on arm64/ThunderX2, and the speedup is 7x (\o/) Excellent, thanks. r~

Re: [PATCH v3 00/19] crypto: Provide clmul.h and host accel

On Mon, 21 Aug 2023 at 18:18, Richard Henderson wrote: > > Inspired by Ard Biesheuvel's RFC patches [1] for accelerating > carry-less multiply under emulation. > > Changes for v3: > * Update target/i386 ops_sse.h. > * Apply r-b. > > Changes for v2: > * Only accelerate clmul_64; keep generic

Re: [PATCH 2/2] hw/intc: Make rtc variable names consistent

On Mon, Aug 21, 2023 at 12:15 PM Jason Chien wrote: > > Ping. This has been applied to the RISC-V tree. It will go in after the QEMU release freeze is over (probably a week or two). Alistair > > On Fri, Aug 11, 2023 at 2:25 AM Alistair Francis wrote: >> >> On Fri, Jul 28, 2023 at 4:57 AM

Re: [PATCH v3 19/19] host/include/aarch64: Implement clmul.h

On 21/8/23 18:18, Richard Henderson wrote: Detect PMULL in cpuinfo; implement the accel hook. Signed-off-by: Richard Henderson --- host/include/aarch64/host/cpuinfo.h | 1 + host/include/aarch64/host/crypto/clmul.h | 41 util/cpuinfo-aarch64.c

Re: [PATCH v3 15/19] target/i386: Use clmul_64

On 21/8/23 18:18, Richard Henderson wrote: Use generic routine for 64-bit carry-less multiply. Signed-off-by: Richard Henderson --- target/i386/ops_sse.h | 40 +--- 1 file changed, 9 insertions(+), 31 deletions(-) Reviewed-by: Philippe Mathieu-Daudé

Re: [PATCH v5 4/5] qmp: Added new command to retrieve eBPF blob.

Andrew Melnichenko writes: > Hi all, > Thanks for the comments - I'll update and send new patches. > > On Sat, Aug 5, 2023 at 10:34 AM Markus Armbruster wrote: >> >> Andrew Melnychenko writes: >> >> > Now, the binary objects may be retrieved by id. >> > It would require for future qmp commands

Re: [PATCH 05/21] block: Introduce bdrv_schedule_unref()

Am 18.08.2023 um 18:26 hat Eric Blake geschrieben: > On Fri, Aug 18, 2023 at 11:24:00AM -0500, Eric Blake wrote: > > > +++ b/block/graph-lock.c > > > @@ -163,17 +163,26 @@ void bdrv_graph_wrlock(BlockDriverState *bs) > > > void bdrv_graph_wrunlock(void) > > > { > > > GLOBAL_STATE_CODE(); >

Re: [PATCH v10 00/10] migration: Modify 'migrate' and 'migrate-incoming' QAPI commands for migration

Het, On Mon, Aug 21, 2023 at 11:43:02AM +0530, Het Gala wrote: > Hi qemu-devel community, > > A gentle reminder and request for all migration maintainers - Peter, Juan, > Dr. Gilbert and others too for review of the patchset series. Received > reviewed-by from Daniel on migration implementation

[PATCH v3 02/19] target/arm: Use clmul_8* routines

Use generic routines for 8-bit carry-less multiply. Remove our local version of pmull_h. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/vec_internal.h | 5 target/arm/tcg/mve_helper.c | 8 ++ target/arm/tcg/vec_helper.c | 53

[PATCH v3 18/19] host/include/i386: Implement clmul.h

Detect PCLMUL in cpuinfo; implement the accel hook. Signed-off-by: Richard Henderson --- host/include/i386/host/cpuinfo.h| 1 + host/include/i386/host/crypto/clmul.h | 29 + host/include/x86_64/host/crypto/clmul.h | 1 + include/qemu/cpuid.h

[PATCH v3 17/19] target/ppc: Use clmul_64

Use generic routine for 64-bit carry-less multiply. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/int_helper.c | 17 +++-- 1 file changed, 3 insertions(+), 14 deletions(-) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index

[PATCH v3 12/19] target/ppc: Use clmul_32* routines

Use generic routines for 32-bit carry-less multiply. Signed-off-by: Richard Henderson --- target/ppc/int_helper.c | 26 ++ 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 10e19d8c9b..ce793cf163 100644

[PATCH v3 15/19] target/i386: Use clmul_64

Use generic routine for 64-bit carry-less multiply. Signed-off-by: Richard Henderson --- target/i386/ops_sse.h | 40 +--- 1 file changed, 9 insertions(+), 31 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index a0e425733f..33908c0691

[PATCH v3 16/19] target/s390x: Use clmul_64

Use the generic routine for 64-bit carry-less multiply. Remove our local version of galois_multiply64. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/vec_int_helper.c | 58 +++ 1 file changed, 12 insertions(+), 46

[PATCH v3 19/19] host/include/aarch64: Implement clmul.h

Detect PMULL in cpuinfo; implement the accel hook. Signed-off-by: Richard Henderson --- host/include/aarch64/host/cpuinfo.h | 1 + host/include/aarch64/host/crypto/clmul.h | 41 util/cpuinfo-aarch64.c | 4 ++- 3 files changed, 45 insertions(+),

[PATCH v3 07/19] target/s390x: Use clmul_16* routines

Use generic routines for 16-bit carry-less multiply. Remove our local version of galois_multiply16. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/vec_int_helper.c | 27 --- 1 file changed, 24 insertions(+), 3 deletions(-)

[PATCH v3 09/19] crypto: Add generic 32-bit carry-less multiply routines

Signed-off-by: Richard Henderson --- include/crypto/clmul.h | 7 +++ crypto/clmul.c | 13 + 2 files changed, 20 insertions(+) diff --git a/include/crypto/clmul.h b/include/crypto/clmul.h index c7ad28aa85..0ea25a252c 100644 --- a/include/crypto/clmul.h +++

[PATCH v3 05/19] crypto: Add generic 16-bit carry-less multiply routines

Signed-off-by: Richard Henderson --- include/crypto/clmul.h | 16 crypto/clmul.c | 21 + 2 files changed, 37 insertions(+) diff --git a/include/crypto/clmul.h b/include/crypto/clmul.h index 153b5e3057..c7ad28aa85 100644 --- a/include/crypto/clmul.h

[PATCH v3 08/19] target/ppc: Use clmul_16* routines

Use generic routines for 16-bit carry-less multiply. Signed-off-by: Richard Henderson --- target/ppc/int_helper.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 343874863a..10e19d8c9b 100644 ---

[PATCH v3 13/19] crypto: Add generic 64-bit carry-less multiply routine

Signed-off-by: Richard Henderson --- host/include/generic/host/crypto/clmul.h | 15 +++ include/crypto/clmul.h | 19 +++ crypto/clmul.c | 18 ++ 3 files changed, 52 insertions(+) create mode 100644

[PATCH v3 06/19] target/arm: Use clmul_16* routines

Use generic routines for 16-bit carry-less multiply. Remove our local version of pmull_w. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/vec_internal.h | 6 -- target/arm/tcg/mve_helper.c | 8 ++-- target/arm/tcg/vec_helper.c | 13

[PATCH v3 14/19] target/arm: Use clmul_64

Use generic routine for 64-bit carry-less multiply. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 22 -- 1 file changed, 4 insertions(+), 18 deletions(-) diff --git a/target/arm/tcg/vec_helper.c

[PATCH v3 10/19] target/arm: Use clmul_32* routines

Use generic routines for 32-bit carry-less multiply. Remove our local version of pmull_d. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/vec_helper.c | 14 +- 1 file changed, 1 insertion(+), 13 deletions(-) diff --git

[PATCH v3 03/19] target/s390x: Use clmul_8* routines

Use generic routines for 8-bit carry-less multiply. Remove our local version of galois_multiply8. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/vec_int_helper.c | 32 --- 1 file changed, 29 insertions(+), 3 deletions(-)

[PATCH v3 04/19] target/ppc: Use clmul_8* routines

Use generic routines for 8-bit carry-less multiply. Signed-off-by: Richard Henderson --- target/ppc/int_helper.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 834da80fe3..343874863a 100644 ---

[PATCH v3 11/19] target/s390x: Use clmul_32* routines

Use generic routines for 32-bit carry-less multiply. Remove our local version of galois_multiply32. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/tcg/vec_int_helper.c | 75 +-- 1 file changed, 22 insertions(+), 53 deletions(-)

[PATCH v3 00/19] crypto: Provide clmul.h and host accel

Inspired by Ard Biesheuvel's RFC patches [1] for accelerating carry-less multiply under emulation. Changes for v3: * Update target/i386 ops_sse.h. * Apply r-b. Changes for v2: * Only accelerate clmul_64; keep generic helpers for other sizes. * Drop most of the Int128 interfaces, except

[PATCH v3 01/19] crypto: Add generic 8-bit carry-less multiply routines

Signed-off-by: Richard Henderson --- include/crypto/clmul.h | 41 + crypto/clmul.c | 60 ++ crypto/meson.build | 9 --- 3 files changed, 107 insertions(+), 3 deletions(-) create mode 100644

Re: [PATCH 2/2] hw/intc: Make rtc variable names consistent

Ping. On Fri, Aug 11, 2023 at 2:25 AM Alistair Francis wrote: > On Fri, Jul 28, 2023 at 4:57 AM Jason Chien > wrote: > > > > The variables whose values are given by cpu_riscv_read_rtc() should be > named > > "rtc". The variables whose value are given by cpu_riscv_read_rtc_raw() > > should be

Re: [8.1 regression] Re: [PULL 05/19] virtio-gpu-udmabuf: correct naming of QemuDmaBuf size properties

On Mon, 21 Aug 2023 14:20:38 +0400 Marc-André Lureau wrote: > Hi Alex > > On Thu, Aug 17, 2023 at 1:25 AM Alex Williamson > wrote: > > > > On Wed, 16 Aug 2023 15:08:10 -0600 > > Alex Williamson wrote: > > > > diff --git a/ui/egl-helpers.c b/ui/egl-helpers.c > > > > index

Re: Funny results with long double denorms on m68k

> When I developped the FPU emulation I compared the result of QEMU and a real > hardware using > https://github.com/vivier/m68k-testfloat and > https://github.com/vivier/m68k-softfloat It looks like the second of those has similar issues with m68k denorms?

Re: [PATCH v2 00/18] crypto: Provide clmul.h and host accel

On Mon, 21 Aug 2023 at 17:15, Richard Henderson wrote: > > On 8/21/23 07:57, Ard Biesheuvel wrote: > >> Richard Henderson (18): > >>crypto: Add generic 8-bit carry-less multiply routines > >>target/arm: Use clmul_8* routines > >>target/s390x: Use clmul_8* routines > >>target/ppc:

Re: [PATCH] target/ppc: Fix LQ, STQ register-pair order for big-endian

On 8/21/23 08:30, Nicholas Piggin wrote: LQ, STQ have the same register-pair ordering as LQARX/STQARX., which is the even (lower) register contains the most significant bits. This is not implemented correctly for big-endian. do_ldst_quad() has variables low_addr_gpr and high_addr_gpr which is

[PATCH] target/ppc: Fix LQ, STQ register-pair order for big-endian

LQ, STQ have the same register-pair ordering as LQARX/STQARX., which is the even (lower) register contains the most significant bits. This is not implemented correctly for big-endian. do_ldst_quad() has variables low_addr_gpr and high_addr_gpr which is confusing because they are low and high

Re: [RFC PATCH] target/arm: properly document FEAT_CRC32

On Wed, 22 Feb 2023 at 11:01, Alex Bennée wrote: > > This is a mandatory feature for Armv8.1 architectures but we don't > state the feature clearly in our emulation list. While checking verify > our cortex-a76 model matches up with the current TRM by breaking out > the long form isar into a more

Re: [PATCH v2 00/18] crypto: Provide clmul.h and host accel

On 8/21/23 07:57, Ard Biesheuvel wrote: Richard Henderson (18): crypto: Add generic 8-bit carry-less multiply routines target/arm: Use clmul_8* routines target/s390x: Use clmul_8* routines target/ppc: Use clmul_8* routines crypto: Add generic 16-bit carry-less multiply routines

Re: [PATCH v2 00/18] crypto: Provide clmul.h and host accel

On Sat, 19 Aug 2023 at 03:02, Richard Henderson wrote: > > Inspired by Ard Biesheuvel's RFC patches [1] for accelerating > carry-less multiply under emulation. > > Changes for v2: > * Only accelerate clmul_64; keep generic helpers for other sizes. > * Drop most of the Int128 interfaces,

Re: about QEMU TLS

Hello Daniel, sorry for my slow reply! I tested the approach you suggested by the following way: On the target server, start a VM in -incoming mode: qemu-7.1 \ -uuid ${VM_UUID} \ ... -object tls-creds-x509,id=tls0,dir=${HOME}/qemutls,endpoint=server \ ... -incoming defer \ -qmp

Re: [PATCH v2 03/58] target/i386: Parse TDX vm type

On 8/21/2023 4:27 PM, Daniel P. Berrangé wrote: On Fri, Aug 18, 2023 at 05:49:46AM -0400, Xiaoyao Li wrote: TDX VM requires VM type KVM_X86_TDX_VM to be passed to kvm_ioctl(KVM_CREATE_VM). If tdx-guest object is specified to confidential-guest-support, like, qemu -machine

Re: [PATCH v2 5/8] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG

On Thu, 10 Aug 2023 at 20:16, Francisco Iglesias wrote: > > Introduce a model of Xilinx Versal's Configuration Frame controller > (CFRAME_REG). > > Signed-off-by: Francisco Iglesias > --- > MAINTAINERS | 2 + > hw/misc/meson.build | 1 + >

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

On Mon, Aug 14, 2023 at 04:58:00PM +0800, Sam Li wrote: > diff --git a/block/qcow2.h b/block/qcow2.h > index f789ce3ae0..3694c8d217 100644 > --- a/block/qcow2.h > +++ b/block/qcow2.h > @@ -236,6 +236,20 @@ typedef struct Qcow2CryptoHeaderExtension { > uint64_t length; > } QEMU_PACKED

Re: [RFC 2/5] qcow2: add zone device metadata with zd_extension

Sam Li writes: > Zone descriptor data is host definied data that is associated with > each zone. Add zone descriptor extensions to zonedmeta and > blk_get_zone_extension to access zd_extensions. > > Signed-off-by: Sam Li [...] > diff --git a/qapi/block-core.json b/qapi/block-core.json > index

Re: [PATCH v2 2/4] qcow2: add configurations for zoned format extension

Sam Li writes: > To configure the zoned format feature on the qcow2 driver, it > requires following arguments: the device size, zoned profile, > zoned model, zone size, zone capacity, number of conventional > zones, limits on zone resources (max append sectors, max open > zones, and

[PATCH v3 5/8] target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_init

Extract loongarch64 specific code from loongarch_cpu_class_init() to a new loongarch64_cpu_class_init(). In preparation of supporting loongarch32 cores, rename these functions using the '64' suffix. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé ---

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