[PATCH v2 15/23] bsd-user: Implement mlock(2), munlock(2), mlockall(2), munlockall(2), minherit(2)

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Richard Henderson --- bsd-user/bsd-mem.h| 37 +++ bsd-user/freebsd/os-syscall.c | 20 +++ 2 files changed, 57 insertions(+) diff --git

[PATCH v2 07/23] bsd-user: Add bsd-mem.c to meson.build

Signed-off-by: Karim Taha Reviewed-by: Richard Henderson Reviewed-by: Warner Losh --- bsd-user/bsd-mem.c | 0 bsd-user/meson.build | 1 + 2 files changed, 1 insertion(+) create mode 100644 bsd-user/bsd-mem.c diff --git a/bsd-user/bsd-mem.c b/bsd-user/bsd-mem.c new file mode 100644 index

[PATCH v2 12/23] bsd-user: Implement mmap(2) and munmap(2)

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/bsd-mem.h| 20 bsd-user/freebsd/os-syscall.c | 9 + 2 files changed, 29 insertions(+) diff --git

[PATCH v2 18/23] bsd-user: Implement do_obreak function

From: Stacey Son Match linux-user, by manually applying the following commits, in order: d28b3c90cfad1a7e211ae2bce36ecb9071086129 linux-user: Make sure initial brk(0) is page-aligned 15ad98536ad9410fb32ddf1ff09389b677643faa linux-user: Fix qemu brk() to not zero bytes on current page

[PATCH v2 13/23] bsd-user: Implement mprotect(2)

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Richard Henderson Reviewed-by: Warner Losh --- bsd-user/bsd-mem.h| 7 +++ bsd-user/freebsd/os-syscall.c | 4 2 files changed, 11 insertions(+) diff --git a/bsd-user/bsd-mem.h

[PATCH v2 21/23] bsd-user: Implement shmctl(2)

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Warner Losh --- bsd-user/bsd-mem.h| 33 + bsd-user/freebsd/os-syscall.c | 4 2 files changed, 37 insertions(+) diff --git a/bsd-user/bsd-mem.h

[PATCH v2 02/23] bsd-user: Implement struct target_shmid_ds

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Richard Henderson Reviewed-by: Warner Losh --- bsd-user/syscall_defs.h | 20 1 file changed, 20 insertions(+) diff --git a/bsd-user/syscall_defs.h b/bsd-user/syscall_defs.h index

[PATCH v2 14/23] bsd-user: Implement msync(2)

From: Stacey Son Co-authored-by: Kyle Evans Signed-off-by: Stacey Son Signed-off-by: Kyle Evans Signed-off-by: Karim Taha Reviewed-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/bsd-mem.h| 11 +++ bsd-user/freebsd/os-syscall.c | 4 2 files changed,

[PATCH v2 11/23] bsd-user: Introduce bsd-mem.h to the source tree

From: Stacey Son Preserve the copyright notice and help with the 'Author' info for subsequent changes to the file. Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/bsd-mem.h| 64

[PATCH v2 03/23] bsd-user: Declarations for ipc_perm and shmid_ds conversion functions

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Richard Henderson Reviewed-by: Warner Losh --- bsd-user/qemu-bsd.h | 45 + 1 file changed, 45 insertions(+) create mode 100644 bsd-user/qemu-bsd.h diff --git

[PATCH v2 01/23] bsd-user: Implement struct target_ipc_perm

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Richard Henderson Reviewed-by: Warner Losh --- bsd-user/syscall_defs.h | 17 + 1 file changed, 17 insertions(+) diff --git a/bsd-user/syscall_defs.h b/bsd-user/syscall_defs.h index

[PATCH v2 10/23] bsd-user: Implement shmid_ds conversion between host and target.

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha --- bsd-user/bsd-mem.c | 43 +++ 1 file changed, 43 insertions(+) diff --git a/bsd-user/bsd-mem.c b/bsd-user/bsd-mem.c index 46cda8eb5c..eea499a727 100644 --- a/bsd-user/bsd-mem.c +++

[PATCH v2 17/23] bsd-user: Implement mincore(2)

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha --- bsd-user/bsd-mem.h| 22 ++ bsd-user/freebsd/os-syscall.c | 4 2 files changed, 26 insertions(+) diff --git a/bsd-user/bsd-mem.h b/bsd-user/bsd-mem.h index 0e16051418..1dabbe36e6

[PATCH v2 22/23] bsd-user: Implement shmat(2) and shmdt(2)

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha --- bsd-user/bsd-mem.h| 76 +++ bsd-user/freebsd/os-syscall.c | 8 2 files changed, 84 insertions(+) diff --git a/bsd-user/bsd-mem.h b/bsd-user/bsd-mem.h index

[PATCH v2 16/23] bsd-user: Implment madvise(2) to match the linux-user implementation.

Signed-off-by: Signed-off-by: Karim Taha --- bsd-user/bsd-mem.h| 53 +++ bsd-user/freebsd/os-syscall.c | 4 +++ bsd-user/syscall_defs.h | 2 ++ 3 files changed, 59 insertions(+) diff --git a/bsd-user/bsd-mem.h b/bsd-user/bsd-mem.h index

[PATCH v2 23/23] bsd-user: Add stubs for vadvise(), sbrk() and sstk()

From: Warner Losh The above system calls are not supported by qemu. Signed-off-by: Warner Losh Signed-off-by: Karim Taha --- bsd-user/bsd-mem.h| 18 ++ bsd-user/freebsd/os-syscall.c | 12 2 files changed, 30 insertions(+) diff --git

[PATCH v2 00/23] bsd-user: Implement mmap related system calls for FreeBSD.

Upstream the implementation of the following mmap system calls, from the qemu-bsd-user fork: mmap(2), munmap(2), mprotect(2), msync(2), mlock(2), munlock(2), mlockall(2), munlockall(2), mincore(2), madvise(2), minherit(2), shm_open(2),shm_open2(2), shm_rename2(2),

[PATCH v2 08/23] bsd-user: Implement target_set_brk function in bsd-mem.c instead of os-syscall.c

From: Stacey Son The definitions and variables names matches the corresponding ones in linux-user/syscall.c, for making later implementation of do_obreak easier Co-authored-by: Mikaël Urankar Signed-off-by: Mikaël Urankar Signed-off-by: Karim Taha Reviewed-by: Warner Losh Reviewed-by:

[PATCH v2 09/23] bsd-user: Implement ipc_perm conversion between host and target.

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Richard Henderson --- bsd-user/bsd-mem.c | 25 + 1 file changed, 25 insertions(+) diff --git a/bsd-user/bsd-mem.c b/bsd-user/bsd-mem.c index 8834ab2e58..46cda8eb5c 100644 ---

[PATCH v2 04/23] bsd-user: Introduce freebsd/os-misc.h to the source tree

From: Stacey Son To preserve the copyright notice and help with the 'Author' info for subsequent changes to the file. Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Richard Henderson Reviewed-by: Warner Losh --- bsd-user/freebsd/os-misc.h | 28

[PATCH v2 06/23] bsd-user: Implement shm_rename(2) system call

From: Kyle Evans Signed-off-by: Kyle Evans Signed-off-by: Karim Taha Reviewed-by: Richard Henderson Reviewed-by: Warner Losh --- bsd-user/freebsd/os-misc.h| 24 bsd-user/freebsd/os-syscall.c | 6 ++ 2 files changed, 30 insertions(+) diff --git

[PATCH v2 19/23] bsd-user: Implement shm_open(2)

From: Stacey Son Co-authored-by: Kyle Evans Signed-off-by: Stacey Son Signed-off-by: Kyle Evans Signed-off-by: Karim Taha --- bsd-user/bsd-mem.h| 25 + bsd-user/freebsd/os-syscall.c | 4 2 files changed, 29 insertions(+) diff --git

[PATCH v2 20/23] bsd-user: Implement shm_unlink(2) and shmget(2)

From: Stacey Son Signed-off-by: Stacey Son Signed-off-by: Karim Taha Reviewed-by: Warner Losh Reviewed-by: Richard Henderson --- bsd-user/bsd-mem.h| 23 +++ bsd-user/freebsd/os-syscall.c | 8 2 files changed, 31 insertions(+) diff --git

[PATCH v2 05/23] bsd-user: Implement shm_open2(2) system call

From: Kyle Evans Signed-off-by: Kyle Evans Signed-off-by: Karim Taha --- bsd-user/freebsd/os-misc.h| 42 +++ bsd-user/freebsd/os-syscall.c | 13 +++ 2 files changed, 55 insertions(+) diff --git a/bsd-user/freebsd/os-misc.h

Re: [PATCH 20/22] Implement shmctl(2)

Richard Henderson wrote: > On 8/19/23 02:48, Karim Taha wrote: >> +switch (cmd) { >> +case IPC_STAT: >> +case IPC_SET: >> +if (target_to_host_shmid_ds(, buff)) { >> +return -TARGET_EFAULT; >> +} >> +ret = get_errno(shmctl(shmid, cmd, )); >> +

Re: [RESEND] qemu/timer: Add host ticks function for RISC-V

On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini wrote: > > Queued, thanks. > I didn't realize it was already queued. Gmail threads failed me this time. @Paolo Bonzini : Can you please drop this one as this will break as soon as the host riscv system has the latest kernel ? I have provided more

Re: [PATCH v3 8/8] hw/fsi: Documentation and testing

Hello Cedric, On 8/30/23 02:13, Cédric Le Goater wrote: On 8/30/23 09:05, Thomas Huth wrote: On 30/08/2023 04.26, Ninad Palsule wrote: Added FSI document Added basic qtests for FSI model. Added MAINITAINER for FSI Replaced some qemu logs to traces. Sorry, that's not how we rework patch

Re: [RESEND] qemu/timer: Add host ticks function for RISC-V

On Thu, Sep 7, 2023 at 8:33 PM LIU Zhiwei wrote: > > From: LIU Zhiwei > > Signed-off-by: LIU Zhiwei > --- > include/qemu/timer.h | 19 +++ > 1 file changed, 19 insertions(+) > > diff --git a/include/qemu/timer.h b/include/qemu/timer.h > index 9a91cb1248..105767c195 100644 > ---

[PATCH v4 06/10] hw/fsi: Aspeed APB2OPB interface

This is a part of patchset where IBM's Flexible Service Interface is introduced. An APB-to-OPB bridge enabling access to the OPB from the ARM core in the AST2600. Hardware limitations prevent the OPB from being directly mapped into APB, so all accesses are indirect through the bridge.

[PATCH v4 07/10] hw/arm: Hook up FSI module in AST2600

This patchset introduces IBM's Flexible Service Interface(FSI). Time for some fun with inter-processor buses. FSI allows a service processor access to the internal buses of a host POWER processor to perform configuration or debugging. FSI has long existed in POWER processes and so comes with

[PATCH v4 05/10] hw/fsi: IBM's On-chip Peripheral Bus

This is a part of patchset where IBM's Flexible Service Interface is introduced. The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in POWER processors. This now makes an appearance in the ASPEED SoC due to tight integration of the FSI master IP with the OPB, mainly the existence

[PATCH v4 09/10] hw/fsi: Added FSI documentation

Documentation for IBM FSI model. Signed-off-by: Ninad Palsule --- v4: - Added separate commit for documentation --- docs/specs/fsi.rst | 141 + 1 file changed, 141 insertions(+) create mode 100644 docs/specs/fsi.rst diff --git a/docs/specs/fsi.rst

[PATCH v4 01/10] hw/fsi: Introduce IBM's Local bus

This is a part of patchset where IBM's Flexible Service Interface is introduced. The LBUS is modelled to maintain the qdev bus hierarchy and to take advantage of the object model to automatically generate the CFAM configuration block. The configuration block presents engines in the order they are

Re: [PATCH v3 8/8] hw/fsi: Documentation and testing

Hello Thomas, On 8/30/23 02:05, Thomas Huth wrote: On 30/08/2023 04.26, Ninad Palsule wrote: Added FSI document Added basic qtests for FSI model. Added MAINITAINER for FSI Replaced some qemu logs to traces. Sorry, that's not how we rework patch series in the QEMU development process. Please

[PATCH v4 08/10] hw/fsi: Added qtest

Added basic qtests for FSI model. Signed-off-by: Ninad Palsule --- v3: - Added new qtest as per Cedric's comment. V4: - Remove MAINTAINER and documentation changes from this commit --- tests/qtest/fsi-test.c | 210 tests/qtest/meson.build | 2 + 2

[PATCH v4 00/10] Introduce model for IBM's FSI

Hello, Please review the patch-set version 4. I have incorporated review comments from Cedric and Thomas. Ninad Palsule (10): hw/fsi: Introduce IBM's Local bus hw/fsi: Introduce IBM's scratchpad hw/fsi: Introduce IBM's cfam,fsi-slave hw/fsi: Introduce IBM's FSI hw/fsi: IBM's On-chip

[PATCH v4 04/10] hw/fsi: Introduce IBM's FSI

This is a part of patchset where IBM's Flexible Service Interface is introduced. This commit models the FSI bus. CFAM is hanging out of FSI bus. The bus is model such a way that it is embeded inside the FSI master which is a bus controller. The FSI master: A controller in the platform service

[PATCH v4 10/10] hw/fsi: Update MAINTAINER list

Added maintainer for IBM FSI model Signed-off-by: Ninad Palsule --- V4: - Added separate commit for MAINTAINER change. --- MAINTAINERS | 22 ++ 1 file changed, 22 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6111b6b4d9..285f3a3bc9 100644 --- a/MAINTAINERS

[PATCH v4 03/10] hw/fsi: Introduce IBM's cfam,fsi-slave

This is a part of patchset where IBM's Flexible Service Interface is introduced. The Common FRU Access Macro (CFAM), an address space containing various "engines" that drive accesses on busses internal and external to the POWER chip. Examples include the SBEFIFO and I2C masters. The engines hang

[PATCH v4 02/10] hw/fsi: Introduce IBM's scratchpad

This is a part of patchset where IBM's Flexible Service Interface is introduced. The LBUS device is embeded inside the scratchpad. The scratchpad provides a non-functional registers. There is a 1-1 relation between scratchpad and LBUS devices. Each LBUS device has 1K memory mapped in the LBUS.

Re: [PATCH v3 0/6] vfio/migration: Block VFIO migration with postcopy and background snapshot

On Thu, Sep 07, 2023 at 11:07:10AM +0200, Cédric Le Goater wrote: > [ ... ] > > > Applied to vfio-next. > > On that topic I am preparing a PR. > > Juan, Peter, Leonardo, is it ok for you if these migration changes > go through the VFIO tree ? All good here. Thanks, -- Peter Xu

[PATCH] meson: Fix targetos match for illumos and Solaris.

qemu 8.1.0 breaks on illumos platforms due to _XOPEN_SOURCE and others no longer being set correctly, leading to breakage such as: https://us-central.manta.mnx.io/pkgsrc/public/reports/trunk/tools/20230908.1404/qemu-8.1.0/build.log This is a result of meson conversion which incorrectly

Re: [PATCH 04/14] target/arm: Implement FEAT_MOPS enable bits

On 9/7/23 09:03, Peter Maydell wrote: FEAT_MOPS defines a handful of new enable bits: * HCRX_EL2.MSCEn, SCTLR_EL1.MSCEn, SCTLR_EL2.MSCen: define whether the new insns should UNDEF or not * HCRX_EL2.MCE2: defines whether memops exceptions from EL1 should be taken to EL1 or EL2 Since

Re: [PATCH 08/14] target/arm: Implement MTE tag-checking functions for FEAT_MOPS

On 9/7/23 09:03, Peter Maydell wrote: The FEAT_MOPS instructions need a couple of helper routines that check for MTE tag failures: * mte_mops_probe() checks whether there is going to be a tag error in the next up-to-a-page worth of data * mte_check_fail() is an existing function to

Re: [PATCH 07/14] target/arm: New function allocation_tag_mem_probe()

On 9/7/23 09:03, Peter Maydell wrote: @@ -198,6 +215,14 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, return memory_region_get_ram_ptr(mr) + xlat; #endif } +static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx, Missed spacing. Otherwise,

Re: [PATCH 06/14] target/arm: Define syndrome function for MOPS exceptions

On 9/7/23 09:03, Peter Maydell wrote: The FEAT_MOPS memory operations can raise a Memory Copy or Memory Set exception if a copy or set instruction is executed when the CPU register state is not correct for that instruction. Define the usual syn_* function that constructs the syndrome register

Re: [PATCH 05/14] target/arm: Pass unpriv bool to get_a64_user_mem_index()

On 9/7/23 09:03, Peter Maydell wrote: In every place that we call the get_a64_user_mem_index() function we do it like this: memidx = a->unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); Refactor so the caller passes in the bool that says whether they want the 'unpriv' or 'normal'

Re: [PULL 24/51] meson: compile bundled device trees

On Fri, 8 Sep 2023, Michael Tokarev wrote: 08.09.2023 22:21, BALATON Zoltan: I was about to ask, since when but probably nobody knows then. AFAIR I had no such errors for the canyonlands one when I've added it but that was quite some years ago and things in dtc for example could have changed

Re: [PATCH 02/14] target/arm: Don't skip MTE checks for LDRT/STRT at EL0

On 9/7/23 09:03, Peter Maydell wrote: The LDRT/STRT "unprivileged load/store" instructions behave like normal ones if executed at EL0. We handle this correctly for the load/store semantics, but get the MTE checking wrong. We always look at s->mte_active[is_unpriv] to see whether we should be

Re: [PULL 24/51] meson: compile bundled device trees

08.09.2023 22:21, BALATON Zoltan: .. I was about to ask, since when but probably nobody knows then. AFAIR I had no such errors for the canyonlands one when I've added it but that was quite some years ago and things in dtc for example could have changed so it now gives these warnings. I think

Re: [PULL 00/51] Build system, i386 changes for 2023-09-07

On Fri, Sep 8, 2023 at 7:28 PM Kevin Wolf wrote: > Maybe the calls aren't eliminated because --enable-debug implies -O0? My experience is that it will still fold simple dead code like "0 && foo()" or even "if (0) { ... }", but maybe it's a GCC vs. clang difference. Philippe, I take it that you

Re: [PULL 24/51] meson: compile bundled device trees

On Fri, 8 Sep 2023, Michael Tokarev wrote: 08.09.2023 19:27, Philippe Mathieu-Daudé: On 7/9/23 14:59, Paolo Bonzini wrote: If dtc is available, compile the .dts files in the pc-bios directory instead of using the precompiled binaries. Reviewed-by: Richard Henderson Signed-off-by: Paolo

RE: [PATCH 1/3] hw/misc: Introduce AMD/Xilix Versal TRNG device

Hi Peter, Your recommendation is noted. Thanks for your valuable input. I will present V2 with better alignment. Regards, Tong Ho -Original Message- From: Peter Maydell Sent: Friday, September 8, 2023 11:35 AM To: Ho, Tong Cc: Richard Henderson ; qemu-...@nongnu.org;

Re: [RFC Patch 4/5] hw/display: Allwinner A10 LCDC emulation

Hi Philippe, Thank you for your comment. On Wed, Sep 6, 2023 at 7:03 AM Philippe Mathieu-Daudé wrote: > +Gerd & Marc-André for the ui/fb parts. > > On 5/9/23 22:14, Strahinja Jankovic wrote: > > This patch adds support for Allwinner A10 LCD controller. > > Current emulation supports only

Re: [PATCH 1/3] hw/misc: Introduce AMD/Xilix Versal TRNG device

On Fri, 8 Sept 2023 at 18:56, Ho, Tong wrote: > > Hi Peter, > > The Versal TRNG device is required to support both TRNG mode and PRNG mode, > and target/guest > software selects and changes the mode at will during runtime. > > I do agree that, in the TRNG mode, the model using

Re: [PATCH v22 16/20] tests/avocado: s390x cpu topology entitlement tests

On Thu, 2023-09-07 at 11:05 +0200, Thomas Huth wrote: > On 01/09/2023 17.58, Nina Schoetterl-Glausch wrote: > > From: Pierre Morel > > > > Test changes in the entitlement from both a guest and a host point of > > view, depending on the polarization. > > > > Signed-off-by: Pierre Morel > >

[RFC v1 3/8] target/riscv: Add new bits in CSRs for Zjpm 0.6.1

Signed-off-by: Alexey Baturo --- target/riscv/cpu_bits.h | 6 ++ target/riscv/csr.c | 8 target/riscv/pmp.c | 5 + target/riscv/pmp.h | 12 +++- 4 files changed, 26 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu_bits.h

[RFC v1 6/8] target/riscv: Add functions to calculate current N masked bits for pointer masking

Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 6 ++-- target/riscv/cpu_helper.c | 58 +++ 2 files changed, 62 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 17d0088cb4..c87c4f26a2 100644 ---

[RFC v1 0/8] RISC-V Pointer Masking update to Zjpm v0.6.1

Hi all, This series of patches intends to update RISC-V Pointer Masking implementation to the latest Zjpm v0.6.1 version. The Pointer Masking functionality is simplified compared to previous version of spec. The changes have been tested with handwritten assembly tests and LLVM HWASAN test suite.

[RFC v1 2/8] target/riscv: Add new S{sn, mn, m}jpm extensions as part of Zjpm v0.6.1

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 7 +++ target/riscv/cpu_cfg.h | 3 +++ target/riscv/machine.c | 6 -- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f937820976..af8f16b94f 100644 ---

[RFC v1 7/8] target/riscv: Update address modify functions to take into account pointer masking

Signed-off-by: Alexey Baturo --- target/riscv/translate.c | 21 +++-- target/riscv/vector_helper.c | 7 +++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3434ba58b6..4aa0e2b9e1 100644 ---

[RFC v1 5/8] target/riscv: Add pointer masking tb flags

Signed-off-by: Alexey Baturo --- target/riscv/cpu.h| 19 +-- target/riscv/cpu_helper.c | 4 target/riscv/translate.c | 10 ++ 3 files changed, 27 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index

[RFC v1 1/8] target/riscv: Remove obsolete pointer masking extension code

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c | 12 -- target/riscv/cpu.h | 30 +--- target/riscv/cpu_bits.h | 82 - target/riscv/cpu_helper.c| 52 -- target/riscv/csr.c | 326 --- target/riscv/machine.c

[RFC v1 8/8] target/riscv: enable updates for pointer masking variables and thus enable pointer masking extension

Signed-off-by: Alexey Baturo --- target/riscv/cpu.c| 1 + target/riscv/cpu_helper.c | 1 + target/riscv/csr.c| 4 target/riscv/machine.c| 1 + target/riscv/pmp.c| 1 + 5 files changed, 8 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index

[RFC v1 4/8] Add enum with maximum ignored bits depending on privilege level for Zjpm v0.6.1

Signed-off-by: Alexey Baturo --- target/riscv/cpu.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 62dabfa207..25fe60476b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -88,6 +88,16 @@ typedef enum {

RE: [PATCH 1/3] hw/misc: Introduce AMD/Xilix Versal TRNG device

Hi Peter, The Versal TRNG device is required to support both TRNG mode and PRNG mode, and target/guest software selects and changes the mode at will during runtime. I do agree that, in the TRNG mode, the model using qemu_guest_getrandom() will work without any issues. When software selects

Re: [PATCH v6 06/17] nbd/server: Support a request payload

On Wed, Sep 06, 2023 at 12:52:22PM -0500, Eric Blake wrote: > On Tue, Sep 05, 2023 at 05:36:15PM +0300, Vladimir Sementsov-Ogievskiy wrote: > > On 29.08.23 20:58, Eric Blake wrote: > > > Upcoming additions to support NBD 64-bit effect lengths allow for the > > > possibility to distinguish between

Re: [PATCH 11/11] qdev: Rework array properties based on list visitor

Am 08.09.2023 um 17:18 hat Peter Maydell geschrieben: > On Fri, 8 Sept 2023 at 15:37, Kevin Wolf wrote: > > > > Until now, array properties are actually implemented with a hack that > > uses multiple properties on the QOM level: a static "foo-len" property > > and after it is set, dynamically

Re: [PULL 00/51] Build system, i386 changes for 2023-09-07

Am 08.09.2023 um 19:16 hat Kevin Wolf geschrieben: > Am 08.09.2023 um 18:11 hat Philippe Mathieu-Daudé geschrieben: > > Hi Kevin, > > > > On 8/9/23 17:01, Kevin Wolf wrote: > > > Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben: > > > > Applied, thanks. > > > > > > > > Please update the

Re: [PULL 00/51] Build system, i386 changes for 2023-09-07

08.09.2023 20:16, Kevin Wolf: Am 08.09.2023 um 18:11 hat Philippe Mathieu-Daudé geschrieben: Hi Kevin, On 8/9/23 17:01, Kevin Wolf wrote: Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben: Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any

Re: [PULL 00/51] Build system, i386 changes for 2023-09-07

On Fri, Sep 08, 2023 at 07:16:16PM +0200, Kevin Wolf wrote: > Am 08.09.2023 um 18:11 hat Philippe Mathieu-Daudé geschrieben: > > Hi Kevin, > > > > On 8/9/23 17:01, Kevin Wolf wrote: > > > Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben: > > > > Applied, thanks. > > > > > > > > Please

Re: [Qemu PATCH v2 7/9] hw/cxl/cxl-mailbox-utils: Add mailbox commands to support add/release dynamic capacity response

On Fri, Sep 08, 2023 at 01:00:16PM +, J?rgen Hansen wrote: > On 7/25/23 20:39, Fan Ni wrote: > > From: Fan Ni > > > > Per CXL spec 3.0, two mailbox commands are implemented: > > Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.8.9.3, and > > Release Dynamic Capacity (Opcode 4803h)

Re: [PULL 24/51] meson: compile bundled device trees

08.09.2023 19:27, Philippe Mathieu-Daudé: On 7/9/23 14:59, Paolo Bonzini wrote: If dtc is available, compile the .dts files in the pc-bios directory instead of using the precompiled binaries. Reviewed-by: Richard Henderson Signed-off-by: Paolo Bonzini ---   pc-bios/Makefile    | 19

Re: [PULL 00/51] Build system, i386 changes for 2023-09-07

Am 08.09.2023 um 18:11 hat Philippe Mathieu-Daudé geschrieben: > Hi Kevin, > > On 8/9/23 17:01, Kevin Wolf wrote: > > Am 07.09.2023 um 17:44 hat Stefan Hajnoczi geschrieben: > > > Applied, thanks. > > > > > > Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for > > > any

Re: [Qemu PATCH v2 6/9] hw/mem/cxl_type3: Add DC extent list representative and get DC extent list mailbox support

On Fri, Sep 08, 2023 at 01:12:45PM +, J?rgen Hansen wrote: > On 7/25/23 20:39, Fan Ni wrote: > > From: Fan Ni > > > > Add dynamic capacity extent list representative to the definition of > > CXLType3Dev and add get DC extent list mailbox command per > > CXL.spec.3.0:.8.2.9.8.9.2. > > > >

[PULL v2 00/15] Block layer patches

The following changes since commit 13d9f6dca08a38e9258b6328f3ad61bdb8e19619: Merge tag 'ide-pull-request' of https://gitlab.com/jsnow/qemu into staging (2023-09-07 10:28:33 -0400) are available in the Git repository at: https://repo.or.cz/qemu/kevin.git tags/for-upstream for you to fetch

[PULL 12/26] hw/misc: Introduce a model of Xilinx Versal's CFU_APB

From: Francisco Iglesias Introduce a model of the software programming interface (CFU_APB) of Xilinx Versal's Configuration Frame Unit. Signed-off-by: Francisco Iglesias Reviewed-by: Peter Maydell Message-id: 20230831165701.2016397-3-francisco.igles...@amd.com Signed-off-by: Peter Maydell

[PULL 06/26] target/arm: Implement FEAT_EPAC

From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20230829232335.965414-7-richard.hender...@linaro.org Message-Id: <20230609172324.982888-5-aa...@os.amperecomputing.com> Signed-off-by:

[PULL 13/26] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal CFU_FDRO

From: Francisco Iglesias Introduce a model of Xilinx Versal's Configuration Frame Unit's data out port (CFU_FDRO). Signed-off-by: Francisco Iglesias Reviewed-by: Peter Maydell Message-id: 20230831165701.2016397-4-francisco.igles...@amd.com Signed-off-by: Peter Maydell ---

[PULL 24/26] target/arm: Implement FEAT_TIDCP1

From: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20230831232441.66020-5-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.h | 5 + target/arm/helper.h

[PULL 17/26] hw/arm/xlnx-versal: Connect the CFU_APB, CFU_FDRO and CFU_SFR

From: Francisco Iglesias Connect the Configuration Frame Unit (CFU_APB, CFU_FDRO and CFU_SFR) to the Versal machine. Signed-off-by: Francisco Iglesias Acked-by: Edgar E. Iglesias Reviewed-by: Peter Maydell Message-id: 20230831165701.2016397-8-francisco.igles...@amd.com Signed-off-by: Peter

[PULL 07/26] target/arm: Implement FEAT_Pauth2

From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20230829232335.965414-8-richard.hender...@linaro.org Message-Id: <20230609172324.982888-6-aa...@os.amperecomputing.com> Signed-off-by:

[PULL 00/26] target-arm queue

/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230908 for you to fetch changes up to c8f2eb5d414b788420b938f2ffdde891aa6c3ae8: arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE (2023-09-08 16:41:36 +0100) target

[PULL 11/26] hw/misc: Introduce the Xilinx CFI interface

From: Francisco Iglesias Introduce the Xilinx Configuration Frame Interface (CFI) for transmitting CFI data packets between the Xilinx Configuration Frame Unit models (CFU_APB, CFU_FDRO and CFU_SFR), the Xilinx CFRAME controller (CFRAME_REG) and the Xilinx CFRAME broadcast controller

[PULL 14/26] hw/misc/xlnx-versal-cfu: Introduce a model of Xilinx Versal's CFU_SFR

From: Francisco Iglesias Introduce a model of Xilinx Versal's Configuration Frame Unit's Single Frame Read port (CFU_SFR). Signed-off-by: Francisco Iglesias Reviewed-by: Peter Maydell Message-id: 20230831165701.2016397-5-francisco.igles...@amd.com Signed-off-by: Peter Maydell ---

[PULL 25/26] target/arm: Enable SCTLR_EL1.TIDCP for user-only

From: Richard Henderson The linux kernel detects and enables this bit. Once trapped, EC_SYSTEMREGISTERTRAP is treated like EC_UNCATEGORIZED, so no changes required within linux-user/aarch64/cpu_loop.c. Signed-off-by: Richard Henderson Message-id:

[PULL 23/26] target/arm: Implement HCR_EL2.TIDCP

From: Richard Henderson Perform the check for EL2 enabled in the security space and the TIDCP bit in an out-of-line helper. Signed-off-by: Richard Henderson Message-id: 20230831232441.66020-4-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell ---

[PULL 15/26] hw/misc: Introduce a model of Xilinx Versal's CFRAME_REG

From: Francisco Iglesias Introduce a model of Xilinx Versal's Configuration Frame controller (CFRAME_REG). Signed-off-by: Francisco Iglesias Message-id: 20230831165701.2016397-6-francisco.igles...@amd.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- MAINTAINERS

[PULL 01/26] tests/tcg/aarch64: Adjust pauth tests for FEAT_FPAC

From: Richard Henderson With FEAT_FPAC, AUT* instructions that fail authentication do not produce an error value but instead fault. For pauth-2, install a signal handler and verify it gets called. For pauth-4 and pauth-5, we are explicitly testing the error value, so there's nothing to test

[PULL 22/26] target/arm: Implement cortex-a710

From: Richard Henderson The cortex-a710 is a first generation ARMv9.0-A processor. Signed-off-by: Richard Henderson Message-id: 20230831232441.66020-3-richard.hender...@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 1 + hw/arm/virt.c

[PULL 09/26] target/arm: Implement FEAT_FPAC and FEAT_FPACCOMBINE

From: Aaron Lindsay Signed-off-by: Aaron Lindsay Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20230829232335.965414-10-richard.hender...@linaro.org Message-Id: <20230609172324.982888-8-aa...@os.amperecomputing.com> [rth: Simplify fpac comparison, reusing

[PULL 04/26] target/arm: Don't change pauth features when changing algorithm

From: Richard Henderson We have cpu properties to adjust the pauth algorithm for the purpose of speed of emulation. Retain the set of pauth features supported by the cpu even as the algorithm changes. This already affects the neoverse-v1 cpu, which has FEAT_EPAC. Reviewed-by: Peter Maydell

[PULL 26/26] arm/kvm: Enable support for KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE

From: Shameer Kolothum Now that we have Eager Page Split support added for ARM in the kernel, enable it in Qemu. This adds, -eager-split-size to -accel sub-options to set the eager page split chunk size. -enable KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE. The chunk size specifies how many pages to

[PULL 20/26] arm64: Restore trapless ptimer access

From: Colton Lewis Due to recent KVM changes, QEMU is setting a ptimer offset resulting in unintended trap and emulate access and a consequent performance hit. Filter out the PTIMER_CNT register to restore trapless ptimer access. Quoting Andrew Jones: Simply reading the CNT register and

[PULL 10/26] hw/intc/arm_gicv3_its: Avoid maybe-uninitialized error in get_vte()

From: Philippe Mathieu-Daudé Fix when using GCC v11.4 (Ubuntu 11.4.0-1ubuntu1~22.04) with CFLAGS=-Og: [4/6] Compiling C object libcommon.fa.p/hw_intc_arm_gicv3_its.c.o FAILED: libcommon.fa.p/hw_intc_arm_gicv3_its.c.o inlined from ‘lookup_vte’ at hw/intc/arm_gicv3_its.c:453:9,

[PULL 05/26] target/arm: Implement FEAT_PACQARMA3

From: Richard Henderson Implement the QARMA3 cryptographic algorithm for PAC calculation. Implement a cpu feature to select the algorithm and document it. Signed-off-by: Aaron Lindsay Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-id:

[PULL 02/26] target/arm: Add ID_AA64ISAR2_EL1

From: Aaron Lindsay Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Aaron Lindsay Signed-off-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20230829232335.965414-3-richard.hender...@linaro.org [PMM: drop the HVF part of the patch and just

[PULL 18/26] hw/arm/versal: Connect the CFRAME_REG and CFRAME_BCAST_REG

From: Francisco Iglesias Connect the Configuration Frame controller (CFRAME_REG) and the Configuration Frame broadcast controller (CFRAME_BCAST_REG) to the Versal machine. Signed-off-by: Francisco Iglesias Reviewed-by: Peter Maydell Message-id:

[PULL 08/26] target/arm: Inform helpers whether a PAC instruction is 'combined'

From: Aaron Lindsay An instruction is a 'combined' Pointer Authentication instruction if it does something in addition to PAC -- for instance, branching to or loading an address from the authenticated pointer. Knowing whether a PAC operation is 'combined' is needed to implement

[PULL 19/26] target/arm: Do not use gen_mte_checkN in trans_STGP

From: Richard Henderson STGP writes to tag memory, it does not check it. This happened to work because we wrote tag memory first so that the check always succeeded. Signed-off-by: Richard Henderson Message-id: 20230901203103.136408-1-richard.hender...@linaro.org Reviewed-by: Peter Maydell

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