On Sat, Sep 16, 2023 at 12:37:29AM +0800, Akihiko Odaki wrote:
> On 2023/09/16 1:04, Akihiko Odaki wrote:
> > On 2023/09/15 20:11, Huang Rui wrote:
> >> From: Antonio Caggiano
> >>
> >> Support BLOB resources creation, mapping and unmapping by calling the
> >> new stable virglrenderer 0.10
On 2023/09/20 14:50, Huang Rui wrote:
On Sat, Sep 16, 2023 at 12:37:29AM +0800, Akihiko Odaki wrote:
On 2023/09/16 1:04, Akihiko Odaki wrote:
On 2023/09/15 20:11, Huang Rui wrote:
From: Antonio Caggiano
Support BLOB resources creation, mapping and unmapping by calling the
new stable
19.09.2023 12:34, Jonathan Cameron via wrote:
Establishing that only register accesses of size 4 and 8 can occur
using these functions requires looking at their callers. Make it
easier to see that by using switch statements.
Assertions are used to enforce that the register storage is of the
19.09.2023 13:19, Jonathan Cameron via wrote:
v2:
- Tag collection.
- Patch 2 discussion on appropriate license concluded that this should
have originally only been accepted on GPL-v2 and later. However, I've
left it as GPL-v2-only as that is what was used for other CXL files and
Hi Michael S. Tsirkin,
On 2023/9/19 20:31, Michael S. Tsirkin wrote:
> On Tue, Sep 19, 2023 at 07:42:42PM +0800, Jiqian Chen wrote:
>> When guest vm does S3, Qemu will reset and clear some things of virtio
>> devices, but guest can't aware that, so that may cause some problems.
>> For excample,
Hi!
I'm in somewhat doubt what to do with 8.1.1 release.
There are 2 compelling issues, fixing one discovers the other.
https://gitlab.com/qemu-project/qemu/-/issues/1864
"x86 VM with TCG and SMP fails to start on 8.1.0"
is fixed by 0d58c660689f "softmmu: Use async_run_on_cpu in tcg_commit"
> From: Chen, Jiqian
> Sent: Wednesday, September 20, 2023 9:28 AM
> >> For above purpose, we need a mechanism that allows guests and QEMU to
> >> negotiate their reset behavior. So this patch add a new parameter
> >> named
> > Freeze != reset. :)
> > Please fix it to say freeze or suspend.
>
Hi Parav,
On 2023/9/19 20:10, Parav Pandit wrote:
> Hi Jiqian,
>
>> From: Jiqian Chen
>> Sent: Tuesday, September 19, 2023 5:13 PM
>>
>> When guest vm does S3, Qemu will reset and clear some things of virtio
>> devices, but guest can't aware that, so that may cause some problems.
> It is not
>-Original Message-
>From: Cédric Le Goater
>Sent: Wednesday, September 20, 2023 1:08 AM
>Subject: Re: [PATCH v1 15/22] Add iommufd configure option
>
>On 8/30/23 12:37, Zhenzhong Duan wrote:
>> This adds "--enable-iommufd/--disable-iommufd" to enable or disable
>> iommufd support,
>-Original Message-
>From: Cédric Le Goater
>Sent: Wednesday, September 20, 2023 12:01 AM
>Subject: Re: [PATCH v1 14/22] vfio/common: Simplify vfio_viommu_preset()
>
>On 8/30/23 12:37, Zhenzhong Duan wrote:
>> Commit "vfio/container-base: Introduce [attach/detach]_device container
On Tue, Sep 19, 2023 at 07:47:09PM +, Bernhard Beschow wrote:
>
>
> Am 8. September 2023 08:42:26 UTC schrieb Bernhard Beschow
> :
> >This series contains changes from my effort to bring the VIA south bridges to
> >
> >the PC machine [1]. The first part of the series resolves the
> >
>
Hi pbonzini:
please take some to review this patch. It fixes
autoconverge migration issue for heavy memory dirty
pages. Any comment will be welcome, Thx.
On 2023/9/18 11:29, alloc.yo...@outlook.com wrote:
From: alloc
During migrations, vcpu may run longer than 10ms and not exit
on time.
On 9/19/2023 5:46 PM, Markus Armbruster wrote:
Xiaoyao Li writes:
From: Isaku Yamahata
Add a new property "private" to memory backends. When it's set to true,
it indicates the RAMblock of the backend also requires kvm gmem.
Can you add a brief explanation why you need the property?
It
Adds migration support for Branch History Rolling
Buffer (BHRB) internal state.
Signed-off-by: Glenn Miles
---
target/ppc/machine.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index d42e475bfb..ba328ad5e2 100644
---
This commit is preparatory to the addition of Branch History
Rolling Buffer (BHRB) functionality, which is being provided
today starting with the P8 processor.
BHRB uses several SPR register fields to control whether or not
a branch instruction's address (and sometimes target address)
should be
Add support for the clrbhrb and mfbhrbe instructions.
Since neither instruction is believed to be critical to
performance, both instructions were implemented using helper
functions.
Access to both instructions is controlled by bits in the
HFSCR (for privileged state) and MMCR0 (for problem
On 2023-09-14 20:20, Nicholas Piggin wrote:
On Wed Sep 13, 2023 at 6:25 AM AEST, Glenn Miles wrote:
Adds migration support for Branch History Rolling
Buffer (BHRB) internal state.
Signed-off-by: Glenn Miles
---
target/ppc/machine.c | 23 +++
1 file changed, 23
This commit continues adding support for the Branch History
Rolling Buffer (BHRB) as is provided starting with the P8
processor and continuing with its successors. This commit
is limited to the recording and filtering of taken branches.
The following changes were made:
- Added a BHRB buffer
This is a series of patches for adding support for the Branch History
Rolling Buffer (BHRB) facility. This was added to the Power ISA
starting with version 2.07. Changes were subsequently made in version
3.1 to limit BHRB recording to instructions run in problem state only
and to add a control
On 2023/09/19 23:21, Xenia Ragiadakou wrote:
On 19/9/23 13:44, Akihiko Odaki wrote:
On 2023/09/19 19:28, Xenia Ragiadakou wrote:
On 15/9/23 18:11, Akihiko Odaki wrote:
On 2023/09/15 20:11, Huang Rui wrote:
From: Xenia Ragiadakou
When the memory region has a different life-cycle from that
On 2023/09/20 3:36, Bernhard Beschow wrote:
Am 15. September 2023 02:38:02 UTC schrieb Gurchetan Singh
:
On Thu, Sep 14, 2023 at 12:23 AM Bernhard Beschow wrote:
Am 14. September 2023 04:38:51 UTC schrieb Gurchetan Singh <
gurchetansi...@chromium.org>:
On Wed, Sep 13, 2023 at 4:58 AM
On 2023-09-14 20:13, Nicholas Piggin wrote:
On Wed Sep 13, 2023 at 6:24 AM AEST, Glenn Miles wrote:
Add support for the clrbhrb and mfbhrbe instructions.
Since neither instruction is believed to be critical to
performance, both instructions were implemented using helper
functions.
Access to
On 2023-09-14 20:02, Nicholas Piggin wrote:
On Wed Sep 13, 2023 at 6:24 AM AEST, Glenn Miles wrote:
This commit continues adding support for the Branch History
Rolling Buffer (BHRB) as is provided starting with the P8
processor and continuing with its successors. This commit
is limited to the
On 2023-09-14 19:39, Nicholas Piggin wrote:
On Wed Sep 13, 2023 at 6:23 AM AEST, Glenn Miles wrote:
This commit is preparatory to the addition of Branch History
Rolling Buffer (BHRB) functionality, which is being provided
today starting with the P8 processor.
BHRB uses several SPR register
Hi Alistair,
> It would be great to get a strace of the failure to narrow down what
> it is. From there it should be not too hard to find and fix.
thanks a lot. Here's as much info as I could get with strace mechanisms.
1) What I did, without any tracing
pinacolada ~ # qemu-riscv32 -L
On 9/6/23 21:35, Gavin Shan wrote:
For target/riscv, the CPU type name is always the combination of the
CPU model name and suffix. The CPU model names have been correctly
shown in riscv_cpu_list_entry() and riscv_cpu_add_definition()
Use generic helper cpu_mdoel_from_type() to show the CPU
Example output lacks double quotes. Fix it.
Fixes: 4cda177c60 "qmp: add 'get-win32-socket'"
Signed-off-by: Victor Toso
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Markus Armbruster
---
qapi/misc.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/misc.json
Example output has a comment embedded in the array. Remove it.
The end result is a list of size 2.
Signed-off-by: Victor Toso
Reviewed-by: Daniel P. Berrangé
---
qapi/ui.json | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/qapi/ui.json b/qapi/ui.json
index
Example output has several missing commas. Add them.
Signed-off-by: Victor Toso
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Markus Armbruster
---
qapi/block-core.json | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/qapi/block-core.json
Example output has property name with single quotes. Fix it.
Signed-off-by: Victor Toso
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Markus Armbruster
---
qapi/migration.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/migration.json b/qapi/migration.json
index
Example output has extra end curly bracket. Switch with comma.
Signed-off-by: Victor Toso
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Markus Armbruster
---
qapi/machine.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/machine.json b/qapi/machine.json
index
This generator has two goals:
1. Mechanical validation of QAPI examples
2. Generate the examples in a JSON format to be consumed for extra
validation.
The generator iterates over every Example section, parsing both server
and client messages. The generator prints any inconsistency found,
Example output was using single quotes. Fix it.
Signed-off-by: Victor Toso
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Markus Armbruster
---
qapi/net.json | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/qapi/net.json b/qapi/net.json
index 313c8a606e..81988e499a
Example output has extra end curly bracket. Remove it.
Signed-off-by: Victor Toso
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Markus Armbruster
---
qapi/migration.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/migration.json b/qapi/migration.json
index
Example output has extra end curly bracket. Remove it.
Signed-off-by: Victor Toso
Reviewed-by: Daniel P. Berrangé
Reviewed-by: Markus Armbruster
---
qapi/migration.json | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/migration.json b/qapi/migration.json
index
Example output has a comment embedded in the array. Remove it.
The end result is a list of size 1.
Signed-off-by: Victor Toso
Reviewed-by: Daniel P. Berrangé
---
qapi/rocker.json | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/qapi/rocker.json b/qapi/rocker.json
index
Hi,
v2: https://lists.gnu.org/archive/html/qemu-devel/2023-09/msg02383.html
- Sorry Markus, I kept the two last 'fix example' patches as I don't
fully remember how we should go with it. Not taking them but taking
the generator would be bad as we would fail the build.
- Removed the meson
On Tue, 19 Sept 2023 at 06:26, Kevin Wolf wrote:
> Am 18.09.2023 um 20:56 hat Stefan Hajnoczi geschrieben:
> If we could fully get rid of the AioContext lock (as we originally
> stated as a goal), that would automatically solve this kind of
> deadlocks.
Grepping for "ctx locked", "context
From: Hao Wu
This patch implements the basic registers of GMAC device. Actual network
communications are not supported yet.
Signed-off-by: Hao Wu
include/hw: Fix type problem in NPCMGMACState
- Fix type problem in NPCMGMACState
- Fix Register Initalization which was breaking boot-up in
From: Nabih Estefan Diaz
- Implementation of Transmit function for packets
- Implementation for reading and writing from and to descriptors in
memory for Tx
NOTE: This function implements the steps detailed in the datasheet for
transmitting messages from the GMAC.
Signed-off-by: Nabih
From: Hao Wu
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu
---
From: Hao Wu
This patch wires the PCI mailbox module to Nuvoton SoC.
hw/misc: Add chardev to PCI mailbox
This patches adds a chardev to PCI mailbox that can be used to
receive external read and write request from the host.
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 16
From: Hao Wu
Signed-off-by: Hao Wu
---
hw/arm/npcm8xx.c | 12
include/hw/arm/npcm8xx.h | 118 +++
2 files changed, 118 insertions(+), 12 deletions(-)
create mode 100644 include/hw/arm/npcm8xx.h
diff --git a/hw/arm/npcm8xx.c b/hw/arm/npcm8xx.c
From: Hao Wu
As NPCM8XX SoCs have 2 mailboxes, we can't use -global to connect
the mailboxes to their specific chardevs. So we add the search
for chardev code here, similar to what we did for the GMAC devices.
Signed-off-by: Hao Wu
---
hw/arm/npcm8xx.c | 11 +++
1 file changed, 11
From: Hao Wu
Signed-off-by: Hao Wu
---
hw/arm/npcm7xx.c | 38 --
include/hw/arm/npcm7xx.h | 3 +++
2 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
index c69e936669..15c58ef4a9 100644
---
From: Nabih Estefan Diaz
- General GMAC Register handling
- GMAC IRQ Handling
- Added traces in some methods for debugging
- Lots of declarations for accessing information on GMAC Descriptors
(npcm_gmac.h file)
NOTE: With code on this state, the GMAC can boot-up properly and will show up
in
From: Nabih Estefan Diaz
- Implementation of Receive function for packets
- Implementation for reading and writing from and to descriptors in
memory for Rx
NOTE: At this point in development we believe this function is working
as intended, and the kernel supports these findings, but we need
From: Hao Wu
This patches adds a qtest for NPCM7XX PCI Mailbox module.
It sends read and write requests to the module, and verifies that
the module contains the correct data after the requests.
Signed-off-by: Hao Wu
---
tests/qtest/meson.build | 1 +
From: Nabih Estefan Diaz
- Created qtest to check initialization of registers in GMAC Module.
- Implemented test into Build File.
Signed-off-by: Nabih Estefan Diaz
---
tests/qtest/meson.build | 11 +-
tests/qtest/npcm_gmac-test.c | 209 +++
2 files
From: Nabih Estefan Diaz
Creates NPI Mailbox Module with data verification for read and write (internal
and external),
wiring to the Nuvoton SoC, and QTests.
Also creates the GMAC Networking Module. Implements read and write
functionalities with cooresponding descriptors
and registers. Also
From: Hao Wu
The PCI Mailbox Module is a high-bandwidth communcation module
between a Nuvoton BMC and CPU. It features 16KB RAM that are both
accessible by the BMC and core CPU. and supports interrupt for
both sides.
This patch implements the BMC side of the PCI mailbox module.
Communication
From: Nabih Estefan Diaz
- Implemeted classes for GMAC Receive and Transmit Descriptors
- Implemented Masks for said descriptors
Signed-off-by: Nabih Estefan Diaz
---
include/hw/net/npcm_gmac.h | 27 +++
1 file changed, 27 insertions(+)
diff --git
From: Nabih Estefan Diaz
- Add PCS Register check to npcm_gmac-test
Signed-off-by: Nabih Estefan Diaz
---
tests/qtest/npcm_gmac-test.c | 135 ++-
1 file changed, 134 insertions(+), 1 deletion(-)
diff --git a/tests/qtest/npcm_gmac-test.c
Am 3. April 2023 12:27:14 UTC schrieb Jason Andryuk :
>On Mon, Apr 3, 2023 at 5:33 AM Anthony PERARD
>wrote:
>>
>> On Sat, Apr 01, 2023 at 10:36:45PM +, Bernhard Beschow wrote:
>> >
>> >
>> > Am 30. März 2023 13:00:25 UTC schrieb Anthony PERARD
>> > :
>> > >On Sun, Mar 12, 2023 at
Am 8. September 2023 08:42:26 UTC schrieb Bernhard Beschow :
>This series contains changes from my effort to bring the VIA south bridges to
>
>the PC machine [1]. The first part of the series resolves the
>
>AcpiCpuAmlIfClass::madt_cpu virtual method which frees ACPI controllers from
>
Am 15. September 2023 02:38:02 UTC schrieb Gurchetan Singh
:
>On Thu, Sep 14, 2023 at 12:23 AM Bernhard Beschow wrote:
>
>>
>>
>> Am 14. September 2023 04:38:51 UTC schrieb Gurchetan Singh <
>> gurchetansi...@chromium.org>:
>> >On Wed, Sep 13, 2023 at 4:58 AM Bernhard Beschow
>> wrote:
>> >
On Tue, 19 Sept 2023 at 06:26, Kevin Wolf wrote:
>
> Am 18.09.2023 um 20:56 hat Stefan Hajnoczi geschrieben:
> > Hi Kevin,
> > I believe that my own commit "block-coroutine-wrapper: use
> > qemu_get_current_aio_context()" breaks this test. The failure is
> > non-deterministic (happens about 1 out
From: Helge Deller
Change the TLB code to store the Block-TLBs at the beginning
of the TLB table. New 4k TLB entries which are added later
shall not overwrite any of the BTLB entries.
Make sure that when the TLB is cleared by the OS via the ptlbe
instruction, the Block-TLBs will not be dropped.
Hi Stefan,
On 9/19/23 19:18, Stefan Hajnoczi wrote:
Please take a look at the following CI failure and resend when you
have fixed the error:
...
In file included from ../target/hppa/mem_helper.c:21:
../target/hppa/mem_helper.c: In function ‘helper_diag_btlb’:
../target/hppa/mem_helper.c:461:36:
From: Mikulas Patocka
qemu-hppa may crash when delivering a signal. It can be demonstrated with
this program. Compile the program with "hppa-linux-gnu-gcc -O2 signal.c"
and run it with "qemu-hppa -one-insn-per-tb a.out". It reports that the
address of the flag is 0xb4 and it crashes when
From: Helge Deller
Extract the immediate value given by the diagnose CPU instruction.
This is needed to distinguish the various diagnose calls.
Signed-off-by: Helge Deller
---
target/hppa/insns.decode | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/hppa/insns.decode
From: Mikulas Patocka
The code in setup_rt_frame reads two words at haddr, but locks only one.
This patch fixes it to lock both.
Signed-off-by: Mikulas Patocka
Acked-by: Helge Deller
Cc: qemu-sta...@nongnu.org
Signed-off-by: Helge Deller
---
linux-user/hppa/signal.c | 5 +++--
1 file
From: Helge Deller
The following changes since commit 9ef497755afc252fb8e060c9ea6b0987abfd20b6:
Merge tag 'pull-vfio-20230911' of https://github.com/legoater/qemu into
staging (2023-09-11 09:13:08 -0400)
are available in the Git repository at:
https://github.com/hdeller/qemu-hppa.git
From: Helge Deller
Reserve 16 out of the 256 TLB entries for Block-TLBs.
Signed-off-by: Helge Deller
---
target/hppa/cpu.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index fa13694dab..23852d89b2 100644
---
From: Helge Deller
Report the new number of TLB entries (without BTLBs) to the
guest and drop reporting of BTLB entries which weren't used at all.
Clear all BTLB and TLB entries at machine reset.
Signed-off-by: Helge Deller
---
hw/hppa/machine.c | 10 +-
1 file changed, 5
From: Helge Deller
Wire up the hppa diag instruction to support Block-TLBs
when called with the 0x100 value.
The diag_btlb() helper function does all necessary steps
to emulate the PDC BTLB firmware function, which includes
providing BTLB info, adding a new BTLB, deleting a BTLB
and removing
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Daniel P. Berrangé writes:
> On Tue, Sep 19, 2023 at 12:49:46PM -0400, Peter Xu wrote:
>> On Mon, Sep 18, 2023 at 04:41:14PM +0200, Markus Armbruster wrote:
>> > Oh dear, where to start. There's so much wrong, and in pretty obvious
>> > ways. This code should never have passed review. I'm
On Tue, Sep 19, 2023 at 12:49:46PM -0400, Peter Xu wrote:
> On Mon, Sep 18, 2023 at 04:41:14PM +0200, Markus Armbruster wrote:
> > Oh dear, where to start. There's so much wrong, and in pretty obvious
> > ways. This code should never have passed review. I'm refraining from
> > saying more; see
On Tue, Sep 19, 2023 at 7:14 PM Peter Xu wrote:
>
> On Tue, Sep 19, 2023 at 09:08:10AM -0700, Mattias Nissler wrote:
> > @@ -3119,31 +3143,35 @@ void *address_space_map(AddressSpace *as,
> > void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
> > bool
>
> Let me take a look at that. I suspect the timer is off by 1 tick due to
> some rounding errors.
On Tue, 2023-09-19 at 14:47 +0200, Markus Armbruster wrote:
> Nina Schoetterl-Glausch writes:
>
> > From: Pierre Morel
> >
> > S390 adds two new SMP levels, drawers and books to the CPU
> > topology.
> > S390 CPUs have specific topology features like dedication and
> > entitlement. These
Hi,
Sometimes npcm7xx_timer-test fails intermittently:
https://gitlab.com/qemu-project/qemu/-/jobs/5121787250
38/96 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_timer-test ERROR
0.95s exit status 1
>>> QTEST_QEMU_BINARY=./qemu-system-arm
>>>
Hello all,
I've started working on better support and documentation around
hypervisor vmcores in the Drgn debugger[1]. Of course there's quite a
lot of different implementations out there, but recently I'm looking at
Qemu kdump and ELF vmcores generated via dump-guest-memory, and one
thing caught
On Tue, 19 Sept 2023 at 06:26, Kevin Wolf wrote:
>
> Am 18.09.2023 um 20:56 hat Stefan Hajnoczi geschrieben:
> > Hi Kevin,
> > I believe that my own commit "block-coroutine-wrapper: use
> > qemu_get_current_aio_context()" breaks this test. The failure is
> > non-deterministic (happens about 1 out
On 8/30/23 12:37, Zhenzhong Duan wrote:
From: Yi Liu
Abstract the VFIOContainer to be a base object. It is supposed to be
embedded by legacy VFIO container and later on, into the new iommufd
based container.
The base container implements generic code such as code related to
memory_listener
On Wed, 13 Sep 2023 10:01:47 +0200
Eric Auger wrote:
> Now we retrieve the usable IOVA ranges from the host,
> we now the physical IOMMU aperture and we can remove
> the assumption of 64b IOVA space when calling
> vfio_host_win_add().
>
> This works fine in general but in case of an IOMMU
Please take a look at the following CI failure and resend when you
have fixed the error:
mipsel-linux-gnu-gcc -Ilibqemu-hppa-softmmu.fa.p -I. -I..
-Itarget/hppa -I../target/hppa -Iqapi -Itrace -Iui -Iui/shader
-I/usr/include/pixman-1 -I/usr/include/capstone
-I/usr/include/spice-server
On Tue, Sep 19, 2023 at 09:08:10AM -0700, Mattias Nissler wrote:
> @@ -3119,31 +3143,35 @@ void *address_space_map(AddressSpace *as,
> void address_space_unmap(AddressSpace *as, void *buffer, hwaddr len,
> bool is_write, hwaddr access_len)
> {
> -if (buffer !=
On Tue, Sep 19, 2023 at 09:08:09AM -0700, Mattias Nissler wrote:
> Instead of using a single global bounce buffer, give each AddressSpace
> its own bounce buffer. The MapClient callback mechanism moves to
> AddressSpace accordingly.
>
> This is in preparation for generalizing bounce buffer
On 8/30/23 12:37, Zhenzhong Duan wrote:
This adds "--enable-iommufd/--disable-iommufd" to enable or disable
iommufd support, enabled by default.
Why would someone want to disable support at compile time ? It might
have been useful for dev but now QEMU should self-adjust at runtime
depending
In case when we're rebasing within one backing chain, and when target image
is larger than old backing file, bdrv_is_allocated_above() ends up setting
*pnum = 0. As a result, target offset isn't getting incremented, and we
get stuck in an infinite for loop. Let's detect this case and proceed
When rebasing an image from one backing file to another, we need to
compare data from old and new backings. If the diff between that data
happens to be unaligned to the target cluster size, we might end up
doing partial writes, which would lead to copy-on-write and additional IO.
Consider the
The test cases considered so far:
314 (new test suite):
1. Check that compression mode isn't compatible with "-f raw" (raw
format doesn't support compression).
2. Check that rebasing an image onto no backing file preserves the data
and writes the copied clusters actually compressed.
3.
Add @chsize param to the function which, if non-zero, would represent
the chunk size to be used for comparison. If it's zero, then
BDRV_SECTOR_SIZE is used as default chunk size, which is the previous
behaviour.
In particular, we're going to use this param in img_rebase() to make the
write
Before previous commit, rebase was getting infitely stuck in case of
rebasing within the same backing chain and when overlay_size > backing_size.
Let's add this case to the rebasing test 024 to make sure it doesn't
break again.
Signed-off-by: Andrey Drobyshev
Reviewed-by: Denis V. Lunev
As the previous commit changes the logic of "qemu-img rebase" (it's using
write alignment now), let's add a couple more test cases which would
ensure it works correctly. In particular, the following scenarios:
024: add test case for rebase within one backing chain when the overlay
cluster
v2 --> v3:
* Patch 3/8: fixed logic in the if statement, so that we align on blk
when blk_old_backing == NULL;
* Patch 4/8: comment fix;
* Patch 5/8: comment fix; dropped redundant "if (blk_new_backing)"
statements.
v2:
Since commit bb1c05973cf ("qemu-img: Use qemu_blockalign"), buffers for
the data read from the old and new backing files are aligned using
BlockDriverState (or BlockBackend later on) referring to the target image.
However, this isn't quite right, because buf_new is only being used for
reading from
If we rebase an image whose backing file has compressed clusters, we
might end up wasting disk space since the copied clusters are now
uncompressed. In order to have better control over this, let's add
"--compress" option to the "qemu-img rebase" command.
Note that this option affects only the
On Mon, Sep 18, 2023 at 04:41:14PM +0200, Markus Armbruster wrote:
> Oh dear, where to start. There's so much wrong, and in pretty obvious
> ways. This code should never have passed review. I'm refraining from
> saying more; see the commit messages instead.
>
> Issues remaining after this
On Wed, 13 Sep 2023 10:01:41 +0200
Eric Auger wrote:
> This helper reverses an array of regions, turning original
> regions into holes and original holes into actual regions,
> covering the whole UINT64_MAX span.
>
> Signed-off-by: Eric Auger
>
> ---
>
> v1 -> v2:
> - Move
On 9/19/23 13:46, Hanna Czenczek wrote:
> On 15.09.23 18:20, Andrey Drobyshev wrote:
>> When rebasing an image from one backing file to another, we need to
>> compare data from old and new backings. If the diff between that data
>> happens to be unaligned to the target cluster size, we might end
On Tue, 19 Sept 2023 at 12:00, Alex Bennée wrote:
>
>
> Stefan Hajnoczi writes:
>
> > There is some funny business with tests/lcitool/libvirt-ci. Please
> > rebase on master and send a v3. Sorry for the trouble, I am afraid I
> > would mess something up with the submodule if I attempted to
When DMA memory can't be directly accessed, as is the case when
running the device model in a separate process without shareable DMA
file descriptors, bounce buffering is used.
It is not uncommon for device models to request mapping of several DMA
regions at the same time. Examples include:
*
Brings in assorted bug fixes. The following are of particular interest
with respect to message-based DMA support:
* bb308a2 "Fix address calculation for message-based DMA"
Corrects a bug in DMA address calculation.
* 1569a37 "Pass server->client command over a separate socket pair"
Adds
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