[PATCH v3 12/88] target/hppa: Fix hppa64 case in machine.c

Typo of VMSTATE_UINTTR_V and VMSTATE_UINTTR_ARRAY_V macros. Signed-off-by: Richard Henderson --- target/hppa/machine.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hppa/machine.c b/target/hppa/machine.c index ab3e8c81fa..61ae942ff1 100644 ---

[PATCH v3 10/88] target/hppa: Remove get_temp_tl

Replace with tcg_temp_new_tl without recording into ctx. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 28 +++- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/target/hppa/translate.c

[PATCH v3 27/88] target/hppa: Pass DisasContext to copy_iaoq_entry

Interface change only, no functional effect. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 39 --- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 4e0bc48b09..e342cc1d08

[PATCH v3 11/88] target/hppa: Remove load_const

Replace with tcg_constant_reg. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/translate.c | 21 +++-- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index

[PATCH v3 04/88] target/hppa: Always report one page to tlb_set_page

No need to trigger the large_page_mask code unnecessarily. Drop the now unused HPPATLBEntry.page_size field. Signed-off-by: Richard Henderson --- target/hppa/cpu.h| 5 +++-- target/hppa/mem_helper.c | 11 +-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git

[PATCH v3 14/88] target/hppa: Truncate rotate count in trans_shrpw_sar

When forcing rotate by i32, the shift count must be as well. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 20e44ed528..d6ccce020a 100644 ---

[PATCH v3 24/88] target/hppa: Handle absolute addresses for pa2.0

With pa2.0, absolute addresses are not the same as physical addresses, and undergo a transformation based on PSW_W. Signed-off-by: Richard Henderson --- target/hppa/cpu.h| 3 +++ target/hppa/mem_helper.c | 43 ++-- 2 files changed, 44 insertions(+),

[PATCH v3 22/88] target/hppa: Implement hppa_cpu_class_by_name

Signed-off-by: Richard Henderson --- linux-user/hppa/target_elf.h | 2 +- target/hppa/cpu.c| 10 +- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/linux-user/hppa/target_elf.h b/linux-user/hppa/target_elf.h index 82b4e9535e..19cae8bd65 100644 ---

[PATCH v3 07/88] tcg: Improve expansion of deposit of constant

The extract2 expansion is too difficult for the optimizer to simplify. If we have an immediate input, use and+or instead, skipping the and if the field becomes all 1's. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 28 1 file changed, 28 insertions(+) diff

[PATCH v3 25/88] target/hppa: Adjust hppa_cpu_dump_state for hppa64

Dump all 64 bits for pa2.0 and low 32 bits for pa1.x. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hppa/helper.c | 28 +++- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/target/hppa/helper.c b/target/hppa/helper.c

Re: [PATCH 1/1] MAINTAINERS: update mail address for Weiwei Li

On Mon, Oct 30, 2023 at 6:17 PM Weiwei Li wrote: > > My Iscas mail account will be disabled soon, change to my personal > gmail account. > > Signed-off-by: Weiwei Li Reviewed-by: Alistair Francis Alistair > --- > MAINTAINERS | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff

Re: [PATCH v5 09/13] hw/riscv/virt-acpi-build.c: Add MMU node in RHCT

On Mon, Oct 30, 2023 at 11:23 PM Sunil V L wrote: > > MMU type information is available via MMU node in RHCT. Add this node in > RHCT. > > Signed-off-by: Sunil V L > Reviewed-by: Daniel Henrique Barboza > Reviewed-by: Andrew Jones Acked-by: Alistair Francis Alistair > --- >

Re: [PATCH v2 14/14] disas/riscv: Replace TABs with space

On Fri, Oct 27, 2023 at 1:21 AM Max Chou wrote: > > Replaces TABs with spaces, making sure to have a consistent coding style > of 4 space indentations. > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > disas/riscv.c | 6 +++--- > 1 file changed, 3 insertions(+), 3

Re: [PATCH v2 13/14] disas/riscv: Add support for vector crypto extensions

On Fri, Oct 27, 2023 at 1:22 AM Max Chou wrote: > > This patch adds following v1.0.0 ratified vector crypto extensions > support to the RISC-V disassembler. > - Zvbb > - Zvbc > - Zvkb > - Zvkg > - Zvkned > - Zvknha > - Zvknhb > - Zvksed > - Zvksh > > Signed-off-by: Max Chou Acked-by: Alistair

Re: [PATCH v2 12/14] disas/riscv: Add rv_codec_vror_vi for vror.vi

On Fri, Oct 27, 2023 at 2:47 AM Max Chou wrote: > > Add rv_codec_vror_vi for the vector crypto instruction - vror.vi. > The rotate amount of vror.vi is defined by combining seperated bits. > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > disas/riscv.c | 14

Re: [PATCH v2 11/14] disas/riscv: Add rv_fmt_vd_vs2_uimm format

On Fri, Oct 27, 2023 at 1:21 AM Max Chou wrote: > > Add rv_fmt_vd_vs2_uimm format for vector crypto instructions. > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > disas/riscv.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/disas/riscv.h b/disas/riscv.h >

Re: [PATCH v2 10/14] target/riscv: Move vector crypto extensions to riscv_cpu_extensions

On Fri, Oct 27, 2023 at 1:22 AM Max Chou wrote: > > Because the vector crypto specification is ratified, so move theses > extensions from riscv_cpu_experimental_exts to riscv_cpu_extensions. > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 36

Re: [PATCH v2 09/14] target/riscv: Expose Zvks[c|g] extnesion properties

On Fri, Oct 27, 2023 at 1:22 AM Max Chou wrote: > > Expose the properties of ShangMi Algorithm Suite related extensions > (Zvks, Zvksc, Zvksg). > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff

Re: [PATCH v2 08/14] target/riscv: Add cfg properties for Zvks[c|g] extensions

On Fri, Oct 27, 2023 at 1:21 AM Max Chou wrote: > > Vector crypto spec defines the ShangMi algorithm suite related > extensions (Zvks, Zvksc, Zvksg) combined by several vector crypto > extensions. > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu_cfg.h

Re: [PATCH v2 07/14] target/riscv: Expose Zvkn[c|g] extnesion properties

On Fri, Oct 27, 2023 at 1:21 AM Max Chou wrote: > > Expose the properties of NIST Algorithm Suite related extensions (Zvkn, > Zvknc, Zvkng). > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 6 ++ > 1 file changed, 6 insertions(+) > > diff

Re: [PATCH v2 06/14] target/riscv: Add cfg properties for Zvkn[c|g] extensions

On Fri, Oct 27, 2023 at 2:21 AM Max Chou wrote: > > Vector crypto spec defines the NIST algorithm suite related extensions > (Zvkn, Zvknc, Zvkng) combined by several vector crypto extensions. > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu_cfg.h

Re: [PATCH v2 05/14] target/riscv: Expose Zvkb extension property

On Fri, Oct 27, 2023 at 1:21 AM Max Chou wrote: > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 5099c786415..992f8e0f7b0 100644 > ---

Re: [PATCH v2 04/14] target/riscv: Replace Zvbb checking by Zvkb

On Fri, Oct 27, 2023 at 1:21 AM Max Chou wrote: > > The Zvkb extension is a proper subset of the Zvbb extension and includes > following instructions: > * vandn.[vv,vx] > * vbrev8.v > * vrev8.v > * vrol.[vv,vx] > * vror.[vv,vx,vi] > > Signed-off-by: Max Chou Acked-by: Alistair Francis

Re: [PATCH v2 03/14] target/riscv: Add cfg property for Zvkb extension

On Fri, Oct 27, 2023 at 1:21 AM Max Chou wrote: > > After vector crypto spec v1.0.0-rc3 release, the Zvkb extension is > defined as a proper subset of the Zvbb extension. And both the Zvkn and > Zvks shorthand extensions replace the included Zvbb extension by Zvkb > extnesion. > > Signed-off-by:

Re: [PATCH v2 02/14] target/riscv: Expose Zvkt extension property

On Fri, Oct 27, 2023 at 1:21 AM Max Chou wrote: > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a2881bfa383..5099c786415 100644 > ---

Re: [PATCH v2 01/14] target/riscv: Add cfg property for Zvkt extension

On Fri, Oct 27, 2023 at 1:21 AM Max Chou wrote: > > Vector crypto spec defines the Zvkt extension that included all of the > instructions of Zvbb & Zvbc extensions and some vector instructions. > > Signed-off-by: Max Chou Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu_cfg.h

Re: [PATCH v2 1/1] target/riscv: correct csr_ops[CSR_MSECCFG]

On Mon, Oct 30, 2023 at 8:22 PM Heinrich Schuchardt wrote: > > The CSR register mseccfg is used by multiple extensions: Smepm and Zkr. > > Consider this when checking the existence of the register. > > Fixes: 77442380ecbe ("target/riscv: rvk: add CSR support for Zkr") > Signed-off-by: Heinrich

Re: [PATCH v2 1/1] target/riscv: correct csr_ops[CSR_MSECCFG]

On Mon, Oct 30, 2023 at 8:22 PM Heinrich Schuchardt wrote: > > The CSR register mseccfg is used by multiple extensions: Smepm and Zkr. > > Consider this when checking the existence of the register. > > Fixes: 77442380ecbe ("target/riscv: rvk: add CSR support for Zkr") > Signed-off-by: Heinrich

Re: [PATCH v5 4/5] target/riscv: Add "pmu-mask" property to replace "pmu-num"

On Wed, Nov 1, 2023 at 1:41 AM Rob Bradford wrote: > > Using a mask instead of the number of PMU devices supports the accurate > emulation of platforms that have a discontinuous set of PMU counters. > > The "pmu-num" property now generates a warning when used by the user on > the command line. >

[PATCH v4 11/33] target/loongarch: Use generic helper to show CPU model names

For target/loongarch, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Signed-off-by: Gavin Shan --- target/loongarch/cpu.c| 5 - target/loongarch/loongarch-qmp-cmds.c | 3 +-- 2

[PATCH v4 33/33] hw/riscv/shakti_c: Check CPU type in machine_run_board_init()

Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/shakti_c.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-)

[PATCH 1/2] hw/ssi: ibex_spi_host: Clear the interrupt even if disabled

We currently don't clear the interrupts if they are disabled. This means that if an interrupt occurs and the guest disables interrupts the QEMU IRQ will remain high. This doesn't immediately affect guests, but if the guest re-enables interrupts it's possible that we will miss an interrupt as it

[PATCH 2/2] target/riscv: cpu: Set the OpenTitan priv to 1.12.0

Set the Ibex CPU priv to 1.12.0 to ensure that smepmp/epmp is correctly enabled. Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac4a6c7eec..b37b9107cd 100644 ---

[PATCH v4 31/33] hw/arm/sbsa-ref: Check CPU type in machine_run_board_init()

Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Leif Lindholm --- hw/arm/sbsa-ref.c | 21 +++-- 1 file

[PATCH v4 28/33] machine: Print CPU model name instead of CPU type name

The names of supported CPU models instead of CPU types should be printed when the user specified CPU type isn't supported, to be consistent with the output from '-cpu ?'. Correct the error messages to print CPU model names instead of CPU type names. Signed-off-by: Gavin Shan ---

[PATCH v4 12/33] target/m68k: Use generic helper to show CPU model names

For target/m68k, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Signed-off-by: Gavin Shan --- target/m68k/helper.c | 14 ++ 1 file changed, 6 insertions(+), 8 deletions(-) diff --git

[PATCH 0/2] RISC-V: OpenTitan: Fixup ePMP and SPI interrupts

Fixup the Ibex CPU priv version so that smepmp/epmp is correctly enabled and make a small change to the SPI interrupt generation to ensure we don't miss interrupts. Alistair Francis (2): hw/ssi: ibex_spi_host: Clear the interrupt even if disabled target/riscv: cpu: Set the OpenTitan priv to

[PATCH v4 26/33] machine: Use error handling when CPU type is checked

QEMU will be terminated if the specified CPU type isn't supported in machine_run_board_init(). The list of supported CPU type names is tracked by mc->valid_cpu_types. The error handling can be used to propagate error messages, to be consistent how the errors are handled for other situations in

[PATCH v4 15/33] target/ppc: Use generic helper to show CPU model names

For target/ppc, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Signed-off-by: Gavin Shan Reviewed-by: Cédric Le Goater --- target/ppc/cpu_init.c | 12 ++-- 1 file changed, 6 insertions(+),

[PATCH v4 32/33] hw/arm: Check CPU type in machine_run_board_init()

Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do it by ourselves. Signed-off-by: Gavin Shan --- hw/arm/bananapi_m2u.c | 12 ++-- hw/arm/cubieboard.c | 12 ++-- hw/arm/mps2-tz.c| 20

[PATCH v4 24/33] cpu: Mark cpu_list() supported on all targets

Remove the false conditions and comments since cpu_list() has been supported on all targets. Signed-off-by: Gavin Shan --- bsd-user/main.c | 3 --- cpu-target.c| 3 --- 2 files changed, 6 deletions(-) diff --git a/bsd-user/main.c b/bsd-user/main.c index c402fadf46..d3612ef0f5 100644 ---

[PATCH v4 17/33] target/rx: Use generic helper to show CPU model names

For target/rx, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Signed-off-by: Gavin Shan --- target/rx/cpu.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/rx/cpu.c

[PATCH v4 30/33] hw/arm/virt: Hide host CPU model for tcg

The 'host' CPU model isn't available until KVM or HVF is enabled. For example, the following error messages are seen when the guest is started with option '-cpu cortex-a8' on tcg. ERROR:../hw/core/machine.c:1423:is_cpu_type_supported: \ assertion failed: (model != NULL) Bail out!

[PATCH v4 27/33] machine: Introduce helper is_cpu_type_supported()

The logic, to check if the specified CPU type is supported in machine_run_board_init(), is independent enough. Factor it out into helper is_cpu_type_supported(). machine_run_board_init() looks a bit clean with this. Since we're here, @machine_class is renamed to @mc to avoid multiple line spanning

[PATCH v4 23/33] target/nios2: Implement nios2_cpu_list()

Implement nios2_cpu_list() to support cpu_list(). With this applied, the available CPU model names, same to the CPU type names, are shown as below. $ ./build/qemu-system-nios2 -cpu ? Available CPUs: nios2-cpu Signed-off-by: Gavin Shan --- target/nios2/cpu.c | 20

[PATCH v4 16/33] target/riscv: Use generic helper to show CPU model names

For target/riscv, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Besides, @cpuname is renamed to @model in riscv_cpu_class_by_name() since it points to CPU model name instead of CPU type name.

[PATCH v4 22/33] target/microblaze: Implement microblaze_cpu_list()

Implement microblaze_cpu_list() to support cpu_list(). With this applied, the available CPU model names, same to the CPU type names, are shown as below. $ ./build/qemu-system-hppa -cpu ? Available CPUs: microblaze-cpu Signed-off-by: Gavin Shan --- target/microblaze/cpu.c | 20

[PATCH v4 08/33] target/cris: Use generic helper to show CPU model names

For target/cris, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Signed-off-by: Gavin Shan --- target/cris/cpu.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-) diff --git

[PATCH v4 20/33] target/tricore: Use generic helper to show CPU model names

For target/tricore, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Signed-off-by: Gavin Shan Reviewed-by: Bastian Koppelmann --- target/tricore/helper.c | 13 + 1 file changed, 5

[PATCH v4 10/33] target/i386: Use generic helper to show CPU model names

For target/i386, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to convert the CPU type name to the CPU model name. Signed-off-by: Gavin Shan --- target/i386/cpu.c | 7 +++ 1 file changed, 3 insertions(+), 4 deletions(-)

[PATCH v4 29/33] hw/arm/virt: Check CPU type in machine_run_board_init()

Set mc->valid_cpu_types so that the user specified CPU type can be validated in machine_run_board_init(). We needn't to do the check by ourselves. Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 21 +++-- 1 file changed, 3 insertions(+), 18

[PATCH v4 25/33] machine: Constify MachineClass::valid_cpu_types[i]

Constify MachineClass::valid_cpu_types[i], as suggested by Richard Henderson. Suggested-by: Richard Henderson Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daudé --- hw/m68k/q800.c | 2 +- include/hw/boards.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git

[PATCH v4 21/33] target/hppa: Implement hppa_cpu_list()

Implement hppa_cpu_list() to support cpu_list(). With this applied, the available CPU model names, same to the CPU type names, are shown as below. $ ./build/qemu-system-hppa -cpu ? Available CPUs: hppa-cpu Signed-off-by: Gavin Shan --- target/hppa/cpu.c | 19 +++

[PATCH v4 13/33] target/mips: Use generic helper to show CPU model names

For target/mips, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Besides, mips_cpu_list() is reimplemented to dynamically fetch the CPU model names from the registered CPU types , instead of the

[PATCH v4 18/33] target/s390x: Use generic helper to show CPU model names

For target/s390x, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Signed-off-by: Gavin Shan --- target/s390x/cpu_models.c| 12 ++-- target/s390x/cpu_models_sysemu.c | 9 - 2

[PATCH v4 19/33] target/sh4: Use generic helper to show CPU model names

For target/sh4, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Besides, superh_cpu_class_by_name() is improved by avoiding "goto out" tag and renaming @s to @model since it points to CPU model name.

[PATCH v4 06/33] target/arm: Use generic helper to show CPU model names

For target/arm, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. In arm_cpu_list_entry(), @name is renamed to @model since it points to CPU model name instead of CPU type name. Signed-off-by: Gavin Shan

[PATCH v4 14/33] target/openrisc: Use generic helper to show CPU model names

For target/openrisc, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Signed-off-by: Gavin Shan --- target/openrisc/cpu.c | 14 +- 1 file changed, 5 insertions(+), 9 deletions(-) diff

[PATCH v4 09/33] target/hexagon: Use generic helper to show CPU model names

For target/hexagon, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Signed-off-by: Gavin Shan --- target/hexagon/cpu.c | 12 +--- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git

[PATCH v4 02/33] hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name()

From: Philippe Mathieu-Daudé Let CPUClass::class_by_name() handlers to return abstract classes, and filter them once in the public cpu_class_by_name() method. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Gavin Shan --- hw/core/cpu-common.c | 8 +++- include/hw/core/cpu.h | 7

[PATCH v4 04/33] cpu: Add helper cpu_model_from_type()

Add helper cpu_model_from_type() to extract the CPU model name from the CPU type name in two circumstances: (1) The CPU type name is the combination of the CPU model name and suffix. (2) The CPU type name is same to the CPU model name. The helper will be used in the subsequent commits to conver

[PATCH v4 07/33] target/avr: Use generic helper to show CPU model names

For target/avr, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names. Besides, the conversion from CPU model name to CPU type name needs to be supported in avr_cpu_class_by_name(). Signed-off-by: Gavin Shan

[PATCH v4 05/33] target/alpha: Use generic helper to show CPU model names

For target/alpha, the registered CPU type name is always the combination of the CPU model name and suffix. Use cpu_model_from_type() to show the CPU model names instead of the CPU type names. Signed-off-by: Gavin Shan --- target/alpha/cpu.c | 6 -- 1 file changed, 4 insertions(+), 2

[PATCH v4 03/33] cpu: Call object_class_dynamic_cast() once in cpu_class_by_name()

From: Philippe Mathieu-Daudé For all targets, the CPU class returned from CPUClass::class_by_name() and object_class_dynamic_cast(oc, CPU_RESOLVING_TYPE) need to be compatible. Lets apply the check in cpu_class_by_name() for once, instead of having the check in CPUClass::class_by_name() for

[PATCH v4 00/33] Unified CPU type check

There are two places where the user specified CPU type is checked to see if it's supported or allowed by the board: machine_run_board_init() and mc->init(). We don't have to maintain two duplicate sets of logic. This series intends to move the check to machine_run_board_init() so that we have

[PATCH v4 01/33] target/alpha: Tidy up alpha_cpu_class_by_name()

From: Philippe Mathieu-Daudé For target/alpha, the default CPU model name is "ev67". The default CPU model is used when no matching CPU model is found. The conditions to fall back to the default CPU model can be combined so that the code looks a bit simplified. Signed-off-by: Philippe

Re: [QEMU][PATCH v1] Xen: Fix xen_set_irq() and xendevicemodel_set_irq_level()

On Wed, 1 Nov 2023, Vikram Garhwal wrote: > Remove '=' from 'if CONFIG_XEN_CTRL_INTERFACE_VERSION <= 41500'. > Because xendevicemodel_set_irq_level() was introduced in 4.15 version. > > Also, update xendevicemodel_set_irq_level() to return -1 for older versions. > > Signed-off-by: Vikram Garhwal

Re: [PATCH 0/6] Various tracing patches

Am 31. Oktober 2023 16:17:32 UTC schrieb Peter Maydell : >On Sat, 28 Oct 2023 at 13:24, Bernhard Beschow wrote: >> >> This series enhances the tracing experience of some i.MX devices by adding >> new >> trace events and by converting from DPRINTF. SMBus gets also converted from >> DPRINTF to

Re: [PATCH v4 04/14] tpm_crb: use a single read-as-mem/write-as-mmio mapping

On 10/31/23 00:00, Joelle van Dyne wrote: On Apple Silicon, when Windows performs a LDP on the CRB MMIO space, the exception is not decoded by hardware and we cannot trap the MMIO read. This led to the idea from @agraf to use the same mapping type as ROM devices: namely that reads should be

Re: [PATCH 1/7] spapr/pci: Correct "does not support hotplugging error messages

On Wed, 1 Nov 2023, Daniel Henrique Barboza wrote: On 10/31/23 08:10, Markus Armbruster wrote: When dynamic-reconfiguration is off, hot plug / unplug can fail with "Bus 'spapr-pci-host-bridge' does not support hotplugging". spapr-pci-host-bridge is a device, not a bus. Report the name of the

[QEMU][PATCH v1] Xen: Fix xen_set_irq() and xendevicemodel_set_irq_level()

Remove '=' from 'if CONFIG_XEN_CTRL_INTERFACE_VERSION <= 41500'. Because xendevicemodel_set_irq_level() was introduced in 4.15 version. Also, update xendevicemodel_set_irq_level() to return -1 for older versions. Signed-off-by: Vikram Garhwal --- hw/arm/xen_arm.c| 4 +++-

Re: [PATCH 1/7] spapr/pci: Correct "does not support hotplugging error messages

On 10/31/23 08:10, Markus Armbruster wrote: When dynamic-reconfiguration is off, hot plug / unplug can fail with "Bus 'spapr-pci-host-bridge' does not support hotplugging". spapr-pci-host-bridge is a device, not a bus. Report the name of the bus it provides instead: 'pci.0'. Signed-off-by:

[PATCH v2 0/4] Misc ati-vga patches

Changes in v2: - Add HOST_PATH_CNTL reg in patch 1 to match Linux vram size calculation - Add a new patch to implement pixman fallbacks for ati-vga that should help with the series that make pixman optional. Some misc patches I had laying around that could be upstreamed just to clean up my tree a

[PATCH v2 3/4] ati-vga: Add 30 bit palette access register

Radeon cards have a 30 bit DAC and corresponding palette register to access it. We only use 8 bits but let the guests use 10 bit color values for those that access it through this register. Signed-off-by: BALATON Zoltan --- hw/display/ati.c | 9 + hw/display/ati_dbg.c | 1 +

[PATCH v8 11/19] target/riscv/kvm: add 'rva22u64' flag as unavailable

KVM does not have the means to support enabling the rva22u64 profile. The main reasons are: - we're missing support for some mandatory rva22u64 extensions in the KVM module; - we can't make promises about enabling a profile since it all depends on host support in the end. We'll revisit this

[PATCH v8 05/19] target/riscv/tcg: update priv_ver on user_set extensions

We'll add a new bare CPU type that won't have any default priv_ver. This means that the CPU will default to priv_ver = 0, i.e. 1.10.0. At the same we'll allow these CPUs to enable extensions at will, but then, if the extension has a priv_ver newer than 1.10, we'll end up disabling it. Users will

[PATCH v8 13/19] target/riscv/tcg: add MISA user options hash

We already track user choice for multi-letter extensions because we needed to honor user choice when enabling/disabling extensions during realize(). We refrained from adding the same mechanism for MISA extensions since we didn't need it. Profile support requires tne need to check for user choice

[PATCH v2 4/4] ati-vga: Implement fallback for pixman routines

Pixman routines can fail if no implementation is available and it will become optional soon so add fallbacks when pixman does not work. Signed-off-by: BALATON Zoltan --- hw/display/ati.c | 8 + hw/display/ati_2d.c | 75 +++- hw/display/ati_int.h

[PATCH v2 2/4] ati-vga: Support unaligned access to GPIO DDC registers

The GPIO_VGA_DDC and GPIO_DVI_DDC registers are used on Radeon for DDC access. Some drivers like the PPC Mac FCode ROM uses unaligned writes to these registers so implement this the same way as already done for GPIO_MONID which is used the same way for the Rage 128 Pro. Signed-off-by: BALATON

[PATCH v2 1/4] ati-vga: Fix aperture sizes

Apparently these should be half the memory region sizes confirmed at least by Radeon FCocde ROM while Rage 128 Pro ROMs don't seem to use these. Linux r100 DRM driver also checks for a bit in HOST_PATH_CNTL so we also add that even though the FCode ROM does not seem to set it. Signed-off-by:

[PATCH v8 18/19] target/riscv/tcg: validate profiles during finalize

Enabling a profile and then disabling some of its mandatory extensions is a valid use. It can be useful for debugging and testing. But the common expected use of enabling a profile is to enable all its mandatory extensions. Add an user warning when mandatory extensions from an enabled profile are

[PATCH v8 16/19] target/riscv/tcg: add hash table insert helpers

Previous patches added several g_hash_table_insert() patterns. Add two helpers, one for each user hash, to make the code cleaner. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Andrew Jones --- target/riscv/tcg/tcg-cpu.c | 28 1 file changed, 16 insertions(+),

[PATCH v8 03/19] target/riscv/cpu.c: set satp_max_supported in cpu_riscv_set_satp()

The setter() for the boolean attributes that set satp_mode (sv32, sv39, sv48, sv57, sv64) considers that the CPU will always do a set_satp_mode_max_supported() during cpu_init(). This is not the case for the KVM 'host' CPU, and we'll add another CPU that won't set satp_mode_max() during

[PATCH] tests/avocado: Allow newer versions of tesseract in the nextcube test

Current Linux distros ship version 5 of the tesseract OCR software, so the nextcube screen test is ignored there. Let's make the check more flexible to allow newer versions, too, and remove the old v3 test since most Linux distros don't ship this version anymore. Signed-off-by: Thomas Huth ---

[PATCH v8 09/19] riscv-qmp-cmds.c: expose named features in cpu_model_expansion

Named features (zic64b the sole example at this moment) aren't expose to users, thus we need another way to expose them. Go through each named feature, get its boolean value, do the needed conversions (bool to qbool, qbool to QObject) and add it to output dict. Another adjustment is needed:

[PATCH v8 08/19] target/riscv/tcg: add 'zic64b' support

zic64b is defined in the RVA22U64 profile [1] as a named feature for "Cache blocks must be 64 bytes in size, naturally aligned in the address space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64 profile mandates this feature, meaning that applications using this profile expects 64

[PATCH v8 06/19] target/riscv: add rv64i CPU

We don't have any form of a 'bare bones' CPU. rv64, our default CPUs, comes with a lot of defaults. This is fine for most regular uses but it's not suitable when more control of what is actually loaded in the CPU is required. A bare-bones CPU would be annoying to deal with if not by profile

[PATCH v8 01/19] target/riscv: create TYPE_RISCV_VENDOR_CPU

We want to add a new CPU type for bare CPUs that will inherit specific traits of the 2 existing types: - it will allow for extensions to be enabled/disabled, like generic CPUs; - it will NOT inherit defaults, like vendor CPUs. We can make this conditions met by adding an explicit type for the

[PATCH v8 00/19] rv64i CPU, RVA22U64 profile support

Hi, This v8 contains a few more extra, trivial changes, related to the design of the rv64i. We stripped away all its defaults, including priv_ver and satp mode. Handling priv_ver was somewhat trivial: profiles and regular extensions that are user set will now bump the CPU priv_ver if needed.

[PATCH v8 14/19] target/riscv/tcg: add riscv_cpu_write_misa_bit()

We have two instances of the setting/clearing a MISA bit from env->misa_ext and env->misa_ext_mask pattern. And the next patch will end up adding one more. Create a helper to avoid code repetition. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Reviewed-by: LIU Zhiwei

[PATCH v8 19/19] riscv-qmp-cmds.c: add profile flags in cpu-model-expansion

Expose all profile flags for all CPUs when executing query-cpu-model-expansion. This will allow callers to quickly determine if a certain profile is implemented by a given CPU. This includes vendor CPUs - the fact that they don't have profile user flags doesn't mean that they don't implement the

[PATCH v8 07/19] target/riscv: add zicbop extension flag

QEMU already implements zicbom (Cache Block Management Operations) and zicboz (Cache Block Zero Operations). Commit 59cb29d6a5 ("target/riscv: add Zicbop cbo.prefetch{i, r, m} placeholder") added placeholders for what would be the instructions for zicbop (Cache Block Prefetch Operations), which

[PATCH v8 15/19] target/riscv/tcg: handle profile MISA bits

The profile support is handling multi-letter extensions only. Let's add support for MISA bits as well. We'll go through every known MISA bit. If the profile doesn't declare the bit as mandatory, ignore it. Otherwise, set the bit in env->misa_ext and env->misa_ext_mask. Now that we're setting

[PATCH v8 17/19] target/riscv/tcg: honor user choice for G MISA bits

RVG behaves like a profile: a single flag enables a set of bits. Right now we're considering user choice when handling RVG and zicsr/zifencei and ignoring user choice on MISA bits. We'll add user warnings for profiles when the user disables its mandatory extensions in the next patch. We'll do the

[PATCH v8 12/19] target/riscv/tcg: add user flag for profile support

The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand. Given that this is the first profile we're implementing in TCG

[PATCH v8 04/19] target/riscv/cpu.c: set satp_mode_max MBARE during satp_finalize()

KVM CPUs can handle "cpu->cfg.satp_mode.supported == 0" because KVM will make it do internally, not requiring the current SATP support from TCG. But other TCG CPUs doesn't deal well with it. We'll assert out before OpenSBI if the CPU doesn't set a default:

[PATCH v8 02/19] target/riscv/tcg: do not use "!generic" CPU checks

Our current logic in get/setters of MISA and multi-letter extensions works because we have only 2 CPU types, generic and vendor, and by using "!generic" we're implying that we're talking about vendor CPUs. When adding a third CPU type this logic will break so let's handle it beforehand. In

[PATCH v8 10/19] target/riscv: add rva22u64 profile definition

The rva22U64 profile, described in: https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles Contains a set of CPU extensions aimed for 64-bit userspace applications. Enabling this set to be enabled via a single user flag makes it convenient to enable a predictable set of

[PATCH] tests/avocado/machine_m68k_nextcube: Fix the download URL for the ROM image

If Avocado has to fetch this asset, the download fails with a 403 HTTP error. Use a different URL to fix the issue. Signed-off-by: Thomas Huth --- tests/avocado/machine_m68k_nextcube.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [PATCH] block-jobs: add final flush

On 31.10.23 17:05, Hanna Czenczek wrote: On 04.10.23 15:56, Vladimir Sementsov-Ogievskiy wrote: From: Vladimir Sementsov-Ogievskiy Actually block job is not completed without the final flush. It's rather unexpected to have broken target when job was successfully completed long ago and now we

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