Richard Henderson writes:
> The contents of IIAOQ depend on PSW_W.
> Follow the text in "Interruption Instruction Address Queues",
> pages 2-13 through 2-15.
>
> Reported-by: Sven Schnelle
> Fixes: b10700d826c ("target/hppa: Update IIAOQ, IIASQ for pa2.0")
> Signed-off-by: Richard Henderson
>
On 02/04/2024 12:09, fan wrote:
> On Tue, Apr 02, 2024 at 09:46:46AM +0800, Li Zhijian via wrote:
>> It helps to figure out where the first dvsec register is located. In
>> addition, replace offset and size hardcore with existing macros.
>>
>> Signed-off-by: Li Zhijian
>> ---
>>
When vhost-user or vhost-kernel is handling virtio net datapath, qemu
should not touch used ring.
But with vhost-user socket reconnect scenario, in a very rare case (has
pending kick event). VRING_USED_F_NO_NOTIFY is set by qemu in
following code path:
#0
Hi,
On Monday, April 1, 2024 11:53:11 PM IST daleyoung4...@gmail.com wrote:
> Hi,
>
> On Monday, March 25, 2024 21:20:32 CST Sahil wrote:
> > Q1.
> > Section 2.7.4 of the virtio spec [3] states that in an available
> > descriptor, the "Element Length" stores the length of the buffer element.
> >
On Tue, Apr 02, 2024 at 09:46:46AM +0800, Li Zhijian via wrote:
> It helps to figure out where the first dvsec register is located. In
> addition, replace offset and size hardcore with existing macros.
>
> Signed-off-by: Li Zhijian
> ---
> hw/mem/cxl_type3.c | 19 +--
> 1 file
On 2024/3/29 18:44, Michael S. Tsirkin wrote:
> On Fri, Mar 29, 2024 at 03:20:59PM +0800, Jason Wang wrote:
>> On Fri, Mar 29, 2024 at 3:07 PM Chen, Jiqian wrote:
>>>
>>> On 2024/3/28 20:36, Michael S. Tsirkin wrote:
>>> +}
>>> +
>>> static void virtio_pci_bus_reset_hold(Object *obj)
On 2024/3/29 18:38, Jason Wang wrote:
> On Fri, Mar 29, 2024 at 4:00 PM Chen, Jiqian wrote:
>>
>> On 2024/3/29 15:20, Jason Wang wrote:
>>> On Fri, Mar 29, 2024 at 3:07 PM Chen, Jiqian wrote:
On 2024/3/28 20:36, Michael S. Tsirkin wrote:
+}
+
static void
It helps to figure out where the first dvsec register is located. In
addition, replace offset and size hardcore with existing macros.
Signed-off-by: Li Zhijian
---
hw/mem/cxl_type3.c | 19 +--
1 file changed, 13 insertions(+), 6 deletions(-)
diff --git a/hw/mem/cxl_type3.c
After the kernel commit
0cab68720598 ("cxl/pci: Fix disabling memory if DVSEC CXL Range does not match
a CFMWS window")
CXL type3 devices cannot be enabled again after the reboot because this
flag was not reset.
This flag could be changed by the firmware or OS, let it have a
reset(default) value
The contents of IIAOQ depend on PSW_W.
Follow the text in "Interruption Instruction Address Queues",
pages 2-13 through 2-15.
Reported-by: Sven Schnelle
Fixes: b10700d826c ("target/hppa: Update IIAOQ, IIASQ for pa2.0")
Signed-off-by: Richard Henderson
---
Sven, I looked again through IIAOQ
The current implementation treats emulated memory devices, such as
CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
(E820_TYPE_RAM). However, these emulated devices have different
characteristics than traditional DRAM, making it important to
distinguish them. Thus, we
Since different memory devices require finding, allocating, and putting
memory types, these common steps are abstracted in this patch,
enhancing the scalability and conciseness of the code.
Signed-off-by: Ho-Ren (Jack) Chuang
Reviewed-by: "Huang, Ying"
---
drivers/dax/kmem.c | 20
When a memory device, such as CXL1.1 type3 memory, is emulated as
normal memory (E820_TYPE_RAM), the memory device is indistinguishable from
normal DRAM in terms of memory tiering with the current implementation.
The current memory tiering assigns all detected normal memory nodes to
the same DRAM
Hi SeongJae,
On Mon, Apr 1, 2024 at 11:27 AM Ho-Ren (Jack) Chuang
wrote:
>
> Hi SeongJae,
>
> On Sun, Mar 31, 2024 at 12:09 PM SeongJae Park wrote:
> >
> > Hi Ho-Ren,
> >
> > On Fri, 29 Mar 2024 05:33:52 + "Ho-Ren (Jack) Chuang"
> > wrote:
> >
> > > Since different memory devices require
Richard Henderson writes:
> On 4/1/24 10:39, Sven Schnelle wrote:
>> Richard Henderson writes:
For unknown reasons, Java 1.5 on 64-bit HP-UX 11.11 does signed
computation of the new IAOQ value in the signal handler. In the
current code these bits are not masked when returning to
Hello Peter und Zhjian,
Thank you so much for letting me know about this. I'm also a bit surprised at
the plan for deprecating the RDMA migration subsystem.
> IMHO it's more important to know whether there are still users and whether
> they would still like to see it around.
> I admit RDMA
Peter Xu writes:
> On Mon, Apr 01, 2024 at 02:17:28PM -0300, Fabiano Rosas wrote:
>> Peter Xu writes:
>>
>> > On Fri, Mar 29, 2024 at 08:54:07AM +, Wang, Wei W wrote:
>> >> On Friday, March 29, 2024 11:32 AM, Wang, Lei4 wrote:
>> >> > When using the post-copy preemption feature to perform
On 4/1/24 10:39, Sven Schnelle wrote:
Richard Henderson writes:
On 4/1/24 04:52, Sven Schnelle wrote:
For unknown reasons, Java 1.5 on 64-bit HP-UX 11.11 does signed
computation of the new IAOQ value in the signal handler. In the
current code these bits are not masked when returning to
On 4/1/24 10:56, Sven Schnelle wrote:
This seems to be caused by IIAOQ's containing the upper bits. With the
patch below i'm able to boot. Not sure whether it's correct though.
diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c
index 58c13d3e61..f7c4cca8f1 100644
---
Sven Schnelle writes:
> Sven Schnelle writes:
>
>> Richard Henderson writes:
>>
>>> On 4/1/24 04:52, Sven Schnelle wrote:
For unknown reasons, Java 1.5 on 64-bit HP-UX 11.11 does signed
computation of the new IAOQ value in the signal handler. In the
current code these bits are
Sven Schnelle writes:
> Richard Henderson writes:
>
>> On 4/1/24 04:52, Sven Schnelle wrote:
>>> For unknown reasons, Java 1.5 on 64-bit HP-UX 11.11 does signed
>>> computation of the new IAOQ value in the signal handler. In the
>>> current code these bits are not masked when returning to
Richard Henderson writes:
> On 4/1/24 04:52, Sven Schnelle wrote:
>> For unknown reasons, Java 1.5 on 64-bit HP-UX 11.11 does signed
>> computation of the new IAOQ value in the signal handler. In the
>> current code these bits are not masked when returning to narrow
>> mode, causing java to
> On 1 Apr 2024, at 23:04, Marcin Juszkiewicz
> wrote:
>
> So ask Ubuntu Pro team for support?
I did not ask for support, I just notified the community of an issue I
encountered while building the latest sources, driven by a sincere desire to
improve the project.
If this bothered you, I
On 4/1/24 09:50, Gautam Bhat wrote:
Hi,
Some background: I am trying to write a CPU emulator for MSP430 with
Qemu. I am loading the MSP430 program as follows using the generic
device loader:
/qemu-system-msp430 -machine msp430-launchpad -device
loader,file=simple_test -d in_asm,out_asm
I have
W dniu 1.04.2024 o 21:55, Liviu Ionescu pisze:
On 1 Apr 2024, at 21:48, Richard
Henderson wrote:
You were told back in September that Ubuntu 18.04 is no longer
supported.
Sorry, I missed that.
BTW, according to ubuntu.com: "With Ubuntu Pro, the 18.04 LTS will be
fully supported until 2028.".
> On 1 Apr 2024, at 21:48, Richard Henderson
> wrote:
>
> You were told back in September that Ubuntu 18.04 is no longer supported.
Sorry, I missed that.
BTW, according to ubuntu.com: "With Ubuntu Pro, the 18.04 LTS will be fully
supported until 2028.".
Regards,
Liviu
Hi,
Some background: I am trying to write a CPU emulator for MSP430 with
Qemu. I am loading the MSP430 program as follows using the generic
device loader:
/qemu-system-msp430 -machine msp430-launchpad -device
loader,file=simple_test -d in_asm,out_asm
I have implemented somewhat the
On 4/1/24 08:08, Liviu Ionescu wrote:
same behaviour for 8.2.2; same workaround.
On 2 Sep 2023, at 21:11, Liviu Ionescu wrote:
When trying to build 8.1.0 on an Ubuntu 18.04 aarch64, I get the above error.
You were told back in September that Ubuntu 18.04 is no longer supported.
The passage
On Mon, Apr 01, 2024 at 02:17:28PM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Fri, Mar 29, 2024 at 08:54:07AM +, Wang, Wei W wrote:
> >> On Friday, March 29, 2024 11:32 AM, Wang, Lei4 wrote:
> >> > When using the post-copy preemption feature to perform post-copy live
> >> >
On Sun, 21 Jan 2024 21:50:00 -0500
Hyeonggon Yoo <42.hye...@gmail.com> wrote:
> On Tue, Jan 9, 2024 at 12:54 PM Jonathan Cameron
> wrote:
> >
> > On Fri, 22 Dec 2023 18:00:50 +0900
> > Hyeonggon Yoo <42.hye...@gmail.com> wrote:
> >
> > > The spec states that reads/writes should have no effect
On 4/1/24 04:52, Sven Schnelle wrote:
For unknown reasons, Java 1.5 on 64-bit HP-UX 11.11 does signed
computation of the new IAOQ value in the signal handler. In the
current code these bits are not masked when returning to narrow
mode, causing java to crash.
Signed-off-by: Sven Schnelle
---
Hi, I'm working on a v3 of my query-block series [1] and I'm a bit
confused about how to convert a QMP command into a coroutine.
In case you miss the context:
In that series I'm turning query-block into a coroutine so we can avoid
holding the BQL for too long in the case of a misbehaving
Hi SeongJae,
On Sun, Mar 31, 2024 at 12:09 PM SeongJae Park wrote:
>
> Hi Ho-Ren,
>
> On Fri, 29 Mar 2024 05:33:52 + "Ho-Ren (Jack) Chuang"
> wrote:
>
> > Since different memory devices require finding, allocating, and putting
> > memory types, these common steps are abstracted in this
Hi,
On Monday, March 25, 2024 21:20:32 CST Sahil wrote:
> Q1.
> Section 2.7.4 of the virtio spec [3] states that in an available descriptor,
> the "Element Length" stores the length of the buffer element. In the next
> few lines, it also states that the "Element Length" is reserved for used
>
same behaviour for 8.2.2; same workaround.
> On 2 Sep 2023, at 21:11, Liviu Ionescu wrote:
>
> When trying to build 8.1.0 on an Ubuntu 18.04 aarch64, I get the above error.
>
> The offending code in `/util/cpuinfo-aarch64.c` is:
>
> ```c
> #ifdef CONFIG_LINUX
>unsigned long hwcap =
Peter Xu writes:
> On Fri, Mar 29, 2024 at 08:54:07AM +, Wang, Wei W wrote:
>> On Friday, March 29, 2024 11:32 AM, Wang, Lei4 wrote:
>> > When using the post-copy preemption feature to perform post-copy live
>> > migration, the below scenario could lead to a deadlock and the migration
>> >
01.04.2024 12:43, liu.d...@zte.com.cn wrote:
hmp: Add help information for watchdog action: inject-nmi
virsh qemu-monitor-command --hmp help information of watchdog_action missing
inject-nmi which already supported in Commit 795dc6e4
Signed-off-by: Dayu Liu
Applied to trivial-patches tree,
On Mon, Apr 01, 2024 at 08:41:20PM +0800, Zhu Yangyang wrote:
> Coroutines are not supposed to block. Instead, they should yield.
>
> Fixes: f95910f ("nbd: implement TLS support in the protocol negotiation")
> Signed-off-by: Zhu Yangyang
> ---
> nbd/client.c | 7 ---
> nbd/common.c
On Mon, Apr 01, 2024 at 11:59:47AM +0800, Li Zhijian wrote:
> Except for RDMA migration, other parts of the RDMA subsystem have been
> removed since 9.1.
>
> Due to the lack of unit tests and CI tests for RDMA migration, int the
> past developing cycles, a few fatal errors were introduced and
On Fri, Mar 29, 2024 at 08:54:07AM +, Wang, Wei W wrote:
> On Friday, March 29, 2024 11:32 AM, Wang, Lei4 wrote:
> > When using the post-copy preemption feature to perform post-copy live
> > migration, the below scenario could lead to a deadlock and the migration
> > will
> > never finish:
>
On Thu, 28 Mar 2024 16:54:16 +0100
Philippe Mathieu-Daudé wrote:
> CXL depends on PCIe, which isn't available on non-PCI
> machines such the ISA-only PC one.
> Move CXLState to PcPciMachineState, and move the CXL
> specific calls to pc_pci_machine_initfn() and
> pc_pci_machine_done().
>
>
On Wed, 27 Mar 2024 17:16:42 +0100
Philippe Mathieu-Daudé wrote:
> CXL is based on PCIe. In is pointless to initialize
> its context on non-PCI machines.
>
> Signed-off-by: Philippe Mathieu-Daudé
Seems a reasonable restriction.
Acked-by: Jonathan Cameron
Jonathan
> ---
> hw/i386/pc.c | 4
On Thu, 28 Mar 2024 06:24:24 +
"Xingtao Yao (Fujitsu)" wrote:
> Jonathan
>
> thanks for your reply!
>
> > -Original Message-
> > From: Jonathan Cameron
> > Sent: Wednesday, March 27, 2024 9:28 PM
> > To: Yao, Xingtao/姚 幸涛
> > Cc: fan...@samsung.com; qemu-devel@nongnu.org; Cao,
Hi Andrey,
I am ok with these changes.
No need new iteration with the version change, I will update before merging.
I will merge it after release.
Best Regards,
Konstantin Kostiuk.
On Mon, Apr 1, 2024 at 5:49 PM Andrey Drobyshev <
andrey.drobys...@virtuozzo.com> wrote:
> On 3/22/24 15:17,
Bryan Zhang writes:
> Uses QAT to offload deflate compression and decompression in the
> 'qatzip' compression method for multifd migration.
Please merge this patch with the previous. It makes no sense to have a
commit that adds nocomp code to qatzip only to have the next commit
replace it all.
Bryan Zhang writes:
> Adds an integration test for 'qatzip'.
>
> Signed-off-by: Bryan Zhang
> Signed-off-by: Hao Xiang
Reviewed-by: Fabiano Rosas
Bryan Zhang writes:
> Adds support for migration parameters to control QATzip compression
> level and to enable/disable software fallback when QAT hardware is
> unavailable. This is a preparatory commit for a subsequent commit that
> will actually use QATzip compression.
>
> Signed-off-by: Bryan
On Sun, 31 Mar 2024 16:20:30 -0400 Michael S. Tsirkin wrote:
> > Fixes: c7114b1249fa ("drivers/net/virtio_net: Added basic RSS support.")
> > Cc: sta...@vger.kernel.org
>
> net has its own stable process, don't CC stable on net patches.
Not any more, FWIW:
1.5.7. Stable tree
While it
On 3/23/2024 2:11 AM, Paolo Bonzini wrote:
From: Sean Christopherson
Move the architectural (for lack of a better term) CPUID leaf generation
to a separate helper so that the generation code can be reused by TDX,
which needs to generate a canonical VM-scoped configuration.
For now this is
On 3/22/24 15:17, Andrey Drobyshev wrote:
> On 3/22/24 12:39, Daniel P. Berrangé wrote:
>> On Wed, Mar 20, 2024 at 06:16:42PM +0200, Andrey Drobyshev wrote:
>>> Since the commit 25b5ff1a86 ("qga: add mountpoint usage info to
>>> GuestFilesystemInfo") we have 2 values reported in guest-get-fsinfo:
For unknown reasons, Java 1.5 on 64-bit HP-UX 11.11 does signed
computation of the new IAOQ value in the signal handler. In the
current code these bits are not masked when returning to narrow
mode, causing java to crash.
Signed-off-by: Sven Schnelle
---
target/hppa/sys_helper.c | 4
1 file
On Mon, 1 Apr 2024 at 06:17, Michael Tokarev wrote:
>
> Commit ab72522797 "gitlab: switch from 'stable' to
> 'latest' docker container tags" switched most tags
> to 'latest' but missed cirrus image. Fix this now.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2256
> Signed-off-by:
On Sun, 31 Mar 2024 at 19:32, wrote:
>
> From: Peter Xu
>
> The following changes since commit b9dbf6f9bf533564f6a4277d03906fcd32bb0245:
>
> Merge tag 'pull-tcg-20240329' of https://gitlab.com/rth7680/qemu into
> staging (2024-03-30 14:54:57 +)
>
> are available in the Git repository at:
On Fri, Mar 29, 2024 at 11:56:27AM +0100, Cédric Le Goater wrote:
> This allows to report more precise errors in the migration handler
> dirty_bitmap_save_setup().
>
> Suggested-by Vladimir Sementsov-Ogievskiy
> Signed-off-by: Cédric Le Goater
> ---
>
> To apply on top of :
>
On 07.03.24 16:47, Fiona Ebner wrote:
Backup supports all modes listed in MirrorSyncMode, while mirror does
not. Introduce BackupSyncMode by copying the current MirrorSyncMode
and drop the variants mirror does not support from MirrorSyncMode as
well as the corresponding manual check in
hmp: Add help information for watchdog action: inject-nmi
virsh qemu-monitor-command --hmp help information of watchdog_action missing
inject-nmi which already supported in Commit 795dc6e4
Signed-off-by: Dayu Liu
---
hmp-commands.hx | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Use qemu_fdt_setprop_u64() instead of qemu_fdt_setprop_cell()
to set the address of initrd in FDT to support 64-bit address.
Signed-off-by: Cheng Yang
---
hw/riscv/boot.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index
Coroutines are not supposed to block. Instead, they should yield.
Fixes: f95910f ("nbd: implement TLS support in the protocol negotiation")
Signed-off-by: Zhu Yangyang
---
nbd/client.c | 7 ---
nbd/common.c | 19 ---
nbd/nbd-internal.h | 6 +++---
nbd/server.c
The problem that inserting duplicate coroutine to co_queue_wakeu has been
resolved by 7c1f51bf38 ("nbd/server: Fix drained_poll to wake coroutine
in right AioContext") that avoids repeatedly waking up the same coroutine.
The key modifications are as follows:
static void
On Fri, 29 Mar 2024 at 22:32, Richard Henderson
wrote:
>
> The following changes since commit 5012e522aca161be5c141596c66e5cc6082538a9:
>
> Update version for v9.0.0-rc1 release (2024-03-26 19:46:55 +)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git
On Sun, 31 Mar 2024 at 08:34, Nicholas Piggin wrote:
>
> The following changes since commit 5012e522aca161be5c141596c66e5cc6082538a9:
>
> Update version for v9.0.0-rc1 release (2024-03-26 19:46:55 +)
>
> are available in the Git repository at:
>
> https://gitlab.com/npiggin/qemu.git
On Sat, 30 Mar 2024 at 13:39, Christian Schoenebeck
wrote:
>
> The following changes since commit 5012e522aca161be5c141596c66e5cc6082538a9:
>
> Update version for v9.0.0-rc1 release (2024-03-26 19:46:55 +)
>
> are available in the Git repository at:
>
>
在 2024/3/30 9:37, Dan Williams 写道:
Shiyang Ruan wrote:
The length of Physical Address in General Media Event Record/DRAM Event
Record is 64-bit, so the field mask should be defined as such length.
Otherwise, this causes cxl_general_media and cxl_dram tracepoints to
mask off the upper-32-bits
On 4/1/2024 4:34 PM, Li Feng wrote:
*External email: Use caution opening links or attachments*
Hi yajun,
I have submitted a patch to fix this problem a few months ago, but in
the end this solution was not accepted and other solutions
were adopted to fix it.
[PATCH 1/2] vhost-user: fix
Hi yajun,
I have submitted a patch to fix this problem a few months ago, but in the end
this solution was not accepted and other solutions
were adopted to fix it.
https://lore.kernel.org/all/20230804052954.2918915-2-fen...@smartx.com/
This is the merged fix:
Hello Aditya,
Please run ./scripts/get_maintainer.pl when sending a series. qemu-ppc should be
in Cc:
Briefly looking at this, please separate the changes using one patch per model,
that is : first CPU (target), LPC, OCC, PSI, SBE, PnvCore, SpaprCore. Last the
PnvChip and the machines,
On Thu, 28 Mar 2024 07:40:14 -0500, Eric Blake wrote:
> On Mon, Mar 25, 2024 at 05:18:50PM +0800, zhuyangyang via wrote:
> > If g_main_loop_run()/aio_poll() is called in the coroutine context,
> > the pending coroutine may be woken up repeatedly, and the co_queue_wakeup
> > may be disordered.
> >
Phil,
on 3/29/2024 6:28 PM, Philippe Mathieu-Daudé wrote:
>>
>>
>>> IMHO it's more important to know whether there are still users and
>>> whether
>>> they would still like to see it around.
>>
>> Agree.
>> I didn't immediately express my opinion in V1 because I'm also
>> consulting our
>>
On Mon, Apr 01, 2024 at 10:08:10AM +0800, Yajun Wu wrote:
>
> On 3/27/2024 6:47 PM, Stefano Garzarella wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > Hi Yajun,
> >
> > On Mon, Mar 25, 2024 at 10:54:13AM +, Yajun Wu wrote:
> > > Hi experts,
> > >
> > > With
11.03.2024 10:58, Paolo Bonzini wrote:
The low bit of MMU indices for x86 TCG indicates whether the processor is
in 32-bit mode and therefore linear addresses have to be masked to 32 bits.
However, the index was computed incorrectly, leading to possible conflicts
in the TLB for any address above
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