[PATCH qemu v4 1/2] target/arm: Handle IC IVAU to improve compatibility with JITs

From: John Högberg Unlike architectures with precise self-modifying code semantics (e.g. x86) ARM processors do not maintain coherency for instruction execution and memory, requiring an instruction synchronization barrier on every core that will execute the new code, and on many models also the

[PATCH qemu v4 0/2] target/arm: Improve user-mode compatibility with JITs

Changes since v3: 1) Reworded the first commit comment to note that the need to clear cache is implementation-dependent. 2) CTR_EL0.DIC is now cleared in user mode to indicate that IC IVAU must be used. 3) The test case now only uses DC CVAU / IC IVAU when this is required, as indicated

[PATCH qemu v4 2/2] tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code

From: John Högberg https://gitlab.com/qemu-project/qemu/-/issues/1034 Signed-off-by: John Högberg --- tests/tcg/aarch64/Makefile.target | 3 +- tests/tcg/aarch64/icivau.c| 189 ++ 2 files changed, 191 insertions(+), 1 deletion(-) create mode 100644

[PATCH qemu v3 1/2] target/arm: Handle IC IVAU to improve compatibility with JITs

From: John Högberg Unlike architectures with precise self-modifying code semantics (e.g. x86) ARM processors do not maintain coherency for instruction execution and memory, and require the explicit use of cache management instructions as well as an instruction barrier to make code updates

[PATCH qemu v3 2/2] tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code

From: John Högberg https://gitlab.com/qemu-project/qemu/-/issues/1034 Signed-off-by: John Högberg --- tests/tcg/aarch64/Makefile.target | 3 +- tests/tcg/aarch64/icivau.c| 169 ++ 2 files changed, 171 insertions(+), 1 deletion(-) create mode 100644

[PATCH qemu v3 0/2] target/arm: Improve user-mode compatibility with JITs

The test cases have been changed in v3 to fix some issues pointed out in code review. The main change is that the tests no longer naively copy C code around, opting instead to have hard-coded binary payloads. Given the small amount of code I found that the workarounds for position- independence

[PATCH qemu v2 1/2] target/arm: Handle IC IVAU to improve compatibility with JITs

From: John Högberg Unlike architectures with precise self-modifying code semantics (e.g. x86) ARM processors do not maintain coherency for instruction execution and memory, and require the explicit use of cache management instructions as well as an instruction barrier to make code updates

[PATCH qemu v2 0/2] target/arm: Improve user-mode compatibility with JITs

The previous version of this got mangled, so I'm re-sending it through sourcehut as mentioned in the documentation in the hopes that it's foolproof. Sorry about the extra traffic :-( When running in user-mode QEMU currently fails to emulate JITs that use dual-mapped code to get around W^X

[PATCH qemu v2 2/2] tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code

From: John Högberg https://gitlab.com/qemu-project/qemu/-/issues/1034 Signed-off-by: John Högberg --- tests/tcg/aarch64/Makefile.target | 3 +- tests/tcg/aarch64/icivau.c| 204 ++ 2 files changed, 206 insertions(+), 1 deletion(-) create mode 100644