ress match
>>
>> - patch 10:
>> - add ATS steps in riscv_iommu_validate_device_ctx()
>> - check for 's->enable_ats' before adding RISCV_IOMMU_DC_TC_EN_ATS in
>> device context
>> - check for 's->enable_ats' before processing ATS commands in
>> riscv_
On Thu, May 30, 2024 at 01:05:41PM GMT, Andrew Jones wrote:
> On Thu, May 30, 2024 at 05:49:49AM GMT, Daniel Henrique Barboza wrote:
> > We need #address-cells properties in all interrupt controllers that are
> > referred by an interrupt-map [1]. For the RISC-V machine, both PLI
On Thu, May 30, 2024 at 05:49:49AM GMT, Daniel Henrique Barboza wrote:
> We need #address-cells properties in all interrupt controllers that are
> referred by an interrupt-map [1]. For the RISC-V machine, both PLIC and
> APLIC controllers must have this property.
>
> PLIC already sets it in
On Thu, May 30, 2024 at 11:30:28AM GMT, Fea Wang wrote:
> Hi Daniel,
> thank you for your help.
>
> I found that only the cover is without many maintainers. I used to send
> patches by git send-email --dry-run --to 'qemu-devel@nongnu.org,
> qemu-ri...@nongnu.org'
+/* TODO; To be implemented later. */
> +return -EINVAL;
> +}
> +
> +void kvm_arch_remove_all_hw_breakpoints(void)
> +{
> +/* TODO; To be implemented later. */
> +}
> +
> +void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg)
> +{
> +if (kvm_sw_breakpoints_active(cs)) {
> +dbg->control |= KVM_GUESTDBG_ENABLE;
> +}
> +}
> --
> 2.17.1
>
Reviewed-by: Andrew Jones
GET_KVM_HAVE_GUEST_DEBUG=y
> TARGET_XML_FILES= gdb-xml/riscv-64bit-cpu.xml gdb-xml/riscv-32bit-fpu.xml
> gdb-xml/riscv-64bit-fpu.xml gdb-xml/riscv-64bit-virtual.xml
> TARGET_NEED_FDT=y
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
case KVM_EXIT_RISCV_CSR:
> ret = kvm_riscv_handle_csr(cs, run);
> break;
> +case KVM_EXIT_DEBUG:
> +if (kvm_riscv_handle_debug(cs)) {
> +ret = EXCP_DEBUG;
> +}
> +break;
> default:
> qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
>__func__, run->exit_reason);
> --
> 2.17.1
>
>
Reviewed-by: Andrew Jones
On Mon, May 27, 2024 at 02:19:14AM GMT, Chao Du wrote:
> Set the control flag when there are active breakpoints. This will
> help KVM to know the status in the userspace.
>
> Signed-off-by: Chao Du
> ---
> target/riscv/kvm/kvm-cpu.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
On Mon, May 27, 2024 at 02:19:13AM GMT, Chao Du wrote:
> This patch implements insert/remove software breakpoint process:
>
> Add an input parameter for kvm_arch_insert_sw_breakpoint() and
> kvm_arch_remove_sw_breakpoint() to pass the length information,
> which helps us to know whether it is a
appropriate commit message.
> - Fix error handling according to Andrew Jones suggestion.
> target/riscv/kvm/kvm-cpu.c | 11 +++
> target/riscv/sbi_ecall_interface.h | 12
> 2 files changed, 19 insertions(+), 4 deletions(-)
>
> diff
On Tue, Mar 12, 2024 at 09:52:21PM GMT, Fei Wu wrote:
> The RISC-V Server Platform specification[1] defines a standardized set
> of hardware and software capabilities, that portable system software,
> such as OS and hypervisors can rely on being present in a RISC-V server
> platform.
>
> A
On Tue, Mar 12, 2024 at 09:52:20PM GMT, Wu, Fei2 wrote:
> The harts requirements of RISC-V server platform [1] require RVA23 ISA
> profile support, plus Sv48, Svadu, H, Sscofmpf etc. This patch provides
> a virt CPU type (rvsp-ref) as compliant as possible.
We should add the RVA23 profile cpu
t_per_socket, BITS_PER_LONG) + 1;
> +} else {
> +hart_bits = 0;
> +}
> +
> ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG,
> KVM_DEV_RISCV_AIA_CONFIG_HART_BITS,
> _bits, true, NULL);
> --
> 2.17.1
>
Reviewed-by: Andrew Jones
On Wed, May 15, 2024 at 02:25:31PM GMT, Eric Cheng wrote:
> On 3/8/2024 12:03 AM, Daniel Henrique Barboza wrote:
> > From: Tomasz Jeznach
> >
> > Generate device tree entry for riscv-iommu PCI device, along with
> > mapping all PCI device identifiers to the single IOMMU device instance.
> >
> >
On Fri, May 10, 2024 at 06:36:51PM GMT, Frank Chang wrote:
...
> > static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext
> > *ctx,
> > -IOMMUTLBEntry *iotlb)
> > +IOMMUTLBEntry *iotlb, bool gpa)
> > {
> > +dma_addr_t addr, base;
> > +uint64_t satp, gatp, pte;
>
On Thu, May 09, 2024 at 01:26:56PM GMT, Atish Kumar Patra wrote:
> On Thu, May 2, 2024 at 5:39 AM Andrew Jones wrote:
> >
> > On Tue, Apr 30, 2024 at 03:00:45PM GMT, Daniel Henrique Barboza wrote:
> > >
> > >
> > > On 4/29/24 16:28, Atish Patra wrote:
On Thu, May 09, 2024 at 02:23:42PM GMT, Daniel Henrique Barboza wrote:
>
>
> On 5/8/24 08:22, Andrew Jones wrote:
> > On Tue, May 07, 2024 at 11:27:21AM GMT, Rob Bradford wrote:
> > > This extension has now been ratified:
> > > https://jira.riscv.org/brows
ation (Zba_Zbb_Zbs)")
> +MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
> };
>
> static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
> --
> 2.44.0
>
>
Reviewed-by: Andrew Jones
I think we should also either change the false to true for RVB in
misa_ext_cfgs[] or at least ensure RVB is set for the 'max' cpu
type in riscv_init_max_cpu_extensions().
Thanks,
drew
On Fri, May 03, 2024 at 01:39:32PM GMT, Aleksei Filippov wrote:
>
>
> On 25.04.2024 12:21, Andrew Jones wrote:
> > On Mon, Apr 22, 2024 at 02:31:36PM +0200, Andrew Jones wrote:
> > > On Mon, Apr 22, 2024 at 02:42:54PM +0300, Alexei Filippov wrote:
> > > &g
On Tue, Apr 30, 2024 at 03:00:45PM GMT, Daniel Henrique Barboza wrote:
>
>
> On 4/29/24 16:28, Atish Patra wrote:
> > Currently, if a counter monitoring cycle/instret is stopped via
> > mcountinhibit we just update the state while the value is saved
> > during the next read. This is not accurate
On April 27, 2024 9:24:04 AM GMT+02:00, Michael Tokarev wrote:
>27.04.2024 09:59, Michael Tokarev wrote:
>> 27.04.2024 09:23, Andrew Jones wrote:
>...
>>> It's possible to cross-compile qemu, so it'd be good to add that to the CI
>>> for riscv until we can ad
o pick
it up. I suggest we keep this patch one way or another, though.
Thanks,
drew
>
>Thanks,
>
>/mjt
>
>
>> Reviewed-by: Andrew Jones
>> Signed-off-by: Yong-Xuan Wang
>>
>> ---
>> Changelog
>> v2:
>> - update the function d
boot time if the guest isn't
> using earlycon.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-cpu.c | 111 +
> target/riscv/sbi_ecall_interface.h | 17 +
> 2 files changed, 128 insertions(+)
>
Reviewed-by: Andrew Jones
g happens with an EINVAL error code. If we fail to
> disable the extension in KVM for any other reason, error out.
>
> We'll also keep erroring out when we fail to enable an extension in KVM,
> since adding the extension in riscv,isa at this point will cause a guest
> malfunction becau
On Mon, Apr 22, 2024 at 02:31:36PM +0200, Andrew Jones wrote:
> On Mon, Apr 22, 2024 at 02:42:54PM +0300, Alexei Filippov wrote:
> > kvm_riscv_handle_sbi() may return not supported return code to not
> > trigger qemu abort with vendor-specific sbi.
> >
> > Add new e
On Wed, Apr 24, 2024 at 04:28:09PM +0200, Andrew Jones wrote:
> Implementing wrs.nto to always just return is consistent with the
> specification, as the instruction is permitted to terminate the
> stall for any reason, but it's not useful for virtualization, where
> we'd like the g
.
Signed-off-by: Andrew Jones
Reviewed-by: Christoph Müllner
---
v3:
- Sending again, hoping the ü remains in Müllner
v2:
- Added #ifndef CONFIG_USER_ONLY around helper call
target/riscv/helper.h | 1 +
target/riscv/insn_trans/trans_rvzawrs.c.inc | 29
On Mon, Apr 22, 2024 at 11:08:31AM -0300, Daniel Henrique Barboza wrote:
>
>
> On 4/22/24 10:43, Andrew Jones wrote:
> > On Mon, Apr 22, 2024 at 10:12:53AM -0300, Daniel Henrique Barboza wrote:
> > > Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr
in Linux guests crashing on
boot). And, when running with a KVM which does forward the access,
QEMU will crash, since QEMU doesn't know what to do with the exit.
Fixes: 3108e2f1c69d ("target/riscv/kvm: update KVM exts to Linux 6.8")
Signed-off-by: Andrew Jones
---
target/riscv/cpu.h
, disabling
these types of extensions either shouldn't generally be done (so a noisy
warning helps prohibit that) or done for debug purposes (where a noisy
warning is fine).
>
> Suggested-by: Andrew Jones
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/kvm/kvm-cp
On Mon, Apr 22, 2024 at 02:42:54PM +0300, Alexei Filippov wrote:
> kvm_riscv_handle_sbi() may return not supported return code to not
> trigger qemu abort with vendor-specific sbi.
>
> Add new error path to provide proper error in case of
> qemu_chr_fe_read_all() may not return sizeof(ch).
I
On Mon, Apr 22, 2024 at 01:55:31PM +1000, Alistair Francis wrote:
> On Sat, Apr 13, 2024 at 9:26 PM Alexei Filippov
> wrote:
> >
> > kvm_riscv_handle_sbi() may return not supported return code to not trigger
> > qemu abort with vendor-specific sbi.
> >
> > Added SBI related return code's defines.
b47125 ("target/riscv: Handle KVM_EXIT_RISCV_SBI exit")
> ---
>
> Changes since v3:
> -Clear Reviewed-by tags
> target/riscv/kvm/kvm-cpu.c | 13 +
> target/riscv/sbi_ecall_interface.h | 12
> 2 files changed, 17 insertions(+), 8 deletions(-)
>
Reviewed-by: Andrew Jones
On Mon, Mar 25, 2024 at 04:01:16PM +0300, Alexei Filippov wrote:
> kvm_riscv_handle_sbi() may return not supported return code to not trigger
> qemu abort with vendor-specific sbi.
>
> Added SBI related return code's defines.
>
> Signed-off-by: Alexei Filippov
> Fixes: 4eb47125 ("target/riscv:
On Fri, Mar 15, 2024 at 12:29:57AM +0530, Himanshu Chauhan wrote:
> Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable
> the sdtrig extension and disable the debug property for these CPUs.
You still have the 'and disable the debug property' here...
>
> Signed-off-by:
On Fri, Mar 15, 2024 at 12:29:56AM +0530, Himanshu Chauhan wrote:
> This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled.
> The sdtrig extension may or may not be implemented in a system. Therefore, the
>-cpu rv64,sdtrig=
> option can be used to dynamically turn
; case TRIGGER_TYPE_AD_MATCH6:
> +if (!cpu->cfg.ext_sdtrig) {
> +break;
> +}
> +
> ctrl = env->tdata1[i];
> pc = env->tdata2[i];
>
> @@ -869,6 +885,10 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs,
> CPUWatchpoint *wp)
> }
> break;
> case TRIGGER_TYPE_AD_MATCH6:
> +if (!cpu->cfg.ext_sdtrig) {
> +break;
> +}
> +
> ctrl = env->tdata1[i];
> addr = env->tdata2[i];
> flags = 0;
> --
> 2.34.1
>
Reviewed-by: Andrew Jones
On Thu, Mar 14, 2024 at 05:05:10PM +0530, Himanshu Chauhan wrote:
> Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable
> the sdtrig extension and disable the debug property for these CPUs.
The commit message needs to be updated to remove the 'and disable the
debug property'.
On Thu, Mar 14, 2024 at 05:05:09PM +0530, Himanshu Chauhan wrote:
> This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled.
> The sdtrig extension may or may not be implemented in a system. Therefore, the
>-cpu rv64,sdtrig=
> option can be used to dynamically turn
On Thu, Mar 14, 2024 at 05:05:08PM +0530, Himanshu Chauhan wrote:
> The mcontrol6 triggers are not defined in debug specification v0.13
> These triggers are defined in sdtrig ISA extension.
>
> This patch:
>* Adds ext_sdtrig capability which is used to select mcontrol6 triggers
>* Keeps
wn flag and entry.
>
> [1] https://lists.gnu.org/archive/html/qemu-devel/2024-03/msg02592.html
>
> Reported-by: Clément Chigot
> Fixes: 3b8022269c ("target/riscv: add riscv,isa to named features")
> Suggested-by: Andrew Jones
> Signed-off-by: Daniel Henrique Ba
On Wed, Mar 13, 2024 at 11:50:09PM +0530, Himanshu Chauhan wrote:
> Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable
> the sdtrig extension and disable the debug property for these CPUs.
>
> Signed-off-by: Himanshu Chauhan
> ---
> target/riscv/cpu.c | 2 ++
> 1 file
On Wed, Mar 13, 2024 at 11:50:08PM +0530, Himanshu Chauhan wrote:
> This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled.
> The sdtrig extension may or may not be implemented in a system. Therefore, the
>-cpu rv64,sdtrig=
> option can be used to dynamically turn
On Wed, Mar 13, 2024 at 11:50:07PM +0530, Himanshu Chauhan wrote:
> The mcontrol6 triggers are not defined in debug specification v0.13
> These triggers are defined in sdtrig ISA extension.
>
> This patch:
>* Adds ext_sdtrig capability which is used to select mcontrol6 triggers
>* Keeps
On Wed, Mar 13, 2024 at 05:48:16PM +0530, Himanshu Chauhan wrote:
...
> #ifndef CONFIG_USER_ONLY
> +if (cpu->cfg.debug && cpu->cfg.ext_sdtrig) {
> + warn_report("Disabling debug property since sdtrig ISA
> >>> extension "
> + "is enabled");
>
On Wed, Mar 13, 2024 at 03:50:16PM +0530, Himanshu Chauhan wrote:
> On Wed, Mar 13, 2024 at 3:24 PM Andrew Jones
> wrote:
>
> > On Wed, Mar 13, 2024 at 11:39:30AM +0530, Himanshu Chauhan wrote:
> > > This patch adds "sdtrig" in the ISA string wh
On Wed, Mar 13, 2024 at 11:39:31AM +0530, Himanshu Chauhan wrote:
> Ventana's Veyron CPUs support sdtrig ISA extension. By default, enable
> the sdtrig extension and disable the debug property for these CPUs.
>
> Signed-off-by: Himanshu Chauhan
> ---
> target/riscv/cpu.c | 2 ++
> 1 file
On Wed, Mar 13, 2024 at 11:39:30AM +0530, Himanshu Chauhan wrote:
> This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled.
> The sdtrig extension may or may not be implemented in a system. Therefore, the
>-cpu rv64,sdtrig=
> option can be used to dynamically turn
On Wed, Mar 13, 2024 at 11:39:29AM +0530, Himanshu Chauhan wrote:
> The mcontrol6 triggers are not defined in debug specification v0.13
> These triggers are defined in sdtrig ISA extension.
>
> This patch:
>* Adds ext_sdtrig capability which is used to select mcontrol6 triggers
>* Keeps
_get_timebase_frequency(CPUState *cs)
> +{
> +g_assert_not_reached();
> +}
> +
> +#endif
> +
I think we've decided we don't need stubs like these since kvm_riscv_*
functions should always be called within 'if (kvm_enabled())' blocks (as
you have above), and then we leave it to the compile testing to point
out kvm function calls without kvm_enabled().
> #endif
> --
> 2.17.1
>
Besides dropping the stubs,
Reviewed-by: Andrew Jones
Thanks,
drew
other hand, it is easy to make the conversion to a two's-complement
> number.
>
> Richard
>
> On Sat, Mar 9, 2024 at 4:01 AM Andrew Jones wrote:
>
> > On Fri, Mar 08, 2024 at 08:22:01PM -0800, Richard Bagley wrote:
> > > post-nack, one further comment:
> >
On Mon, Mar 11, 2024 at 04:55:24AM -0700, Wu, Fei2 wrote:
> On 3/8/2024 5:20 PM, Andrew Jones wrote:
> > On Thu, Mar 07, 2024 at 02:26:18PM +0800, Wu, Fei wrote:
> >> On 3/7/2024 8:48 AM, Alistair Francis wrote:
> >>> On Thu, Mar 7, 2024 at 5:13 AM A
On Fri, Mar 08, 2024 at 08:22:01PM -0800, Richard Bagley wrote:
> post-nack, one further comment:
>
> One could argue that this change also aligns QEMU with supporting tools (as
> Andrew observed), and it makes sense to merge this change into QEMU until
> those tools update to supporting signed
On Thu, Mar 07, 2024 at 02:26:18PM +0800, Wu, Fei wrote:
> On 3/7/2024 8:48 AM, Alistair Francis wrote:
> > On Thu, Mar 7, 2024 at 5:13 AM Atish Kumar Patra
> > wrote:
> >>
> >> On Wed, Mar 6, 2024 at 4:56 AM Wu, Fei wrote:
> >>>
> >>> On 3/6/2024 8:19 AM, Alistair Francis wrote:
> On Mon,
On Thu, Feb 29, 2024 at 07:07:43PM +0530, Himanshu Chauhan wrote:
> All the CPUs may or may not implement the debug triggers (sdtrig)
> extension. The presence of it should be dynamically detectable.
> This patch exports the debug triggers as an extension which
> can be turned on or off by sdtrig=
On Thu, Feb 15, 2024 at 04:34:32PM +, Conor Dooley wrote:
> On Thu, Feb 15, 2024 at 03:26:18PM +0100, Andrew Jones wrote:
> > On Thu, Feb 15, 2024 at 01:33:47PM +, Conor Dooley wrote:
> > > On Fri, Feb 02, 2024 at 12:21:51PM -0300, Daniel Henrique Barboza wrote:
&g
On Thu, Feb 15, 2024 at 11:13:51AM -0300, Daniel Henrique Barboza wrote:
...
> > I want to raise my frustration with the crock we've been given here by
> > RVI. Any "named feature" that just creates a name for something that
> > already is assumed is completely useless, and DT property that is
On Thu, Feb 15, 2024 at 01:33:47PM +, Conor Dooley wrote:
> On Fri, Feb 02, 2024 at 12:21:51PM -0300, Daniel Henrique Barboza wrote:
> > The RVA22U64 and RVA22S64 profiles mandates certain extensions that,
> > until now, we were implying that they were available.
> >
> > We can't do this
On Wed, Feb 14, 2024 at 02:38:34PM +0100, Christoph Müllner wrote:
> On Wed, Feb 14, 2024 at 2:35 PM Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 2/7/24 09:22, Christoph Müllner wrote:
> > > The first patch of this series picks up an earlier v2 Ztso patch from
> > > Palmer,
> > > which
On Tue, Feb 13, 2024 at 03:53:08PM +0100, Alexandre Ghiti wrote:
> The Svvptc extension describes a uarch that does not cache invalid TLB
> entries: that's the case for qemu so there is nothing particular to
> implement other than the introduction of this extension, which is done
> here.
>
>
us reviewers.
Anyway, here's mine again
Reviewed-by: Andrew Jones
drew
> ---
> target/riscv/cpu.h | 8
> target/riscv/machine.c | 16
> 2 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
icntr_zicsr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zca_zcd_zba_zbb_
> zbs_zkt_ssccptr_sscounterenw_sstvala_sstvecd_svade_svinval_svpbmt#
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> target/riscv/cpu.c | 42 +++---
> target/riscv/cpu_cfg.h | 6 ++
> target/riscv/tcg/tcg-cpu.c | 2 ++
> 3 files changed, 43 insertions(+), 7 deletions(-)
>
Reviewed-by: Andrew Jones
On Thu, Feb 01, 2024 at 04:06:15PM +0100, Andrew Jones wrote:
> On Wed, Jan 31, 2024 at 10:24:30AM -0800, Palmer Dabbelt wrote:
> > Right now we just report 0 for marchid/mvendorid in QEMU. That's legal,
> > but it's tricky for users that want to check if they're running on QE
On Wed, Jan 31, 2024 at 10:24:30AM -0800, Palmer Dabbelt wrote:
> Right now we just report 0 for marchid/mvendorid in QEMU. That's legal,
> but it's tricky for users that want to check if they're running on QEMU
> to do so. This sets marchid to 42, which I've proposed as the QEMU
> architecture
> 2 files changed, 12 insertions(+), 12 deletions(-)
>
Reviewed-by: Andrew Jones
On Tue, Jan 30, 2024 at 03:30:13AM +, JeeHeng Sia wrote:
...
> > Sharing code is good, but if we have to parametrize the entire table, then
> > we might as well keep Arm and RISCV separate. Building the table first
> > with this struct, just to have it built again with the build_append API,
>
On Tue, Jan 30, 2024 at 03:16:34AM +, JeeHeng Sia wrote:
...
> > I think either there should be a comment that this supports only v2 of
> > SPCR spec or it should be able to create SPCR of any version. IMO, I
> > think it is better to add support till v4 (latest). Since consumers like
> >
> 0) {
> +acpi_add_table(table_offsets, tables_blob);
> +build_srat(tables_blob, tables->linker, s);
> +if (ms->numa_state->have_numa_distance) {
> + acpi_add_table(table_offsets, tables_blob);
> +build_slit(tables_blob, tables->linker, ms, s->oem_id,
> + s->oem_table_id);
> +}
> +}
> +
> /* XSDT is pointed to by RSDP */
> xsdt = tables_blob->len;
> build_xsdt(tables_blob, tables->linker, table_offsets, s->oem_id,
> --
> 2.34.1
>
>
Reviewed-by: Andrew Jones
On Mon, Jan 29, 2024 at 11:47:28AM +0300, Vadim Shakirov wrote:
> mcountinhibit, mcounteren and scounteren must always be 32-bit by
> privileged spec
We should also change hcounteren.
Thanks,
drew
>
> Signed-off-by: Vadim Shakirov
> ---
> target/riscv/cpu.h | 6 +++---
>
On Sun, Jan 28, 2024 at 06:14:39PM -0800, Sia Jee Heng wrote:
> RISC-V should also generate the SPCR in a manner similar to ARM.
> Therefore, instead of replicating the code, relocate this function
> to the common AML build.
>
> Signed-off-by: Sia Jee Heng
> ---
> hw/acpi/aml-build.c |
e QEMU has always implemented hardware A/D PTE bit
updating, so users must opt into svade (or get it from a CPU type
which enables it by default).
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew Jones
---
target/riscv/cpu.c | 8 +++-
target/riscv/tcg/tcg-cpu.c | 6 +
rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_
zicntr_zicsr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zca_zcd_zba_zbb_
zbs_zkt_sscounterenw_sstvala_sstvecd_svade_svinval_svpbmt#
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c
the named features QEMU implements are now being displayed in riscv,isa.
v2:
- Ensure svade is off by default even for the max cpu type
Andrew Jones (3):
target/riscv: Reset henvcfg to zero
target/riscv: Gate hardware A/D PTE bit updating
target/riscv: Promote svade to a normal extension
Danie
Barboza
Reviewed-by: Andrew Jones
---
target/riscv/cpu.c | 17 +
target/riscv/cpu_cfg.h | 6 --
target/riscv/tcg/tcg-cpu.c | 16 ++--
3 files changed, 23 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index
(this behavior change fixes [2])
Fixes: 0af3f115e68e ("target/riscv: Add *envcfg.HADE related check in address
translation") [1]
Fixes: 48531f5adb2a ("target/riscv: implement svade") [2]
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew Jones
---
target/riscv/cp
From: Daniel Henrique Barboza
Recent changes in options handling removed the 'mmu' default the bare
CPUs had, meaning that we must enable 'mmu' by hand when using the
rva22s64 profile CPU.
Given that this profile is setting a satp mode, it already implies that
we need a 'mmu'. Enable the 'mmu'
fg.HADE related check in address
translation")
Fixes: ed67d63798f2 ("target/riscv: Update CSR bits name for svadu extension")
Reviewed-by: Daniel Henrique Barboza
Signed-off-by: Andrew Jones
---
target/riscv/cpu.c | 3 +--
target/riscv/csr.c | 2 +-
2 files changed, 2 insertions(
On Thu, Jan 25, 2024 at 04:53:19PM -0300, Daniel Henrique Barboza wrote:
> From: Andrew Jones
>
> Named features are extensions which don't make sense for users to
> control and are therefore not exposed on the command line. However,
> svade is an extension which makes sense for u
On Thu, Jan 25, 2024 at 05:23:20PM +0900, Akihiko Odaki wrote:
> On 2024/01/24 17:16, Andrew Jones wrote:
> > On Wed, Jan 24, 2024 at 12:08:33PM +0900, Akihiko Odaki wrote:
> > > On 2024/01/23 17:20, Andrew Jones wrote:
> > > > On Mon, Jan 22, 2024 at 02:55
riscv/gdbstub.c
> index 58b3ace0fe..f15980fdcf 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -218,7 +218,7 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int
> base_reg)
> CPURISCVState *env = >env;
> GString *s = g_string_new(NULL);
> riscv_csr_predicate_fn predicate;
> -int bitsize = 16 << env->misa_mxl_max;
> +int bitsize = riscv_cpu_max_xlen(*env);
> int i;
>
> #if !defined(CONFIG_USER_ONLY)
> --
> 2.43.0
>
Otherwise,
Reviewed-by: Andrew Jones
On Wed, Jan 24, 2024 at 12:08:33PM +0900, Akihiko Odaki wrote:
> On 2024/01/23 17:20, Andrew Jones wrote:
> > On Mon, Jan 22, 2024 at 02:55:50PM +, Alex Bennée wrote:
> > > From: Akihiko Odaki
> > >
> > > The effective MXL value matters when booting.
>
misa_mxl_max to determine bitness
> v2:
> set processor family
> ---
> hw/riscv/Kconfig | 1 +
> hw/riscv/virt.c | 42 ++++++
> 2 files changed, 43 insertions(+)
>
Reviewed-by: Andrew Jones
On Mon, Jan 22, 2024 at 02:07:57PM +0100, Heinrich Schuchardt wrote:
> Generate SMBIOS tables for the RISC-V mach-virt.
> Add CONFIG_SMBIOS=y to the RISC-V default config.
> Set the default processor family in the type 4 table.
>
> The implementation is based on the corresponding ARM and Loongson
On Mon, Jan 22, 2024 at 02:55:50PM +, Alex Bennée wrote:
> From: Akihiko Odaki
>
> The effective MXL value matters when booting.
I'd prefer this commit message get some elaboration. riscv_is_32bit()
is used in a variety of contexts, some where it should be reporting
the max misa.mxl.
On Mon, Jan 22, 2024 at 01:28:18PM +0100, Heinrich Schuchardt wrote:
> On 22.01.24 10:57, Andrew Jones wrote:
> > On Fri, Dec 29, 2023 at 01:07:23PM +0100, Heinrich Schuchardt wrote:
...
> > > +#if defined(TARGET_RISCV32)
> > > +smbios_set_default_processor_family(0
QEMU_ARCH_I386 | QEMU_ARCH_ARM | QEMU_ARCH_LOONGARCH | QEMU_ARCH_RISCV)
> SRST
> ``-smbios file=binary``
> Load SMBIOS entry from binary file.
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones
e_legacy(MachineState *ms, size_t *length);
> void smbios_get_tables(MachineState *ms,
> const struct smbios_phys_mem_area *mem_array,
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones
,connector_type=%d][,port_type=%d]\n"
> "specify SMBIOS type 8 fields\n"
> @@ -2722,7 +2722,7 @@ SRST
> ``-smbios
> type=3[,manufacturer=str][,version=str][,serial=str][,asset=str][,sku=str]``
> Specify SMBIOS type 3 fields
>
> -``-smbios
> type=4[,sock_pfx=str][,manufacturer=str][,version=str][,serial=str][,asset=str][,part=str][,processor-id=%d]``
> +``-smbios
> type=4[,sock_pfx=str][,manufacturer=str][,version=str][,serial=str][,asset=str][,part=str][,processor-family=%d][,processor-id=%d]``
> Specify SMBIOS type 4 fields
>
> ``-smbios type=11[,value=str][,path=filename]``
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones
done(Notifier *notifier, void *data)
> {
> RISCVVirtState *s = container_of(notifier, RISCVVirtState,
> @@ -1337,6 +1377,8 @@ static void virt_machine_done(Notifier *notifier, void
> *data)
> riscv_setup_direct_kernel(kernel_entry, fdt_load_addr);
> }
>
> +virt_build_smbios(s);
> +
> if (virt_is_acpi_enabled(s)) {
> virt_acpi_setup(s);
> }
> --
> 2.43.0
>
>
Otherwise,
Reviewed-by: Andrew Jones
Thanks,
drew
On Mon, Jan 22, 2024 at 03:42:10PM +1000, Alistair Francis wrote:
> > > From memory the "debug" property is for the original debug spec:
> > > https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote
> > >
> > > That was ratified and is an official extension. AFAIK this is what is
>
On Wed, Jan 17, 2024 at 07:54:12PM +0530, Himanshu Chauhan wrote:
> This patch adds "x-sdtrig" in the ISA string when sdtrig extension is enabled.
> The sdtrig extension may or may not be implemented in a system. Therefore, the
> -cpu rv64,x-sdtrig=
> option can be used to dynamically
On Thu, Jan 11, 2024 at 03:17:25PM +, Rob Bradford wrote:
> + Ved
>
> On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote:
> > On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote:
> > > On Tue, Jan 09, 2024 at 05:07:35PM +, Rob Bradford wrote:
> &
/tcg-cpu.c
> index 8a35683a34..fda54671d5 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -791,6 +791,7 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
> MISA_CFG(RVJ, false),
> MISA_CFG(RVV, false),
> MISA_CFG(RVG, false),
> +MISA_CFG(RVB, false)
> };
>
> /*
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones
On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote:
> On Tue, Jan 09, 2024 at 05:07:35PM +, Rob Bradford wrote:
> > Add the infrastructure for the 'B' extension which is the union of the
> > Zba, Zbb and Zbs instructions.
> >
> > Signed-off-by: Rob Br
tensions while setting
> * cpu->cfg accordingly.
> @@ -309,6 +338,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
> env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
> }
>
> +if (riscv_has_ext(env, RVB)) {
> + riscv_cpu_validate_b(cpu);
> +}
> +
> if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
> error_setg(errp,
> "I and E extensions are incompatible");
> --
> 2.43.0
>
>
Reviewed-by: Andrew Jones
On Tue, Jan 09, 2024 at 05:07:35PM +, Rob Bradford wrote:
> Add the infrastructure for the 'B' extension which is the union of the
> Zba, Zbb and Zbs instructions.
>
> Signed-off-by: Rob Bradford
> ---
> target/riscv/cpu.c | 5 +++--
> target/riscv/cpu.h | 1 +
>
On Wed, Jan 10, 2024 at 03:32:21PM -0300, Daniel Henrique Barboza wrote:
>
>
> On 1/9/24 14:07, Rob Bradford wrote:
> > Signed-off-by: Rob Bradford
> > ---
> > target/riscv/tcg/tcg-cpu.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git
gt; +
> +riscv_isa = riscv_isa_string(cpu);
> +qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", riscv_isa);
> +
> +snprintf(isa_base, maxlen, "rv%di", xlen);
> +qemu_fdt_setprop_string(fdt, nodename, "riscv,isa-base", isa_base);
> +
> +isa_extensions = riscv_isa_extensions_list(cpu, );
> +qemu_fdt_setprop_string_array(fdt, nodename, "riscv,isa-extensions",
> + isa_extensions, count);
> +
> +for (int i = 0; i < count; i++) {
> +g_free(isa_extensions[i]);
> +}
> +
> +g_free(isa_extensions);
> +}
> +#endif
> +
> #define DEFINE_CPU(type_name, initfn) \
> { \
> .name = type_name, \
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 5f3955c38d..192d0c2d31 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -510,6 +510,7 @@ char *riscv_isa_string(RISCVCPU *cpu);
> #define cpu_mmu_index riscv_cpu_mmu_index
>
> #ifndef CONFIG_USER_ONLY
> +void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename);
> void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
> vaddr addr, unsigned size,
> MMUAccessType access_type,
> --
> 2.39.2
>
Reviewed-by: Andrew Jones
On Wed, Jan 10, 2024 at 10:25:36AM +, Conor Dooley wrote:
> From: Conor Dooley
>
> A cpu may not have the same xlen as the compile time target, and
> misa_mxl_max is the source of truth for what the hart supports.
>
> Reported-by: Andrew Jones
> Link:
> https://lo
On Mon, Dec 18, 2023 at 02:37:55PM +1000, Alistair Francis wrote:
...
> > +void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
> > +{
> > +const size_t maxlen = sizeof("rv128i");
> > +g_autofree char *isa_base = g_new(char, maxlen);
> > +g_autofree char *riscv_isa;
> > +
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