Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On Mon, 2016-06-20 at 09:47 +0200, Thomas Huth wrote: > > Linux ppc behaves the same on a 970. So we will need to fix the 'rfi's > > there also.  > > Really? Wow, that surprises me. That OpenBIOS code likely never ran on a > real 970 hardware, so that's not too much surprising that the "rfi" >

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On Mon, 2016-06-20 at 08:10 +0200, Cédric Le Goater wrote: > That is how I feel also. So, why don't we just remove the op code in the  > instruction sets from the 32bit CPUs instead of leaving it and testing  > for PPC_SEGMENT_64B ? or is there some reasons we want to keep it around ?  Ah no

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On Mon, 2016-06-20 at 17:08 +1000, Benjamin Herrenschmidt wrote: >  > That fixed, it dies elsewhere in something related to page faults, > still digging. >  Next problem: Darwin kernel assumes DSISR is 0 on a 0x380 exception ! qemu was leaving it to whatever value it had before.

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On Mon, 2016-06-20 at 08:35 +1000, Benjamin Herrenschmidt wrote: > , > Ok so Darwin uses some of the HSPRG etc... that we don't emulate on > the 970 so I suspect it never worked. I've added them but something > else breaks, I'll dig, I have the kernel source so it shouldn't b

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On Mon, 2016-06-20 at 08:15 +1000, Benjamin Herrenschmidt wrote: > On Sun, 2016-06-19 at 19:21 +0200, Cédric Le Goater wrote: > > But, I could not boot  ./darwinppc-602.cdr with on a 970. That > > might > > be another issue. > > Right, the issue is that the kernel in D

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On Sun, 2016-06-19 at 19:21 +0200, Cédric Le Goater wrote: > But, I could not boot  ./darwinppc-602.cdr with on a 970. That might > be another issue. Right, the issue is that the kernel in Darwin 6.0.2 doesn't support the 970 :-) I think the first MacOS X to support 970 was some special build of

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On Sun, 2016-06-19 at 19:23 +0200, Cédric Le Goater wrote: > > You can run a 32-bit OS or firmware on ppc64, but it needs to know that > > it's running on a 64-bit chip and do a few things differently. > > yes sure but qemu would still allow rfi under 64bit CPUs, that is what  > I was concerned

Re: [Qemu-devel] [PATCH] ppc: Improve emulation of THRM registers

On Sun, 2016-06-19 at 11:09 -0400, G 3 wrote: >   On 6/19/16 12:12 AM, qemu-devel-requ...@nongnu.org wrote: > > Message: 5 > > Date: Sun, 19 Jun 2016 10:54:13 +1000 > > From: Benjamin Herrenschmidt<b...@kernel.crashing.org> > > To:qemu-...@nongnu.or

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On Sun, 2016-06-19 at 14:49 +0200, Cédric Le Goater wrote: > > So my test is correct in the context of what we emulate today. > > OK. so this is an openbios issue when run under a ppc64. shouldn't we  > be using an openbios-ppc64 in that case ?   > > > We could be more strict with the rfi

[Qemu-devel] [PATCH] ppc: Improve emulation of THRM registers

hus fixing the problem. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/helper.h | 1 + target-ppc/misc_helper.c| 41 + target-ppc/translate_init.c | 13 ++--- 3 files changed, 52 insertions(+), 3 de

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On Fri, 2016-06-17 at 16:32 +0200, Cédric Le Goater wrote: > The instruction set PPC_POWER_BR contains nearly all the deleted  > instructions from isa2. rfi is not part of it and should. Also, only  > the cpus "PowerPC 601*" make a use of it in their insns_flags. Are you sure those arent the old

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

On Fri, 2016-06-17 at 13:02 +0200, Thomas Huth wrote: > According to the PPC970FX user manual that I have: > > "The 970FX does not provide support for the following optional or >  obsolete instructions (or instruction forms). >  Attempted use of these will result in an illegal instruction type >  

Re: [Qemu-devel] [Qemu-ppc] [PATCH 01/10] ppc: Fix rfi/rfid/hrfi/... emulation

<1465795496-15071-2-git-send-email-...@kaod.org> <20160616010702.gi28...@voom.fritz.box> <20160617022731.ga19...@voom.fritz.box> <57639095.5010...@kaod.org> <576392b1.6030...@kaod.org>

Re: [Qemu-devel] [PATCH 06/10] ppc: Rework generation of priv and inval interrupts

On Wed, 2016-06-15 at 11:19 +1000, David Gibson wrote: > > >  static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) > > @@ -4348,9 +4371,15 @@ static inline void gen_op_mfspr(DisasContext *ctx) > >   TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4); > >  

Re: [Qemu-devel] [PATCH 03/10] ppc: Rework POWER7 & POWER8 exception model (part 2)

On Tue, 2016-06-14 at 16:25 +1000, David Gibson wrote: > > Properly implement LPES0/1 handling for HV vs. !HV mode. > >  > > Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> > > [clg: AIL implementation was fixed in commit 5c94b2a5e5ef > &

[Qemu-devel] [PATCH 2/9] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors

invalidating a segment congruence class (ie, allowing more address bits to be relevant in the invalidation), this fails miserably on those OSes. Instead don't bother, do like ppc64 and blow the whole tlb when tlbie is executed. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.

[Qemu-devel] [PATCH 3/9] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode

This ports the existing 64-bit mechanism to 32-bit, thus series of 64 tlbie's followed by a sync like some versions of Darwin (ab)use will result in a single flush. We apply a pending flush on any sync instruction though, as Darwin doesn't use tlbsync on non-SMP systems. Signed-off-by: Benjamin

[Qemu-devel] [PATCH 4/9] ppc: POWER7 had ACOP and PID registers

We only had them on POWER8, add them to POWER7 as well Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/translate_init.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 5

[Qemu-devel] [PATCH 8/9] ppc: Add missing slbfee. instruction on ppc64 BookS processors

Used to lookup SLB entries by address, for some reason it was missing. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/helper.h | 1 + target-ppc/mmu-hash64.c | 30 ++ target-ppc/translate.c | 26 +++

[Qemu-devel] [PATCH 7/9] ppc: Fix slbia decode

-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 3255184..33a9223 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9980,7 +

[Qemu-devel] [PATCH 1/9] ppc: Properly tag the translation cache based on MMU mode

MSR:IR and MSR:DR are part of the hflags used to tag translated code, so that we use different translated code for different MMU settings. Darwin gets hurt by this problem. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/helper_regs.h | 2 +- 1 file chan

[Qemu-devel] [PATCH 9/9] ppc: Do not take exceptions on unknown SPRs in privileged mode

The architecture specifies that mtspr/mfspr on an unknown SPR number should act as a nop in privileged mode. I haven't removed the warning however as it can be useful for diagnosing. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/translate.c | 11

[Qemu-devel] [PATCH 6/9] ppc: Fix mtmsr decoding

We had code to handle the L bit in the opcode but we didn't allow it in the decode mask. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/trans

[Qemu-devel] [PATCH 5/9] ppc: POWER7 has lq/stq instructions and stq need to check ISA

the instructions to POWER7 Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/translate.c | 5 - target-ppc/translate_init.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a

Re: [Qemu-devel] [PATCH 2/2] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors

On Tue, 2016-06-07 at 11:40 +1000, David Gibson wrote: > Ugh, this patch too is showing as corrupt for me.  I suspect the > problem is on my end, but I have no idea what, yet. No it's on mine. The latest update of evolution in Fedora broke sending patches :-( It unconditionally replaces 2 or

[Qemu-devel] [PATCH 1/6] ppc: POWER7 had ACOP and PID registers

We only had them on POWER8, add them to POWER7 as well Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> ---  target-ppc/translate_init.c | 18 ++  1 file changed, 18 insertions(+) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 5

[Qemu-devel] [PATCH 1/6] ppc: POWER7 had ACOP and PID registers

We only had them on POWER8, add them to POWER7 as well Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> ---  target-ppc/translate_init.c | 18 ++  1 file changed, 18 insertions(+) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 5

Re: [Qemu-devel] [PATCH] scsi-disk: fix reads from scsi-disk devices

ector to offset > conversion > in order to restore read functionality. > > Signed-off-by: Mark Cave-Ayland <mark.cave-ayl...@ilande.co.uk> This fixes powerpc PAPR booting Tested-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> > --- >  hw/scsi/scsi-disk.c |2 +-

[Qemu-devel] [PATCH 6/6] ppc: Do not take exceptions on unknown SPRs in privileged mode

The architecture specifies that mtspr/mfspr on an unknown SPR number should act as a nop in privileged mode. I haven't removed the warning however as it can be useful for diagnosing. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> ---  target-ppc/translate.c | 11

[Qemu-devel] [PATCH 4/6] ppc: Fix slbia decode

-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> ---  target-ppc/translate.c | 2 +-  1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 3255184..33a9223 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9980,7 +

[Qemu-devel] [PATCH 5/6] ppc: Add missing slbfee. instruction on ppc64 BookS processors

Used to lookup SLB entries by address, for some reason it was missing. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- A version of this was in my earlier powernv series but had a bug, this one should be correct.  target-ppc/helper.h |  1 +  target-ppc/mmu-hash64.

[Qemu-devel] [PATCH 3/6] ppc: Fix mtmsr decoding

We had code to handle the L bit in the opcode but we didn't allow it in the decode mask. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> ---  target-ppc/translate.c | 2 +-  1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-ppc/translate.c b/target-ppc/trans

[Qemu-devel] [PATCH 2/6] ppc: POWER7 has lq/stq instructions and stq need to check ISA version

the instructions to POWER7 Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> ---  target-ppc/translate.c  | 5 -  target-ppc/translate_init.c | 2 +-  2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index a

Re: [Qemu-devel] [RFC/PATCH] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode

On Mon, 2016-06-06 at 23:36 +0100, Mark Cave-Ayland wrote: > > After another run of the OpenBIOS tests with this patch applied on top > of the previous 2 patches, I see no regressions introduced. Like Cédric > I don't get the feeling that the Mac machines necessarily run faster, > however the

[Qemu-devel] [RFC/PATCH] ppc: Batch TLB flushes on 32-bit 6xx/7xx/7xxx in hash mode

This ports the existing 64-bit mechanism to 32-bit, thus series of 64 tlbie's followed by a sync like some versions of Darwin (ab)use will result in a single flush. We apply a pending flush on any sync instruction though, as Darwin doesn't use tlbsync on non-SMP systems. Signed-off-by: Benjamin

[Qemu-devel] [PATCH 2/2] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors

invalidating a segment congruence class (ie, allowing more address bits to be relevant in the invalidation), this fails miserably on those OSes. Instead don't bother, do like ppc64 and blow the whole tlb when tlbie is executed. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.

[Qemu-devel] [PATCH 1/2] ppc: Properly tag the translation cache based on MMU mode

MSR:IR and MSR:DR are part of the hflags used to tag translated code, so that we use different translated code for different MMU settings. Darwin gets hurt by this problem. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> ---  target-ppc/helper_regs.h | 2 +-  1 file chan

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] ppc: complete the new HV mode

On Mon, 2016-06-06 at 17:04 +1000, Benjamin Herrenschmidt wrote: > On Mon, 2016-06-06 at 07:29 +0100, Mark Cave-Ayland wrote: > > > > > > The best reproducer is to run from David's ppc-for-2.7 branch with > > the above patch applied manually and then try booting the f

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] ppc: complete the new HV mode

On Mon, 2016-06-06 at 07:29 +0100, Mark Cave-Ayland wrote: > > The best reproducer is to run from David's ppc-for-2.7 branch with > the above patch applied manually and then try booting the following > ISOs which now panic on boot with the split I/D MMU mode enabled: So at least HelenOS is fixed

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] ppc: complete the new HV mode

On Mon, 2016-06-06 at 13:55 +1000, Benjamin Herrenschmidt wrote: > > I'm not sure that 32-bit patch is correct. We shouldn't have to flush > on IR/DR transitions at all, that's the whole point of the split I/D > code. > > I think something else is wrong. Note: With whateve

Re: [Qemu-devel] [Qemu-ppc] [PATCH 0/3] ppc: complete the new HV mode

On Sun, 2016-06-05 at 19:41 +0200, Cédric Le Goater wrote: >  > Here is a fix I think. Could you give it a try ?  This is somewhat wrong... > commit cd0c6f473532 ('ppc: Do some batching of TCG tlb flushes') > introduced an optimisation to flush TLBs only when a context > synchronizing event is

Re: [Qemu-devel] [PATCH 0/3] ppc: complete the new HV mode

; > > > Tested on a POWER8 pserie guest and on mac99. > > > > Benjamin Herrenschmidt (2): > >   ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV > >   ppc: Better figure out if processor has HV mode > > > > Cédric Le Goater (1): > >

Re: [Qemu-devel] [PULL 1/3] ppc: Rework POWER7 & POWER8 exception model

On Tue, 2016-04-05 at 09:03 +0200, Cédric Le Goater wrote: > > Well, yes, but cpu_ppc_set_papr() only handles the AMOR setting, the LPCR  > settings were kept for later as they were not bug fixes.  > > As for now, powerpc_excp() checks the ILE bit and uses the AIL bits to  > calculate the vector

Re: [Qemu-devel] powerpc: Clear user CPU feature bits if TM is disabled at runtime

On Tue, 2016-04-05 at 19:35 +1000, Michael Ellerman wrote: > Shouldn't we be clearing the user feature there too? > > The ibm_pa_features array and the logic in scan_features() knows to > flip the > cpu_user_features bits, it was just never updated to handle > cpu_user_features2. > > So it seems

Re: [Qemu-devel] [PULL 1/3] ppc: Rework POWER7 & POWER8 exception model

On Tue, 2016-04-05 at 12:17 +1000, David Gibson wrote: > From: Cédric Le Goater <c...@fr.ibm.com> > > From: Benjamin Herrenschmidt <b...@kernel.crashing.org> > > This patch fixes the current AIL implementation for POWER8. The > interrupt vector address can be calc

Re: [Qemu-devel] [PATCH 04/17] ppc: Add number of threads per core to the processor definition

On Tue, 2016-03-15 at 20:45 +1100, David Gibson wrote: > On Mon, Mar 14, 2016 at 05:56:27PM +0100, Cédric Le Goater wrote: > > > > From: Benjamin Herrenschmidt <b...@kernel.crashing.org> > > > > Also use it to clamp the max SMT mode and ensure that the cpu_d

Re: [Qemu-devel] [Qemu-ppc] [PATCH 14/17] ppc: Add dummy write to VTB

On Mon, 2016-03-14 at 21:54 +0100, Thomas Huth wrote: > I think it would also be possible to use spr_access_nop() for now > instead of introducing more dummy functions like spr_write_vtb. Well, the goal was to eventually put some real code in there... Cheers, Ben.

Re: [Qemu-devel] [PATCH 72/77] ppc: A couple more dummy POWER8 Book4 regs

On Wed, 2016-03-02 at 21:30 +0100, Thomas Huth wrote: > So if you've got some spare time, could you maybe extract all those > patches that define new SPRs with spr_register_kvm[_hv] and send them as > a separate patch series? That could help to fix future migration issues, > and also would

Re: [Qemu-devel] [PATCHv2 09/10] target-ppc: Helper to determine page size information from hpte alone

he spapr code should now be able to handle any page > size > listed in the env->sps table. > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au> Acked-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> > --- >  hw/ppc/

Re: [Qemu-devel] [PATCHv2 08/10] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs

rly ? IE, tlbie will give us the page size using the same encoding as the HPTE iirc when L=1 ? To be honest the encoding of tlbie in arch 2.07 is so completely insane I have a hard time figuring it out myself ... :-) Otherwise, Acked-by: Benjamin Herrenschmidt <b...@kernel.crashing

Re: [Qemu-devel] [PATCHv2 03/10] target-ppc: Rework ppc_store_slb

function and its callers to work this way. > > As a bonus, this slightly simplifies the emulation of segment > registers for > when running a 32-bit OS on a 64-bit CPU. > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au> Acked-by: Benjamin Herrenschmidt <b...@ker

Re: [Qemu-devel] [PATCHv2 04/10] target-ppc: Rework SLB page size lookup

64(), so remove > it and > have the callers use deposit64() directly. > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au> Acked-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> > --- >  target-ppc/cpu.h|  1 + >  target-ppc/machine.c| 2

Re: [Qemu-devel] [PATCHv2 05/10] target-ppc: Use actual page size encodings from HPTE

_shift() > function which looks up the page size of an HPTE.  We use this to > validate > page sizes encodings on faults, and populate the qemu TLB with larger > page sizes when appropriate. > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au> Acked-by: Benjamin Her

Re: [Qemu-devel] [PATCHv2 10/10] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG

gt; didn't support in TCG. > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au> Acked-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> > --- >  target-ppc/mmu-hash64.h |  2 ++ >  target-ppc/translate_init.c | 32 >  2

Re: [Qemu-devel] [PATCHv2 07/10] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one()

ent places, and do different things. > > Clean this up by separating out the tlbiva instruction into its own > handling.  In fact the implementation is only a stub anyway. > > Signed-off-by: David Gibson <da...@gibson.dropbear.id.au> Acked-by: Benjamin Herrenschmidt <b...

Re: [Qemu-devel] [PATCHv2 06/10] target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one

fers and tlbie does provide additional information on server processors that we would need should we chose to implemented fine grained invalidations (such as the page size). In the meantime: Acked-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> > Signed-off-by: David Gibso

Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

On Mon, 2015-12-21 at 13:41 +1100, David Gibson wrote: > Now that the spapr code has been extended to support 64kiB pages, we can > allow guests to use 64kiB pages on an emulated POWER8 by adding it to the > "segment_page_sizes" structure which is advertised via the device tree. > > For now we

Re: [Qemu-devel] [Qemu-ppc] [PATCH 41/77] ppc/pnv: Add LPC controller and hook it up with a UART and RTC

On Thu, 2015-12-03 at 12:04 +1100, Alexey Kardashevskiy wrote: > On 12/02/2015 04:29 PM, Benjamin Herrenschmidt wrote: > > On Wed, 2015-12-02 at 13:24 +1100, Alexey Kardashevskiy wrote: > > > > But on the whole I agree with you, since the LPC is part of the P8 > > >

Re: [Qemu-devel] [Qemu-ppc] [PATCH 41/77] ppc/pnv: Add LPC controller and hook it up with a UART and RTC

On Thu, 2015-12-03 at 12:45 +1100, David Gibson wrote: > > There are several different cases here and I'm not sure which you're > thinking about. > > 1) Guest has different number of threads-per-core than the host > > This one is just fine - PAPR defines how the guest should get the > number of

Re: [Qemu-devel] [Qemu-ppc] [PATCH 41/77] ppc/pnv: Add LPC controller and hook it up with a UART and RTC

On Wed, 2015-12-02 at 13:24 +1100, Alexey Kardashevskiy wrote: > > But on the whole I agree with you, since the LPC is part of the P8 > > chip, I think it makes sense to include it even with -nodefaults. > > POWER8 chips all have 8 threads per core but we do not always assume -smt  >

Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/77] ppc: Add "native" POWER8 platform

On Mon, 2015-11-30 at 19:15 +0100, Cédric Le Goater wrote: > The pnor file is compiled from github. The patch is below (without the dirty > cut and paste I did in loader.c). The offset for the PAYLOAD and BOOTKERNEL > partitions are hard coded but I guess we don't need to read the flash >

Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/77] ppc: Add "native" POWER8 platform

On Mon, 2015-11-30 at 22:24 +0100, Cédric Le Goater wrote: > > In practice we should read the partition tables, I don't like hard > > coded offsets... But we should probably create a proper "flash driver" > > that does a bunch of this, and also adds the BMC style flash interface > > so OPAL can

Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/77] ppc: Add "native" POWER8 platform

On Fri, 2015-11-27 at 11:21 +0100, Alexander Graf wrote: > > How does real hardware store petitboot? If it's flash, you could pass it > in using -pflash and thus model things even more closely and allow users > to just take the ROM image as is. It is a flash image, we could use an Open Power

Re: [Qemu-devel] [Qemu-ppc] [PATCH 00/77] ppc: Add "native" POWER8 platform

On Sat, 2015-11-28 at 11:53 +0100, Alexander Graf wrote: > > > Am 28.11.2015 um 08:59 schrieb Benjamin Herrenschmidt <benh@kernel. > > crashing.org>: > > > > > On Fri, 2015-11-27 at 11:21 +0100, Alexander Graf wrote: > > > > > > How does r

Re: [Qemu-devel] [Qemu-ppc] [PATCH 27/77] ppc/pnv: Add XSCOM infrastructure

On Tue, 2015-11-24 at 14:20 +1100, David Gibson wrote: > Hmm.. I'm thinking it probably makes sense to unify the representation > of "chip" and "xscom" since there's a 1:1 correspondance.  To be > QOMishly correct, I think the right way would be a SysBusDevice for > each chip, implementing the

Re: [Qemu-devel] [Qemu-ppc] [PATCH 27/77] ppc/pnv: Add XSCOM infrastructure

On Tue, 2015-11-24 at 14:20 +1100, David Gibson wrote: > > > +static uint32_t xscom_to_pcb_addr(uint64_t addr) > > +{ > > +    addr &= (XSCOM_SIZE - 1); > > +    return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); > > Wow, that's a pretty weird address transform. Indeed :-) That's how

Re: [Qemu-devel] [Qemu-ppc] [PATCH 24/77] ppc: Move exception generation code out of line

On Fri, 2015-11-20 at 18:53 +1100, David Gibson wrote: > On Wed, Nov 11, 2015 at 11:27:37AM +1100, Benjamin Herrenschmidt > wrote: > > There's no point inlining this, if you hit the exception case you > > exit anyway, > > That doesn't quite seem relevant - IIUC th

Re: [Qemu-devel] [Qemu-ppc] [PATCH 22/77] ppc: Add real mode CI load/store instructions for P7 and P8

On Fri, 2015-11-20 at 18:48 +1100, David Gibson wrote: > > > @@ -380,9 +380,11 @@ typedef struct opcode_t { > >  #if defined(CONFIG_USER_ONLY) > >  #define CHK_HV GEN_PRIV > >  #define CHK_SV GEN_PRIV > > +#define CHK_HVDR GEN_PRIV > > I'm guessing this is supposed to be CHK_HVRM as below.

Re: [Qemu-devel] [Qemu-ppc] [PATCH 21/77] ppc: Rework generation of priv and inval interrupts

On Fri, 2015-11-20 at 18:45 +1100, David Gibson wrote: > snip] > >  /* tlbiel */ > >  static void gen_tlbiel(DisasContext *ctx) > >  { > >  #if defined(CONFIG_USER_ONLY) > > -    gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); > > +    GEN_PRIV; > >  #else > > -    if (unlikely(ctx->pr ||

Re: [Qemu-devel] [Qemu-ppc] [PATCH 21/77] ppc: Rework generation of priv and inval interrupts

On Fri, 2015-11-20 at 18:45 +1100, David Gibson wrote: >  > So, I'm not 100% following the logic below, but it looks like the > existing code used SPR_NOACCESS to mark things which generated a > privilege exception compared to NULL for things which generated an > invalid instruction exception.  

Re: [Qemu-devel] [Qemu-ppc] [PATCH 26/77] ppc/pnv: Add skeletton PowerNV platform

On Fri, 2015-11-20 at 19:21 +1100, David Gibson wrote: > On Wed, Nov 11, 2015 at 11:27:39AM +1100, Benjamin Herrenschmidt > wrote: > > No devices yet, not even an interrupt controller, just to get > > started. > > > > Signed-off-by: Benjamin Herrensch

Re: [Qemu-devel] [Qemu-ppc] [PATCH 09/77] ppc: Fix do_rfi() for rfi emulation

On Thu, 2015-11-19 at 17:19 +1100, David Gibson wrote: > On Wed, Nov 11, 2015 at 11:27:22AM +1100, Benjamin Herrenschmidt > wrote: > > XXX This patch needs double checking... It fixed 32-bit userspace > > but I'm not sure it's right. I wonder whether msr_is_64bit() should >

Re: [Qemu-devel] [Qemu-ppc] [PATCH 08/77] ppc: Add number of threads per core to the processor definition

On Mon, 2015-11-16 at 16:16 +1100, David Gibson wrote: > On Wed, Nov 11, 2015 at 11:27:21AM +1100, Benjamin Herrenschmidt > wrote: > > Also use it to clamp the max SMT mode and ensure that the cpu_dt_id > > are offset by that value in order to preserve consistency with the >

Re: [Qemu-devel] [Qemu-ppc] [PATCH 09/77] ppc: Fix do_rfi() for rfi emulation

On Thu, 2015-11-19 at 21:23 +1100, Benjamin Herrenschmidt wrote: >  > I only just discovered that rfi is actually gone from arch 2.07 :-) > > I'll dig a bit more tomorrow. Ok, so I had a closer look and tore that stuff appart even more :-) If you are curious, feel free to check out

Re: [Qemu-devel] [Qemu-ppc] [PATCH 07/77] ppc: Add a bunch of hypervisor SPRs to Book3s

On Thu, 2015-11-19 at 17:11 +1100, David Gibson wrote: > On Wed, Nov 11, 2015 at 11:27:20AM +1100, Benjamin Herrenschmidt > wrote: > > We don't give them a KVM reg number yet as no current KVM version > > supports HV mode. > > > > Signed-off-by: Benjamin Herrensch

Re: [Qemu-devel] [Qemu-ppc] [PATCH 15/77] ppc: Fix sign extension issue in mtmsr(d) emulation

On Thu, 2015-11-19 at 17:26 +1100, David Gibson wrote: > On Wed, Nov 11, 2015 at 11:27:28AM +1100, Benjamin Herrenschmidt > wrote: > > From: Michael Neuling <mi...@neuling.org> > > > > Signed-off-by: Michael Neuling <mi...@neuling.org> > >

Re: [Qemu-devel] [Qemu-ppc] [PATCH 18/77] ppc: Rework POWER7 & POWER8 exception model

On Thu, 2015-11-19 at 17:44 +1100, David Gibson wrote: > > > -/* new interrupt handler msr */ > > -new_msr = env->msr & ((target_ulong)1 << MSR_ME); > > +/* new interrupt handler msr preserves existing HV and ME unless > > + * explicitly overriden > > + */ > > +new_msr =

Re: [Qemu-devel] [PATCH 45/77] qdev: Add a hook for a bus to device if it can add devices

On Wed, 2015-11-18 at 13:34 +0100, Paolo Bonzini wrote:  ../.. > Tabs for indentation.  There are other occurrences in the patch. Ooops. sorry, missed those. Do you need a respin ? > Apart from this, > > Reviewed-by: Paolo Bonzini > Acked-by: Paolo Bonzini

Re: [Qemu-devel] [Qemu-ppc] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only

On Mon, 2015-11-16 at 21:21 +1100, Benjamin Herrenschmidt wrote: > > Ah you are right. I do have second thoughts about that previous patch > now that you mention it however. In the real MSR, HV and PR are > independant, I wonder if I'm better off making the check explicit... > >

Re: [Qemu-devel] [PATCH v4 00/17] Add an IPMI device to QEMU

On Thu, 2015-11-12 at 13:02 -0600, miny...@acm.org wrote: > This is a long delayed patch set, but I think I have things reworked > to make Igor happy with the way ACPI and SMBIOS work.  This is more > consistent with the way most other things work, anyway.  It did > require adding stubs for

Re: [Qemu-devel] [Qemu-ppc] [PATCH 04/77] target-ppc: Use sensible POWER8/POWER8E versions

On Mon, 2015-11-16 at 16:01 +1100, David Gibson wrote: > On Wed, Nov 11, 2015 at 11:27:17AM +1100, Benjamin Herrenschmidt wrote: > > We never released anything older than POWER8 DD2.0 and POWER8E DD2.1, > > so let's use these versions, without that some firmware or Linux code > &

Re: [Qemu-devel] [Qemu-ppc] [PATCH 03/77] ppc: Do some batching of TCG tlb flushes

On Mon, 2015-11-16 at 16:00 +1100, David Gibson wrote: >  > >  //#define DEBUG_MMU > >  //#define DEBUG_BATS > > @@ -1940,6 +1941,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) > >  case POWERPC_MMU_2_03: > >  case POWERPC_MMU_2_06: > >  case POWERPC_MMU_2_07: > > +

Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/77] ppc: Use split I/D mmu modes to avoid flushes on interrupts

Thanks for reviewing ! On Mon, 2015-11-16 at 15:49 +1100, David Gibson wrote: > >  static inline void hreg_compute_mem_idx(CPUPPCState *env) > >  { > > -/* Precompute MMU index */ > > -if (msr_pr == 0 && msr_hv != 0) { > > -env->mmu_idx = 2; > > +/* This is our encoding for

Re: [Qemu-devel] [Qemu-ppc] [PATCH 13/77] ppc: tlbie, tlbia and tlbisync are HV only

On Mon, 2015-11-16 at 16:34 +1100, David Gibson wrote: > On Wed, Nov 11, 2015 at 11:27:26AM +1100, Benjamin Herrenschmidt > wrote: > > Not that anything remotely recent supports tlbia but ... > > > > Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.o

Re: [Qemu-devel] [PATCH 41/77] ppc/pnv: Add LPC controller and hook it up with a UART and RTC

On Tue, 2015-11-17 at 11:32 +1100, Alexey Kardashevskiy wrote: > On 11/11/2015 11:27 AM, Benjamin Herrenschmidt wrote: > > This adds a model of the POWER8 LPC controller. It is then used > > by the PowerNV code to attach a UART and RTC, which, with the right > > ver

Re: [Qemu-devel] [Qemu-ppc] [PATCH 04/77] target-ppc: Use sensible POWER8/POWER8E versions

On Tue, 2015-11-17 at 11:11 +1100, Alexey Kardashevskiy wrote: > > I have never heard of anyone testing migration of TCG guests. KVM guests > use host PVR anyway. > > I just wonder that we "never released anything older than" but we still > support them in the kernel - why do not we wipe these

[Qemu-devel] [PATCH 00/77] ppc: Add "native" POWER8 platform

This requires an OPAL firmware file which isn't included yet, will emulate enough to boot existing distros and run KVM inside TCG

[Qemu-devel] [PATCH 05/77] ppc: Update SPR definitions

Add definitions for additional SPR numbers and SPR bit definitions that will be relevant for subsequent improvements to POWER8 emulation Also fix the definition of LPIDR which was incorrect (and is different for server and embedded). Signed-off-by: Benjamin Herrenschmidt &l

[Qemu-devel] [PATCH 03/77] ppc: Do some batching of TCG tlb flushes

() on a boot to a ubuntu installer first dialog screen from roughly 360K down to 36K. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- hw/ppc/spapr_hcall.c | 12 +--- target-ppc/cpu.h | 2 ++ target-ppc/excp_helper.c | 9 + target-ppc/he

[Qemu-devel] [PATCH 01/77] ppc: Remove MMU_MODEn_SUFFIX definitions

We don't use the resulting accessors and this gets in the way of the split I/D TLB work. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/cpu.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index b34aed6..9ef0859

[Qemu-devel] [PATCH 08/77] ppc: Add number of threads per core to the processor definition

Also use it to clamp the max SMT mode and ensure that the cpu_dt_id are offset by that value in order to preserve consistency with the HW implementations. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/cpu-qom.h| 1 + target-ppc/translate_init

[Qemu-devel] [PATCH 09/77] ppc: Fix do_rfi() for rfi emulation

XXX This patch needs double checking... It fixed 32-bit userspace but I'm not sure it's right. I wonder whether msr_is_64bit() should be applied to env->msr, not msr, but I need to double check the architecture. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- t

[Qemu-devel] [PATCH 36/77] ppc/xics: Use a helper to add a new ICS

Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- hw/intc/xics.c| 6 ++ hw/intc/xics_spapr.c | 3 +-- include/hw/ppc/xics.h | 1 + 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 0c355f4..3cd696f 100644 --

[Qemu-devel] [PATCH 45/77] qdev: Add a hook for a bus to device if it can add devices

This allows a bus class to tell whether a given bus has room for any new device. max_dev isn't sufficient as the rules can depend on some arguments or can differ between instances of a bus. This will be used by PCI in subsequent patches Signed-off-by: Benjamin Herrenschmidt &l

[Qemu-devel] [PATCH 26/77] ppc/pnv: Add skeletton PowerNV platform

No devices yet, not even an interrupt controller, just to get started. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- default-configs/ppc64-softmmu.mak | 1 + hw/ppc/Makefile.objs | 2 + hw/ppc/pnv.c

[Qemu-devel] [PATCH 28/77] ppc/xics: Rename existing XICS classe to XICS_SPAPR

The common class doesn't change, the KVM one is SPAPR specific, this is a preliminary change to make it easier to support "native" XICS. Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- hw/intc/xics.c| 26 +- hw/intc/xi

[Qemu-devel] [PATCH 34/77] ppc/xics: An ICS with offset 0 is assumed to be uninitialized

This will make life easier for dealing with dynamically configured ICSes such as PHB3 Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- include/hw/ppc/xics.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h

[Qemu-devel] [PATCH 55/77] ppc/pnv+spapr: Add "ibm, pa-features" property to the device-tree

This is currently missing on both PowerNV and PAPR FIXME: Split patch & fix tabs Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- hw/ppc/pnv.c| 8 target-ppc/translate_init.c | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/ppc/pnv.

[Qemu-devel] [PATCH 66/77] ppc: Add a few more P8 PMU SPRs

Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- target-ppc/cpu.h| 7 +++ target-ppc/translate_init.c | 28 2 files changed, 35 insertions(+) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 756a66f..f7e653b

[Qemu-devel] [PATCH 53/77] ppc: Add proper real mode translation support

to limit to the max supported by the implementation (16G). Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org> --- hw/ppc/spapr.c | 7 +++ target-ppc/mmu-hash64.c | 146 ++-- target-ppc/mmu-hash64.h | 1 + targ

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