Re: [PATCH v4 1/1] hw/arm/sbsa-ref: use XHCI to replace EHCI

> On Jun 19, 2023, at 18:28, Peter Maydell wrote: > > On Wed, 7 Jun 2023 at 08:25, Chen Baozi wrote: >> >> >>> On Jun 7, 2023, at 10:33, Yuquan Wang wrote: >>> >>> The current sbsa-ref cannot use EHCI controller which is only >>&g

Re: [PATCH v4 1/1] hw/arm/sbsa-ref: use XHCI to replace EHCI

ty instead of EHCI. > > Signed-off-by: Yuquan Wang Signed-off-by: Chen Baozi mailto:chenba...@phytium.com.cn>>

Re: [PATCH 1/1] hw/arm/sbsa-ref: use XHCI to replace EHCI

Hi Leif, > On Jun 1, 2023, at 00:36, Leif Lindholm wrote: > > On 2023-05-31 16:27, Peter Maydell wrote: >> On Wed, 31 May 2023 at 15:58, Graeme Gregory wrote: The current sbsa-ref cannot use EHCI controller which is only able to do 32-bit DMA, since sbsa-ref doesn't have RAM above

[PATCH v4] target/arm: Add Neoverse-N1 registers

Add implementation defined registers for neoverse-n1 which would be accessed by TF-A. Since there is no DSU in Qemu, CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. Signed-off-by: Chen Baozi --- target/arm/cpu64.c | 69 ++ 1 file

Re: [PATCH v3] target/arm: Add Neoverse-N1 registers

Hi Richard, > On Mar 7, 2023, at 10:33, Richard Henderson > wrote: > > On 3/6/23 18:29, Richard Henderson wrote: >> On 3/6/23 18:14, Chen Baozi wrote: >>> Add implementation defined registers for neoverse-n1 which >>> would be accessed by TF-A. Since there i

[PATCH v3] target/arm: Add Neoverse-N1 registers

Add implementation defined registers for neoverse-n1 which would be accessed by TF-A. Since there is no DSU in Qemu, CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. Signed-off-by: Chen Baozi Tested-by: Marcin Juszkiewicz --- target/arm/cpu64.c | 2 ++ target/arm

[PATCH v2] target/arm: Add Neoverse-N1 registers

Add implementation defined registers for neoverse-n1 which would be accessed by TF-A. Since there is no DSU in Qemu, CPUCFR_EL1.SCU bit is set to 1 to avoid DSU registers definition. Signed-off-by: Chen Baozi Tested-by: Marcin Juszkiewicz --- target/arm/cpu64.c | 2 ++ target/arm

Re: [PATCH 1/2] target/arm: Add Neoverse-N1 registers

Hi Peter, > On Mar 6, 2023, at 19:33, Peter Maydell wrote: > > On Fri, 3 Mar 2023 at 16:15, Chen Baozi wrote: >> >> Add implementation defined registers for neoverse-n1 which >> would be accessed by TF-A. >> >> Signed-off-by: Chen Baozi >> --- &g

[PATCH 1/2] target/arm: Add Neoverse-N1 registers

Add implementation defined registers for neoverse-n1 which would be accessed by TF-A. Signed-off-by: Chen Baozi --- target/arm/cpu64.c | 2 ++ target/arm/cpu_tcg.c | 62 ++ target/arm/internals.h | 2 ++ 3 files changed, 66 insertions(+) diff

[PATCH 0/2] Define Impl. Def. registers for Neoverse-N1

TCG CPUs into tcg/. Therefore this patch should be rework once that patch has been merged. Chen Baozi (2): target/arm: Add Neoverse-N1 registers target/arm: Add DynamIQ Shared Unit control registers target/arm/cpu64.c | 2 + target/arm/cpu_tcg.c | 114

[PATCH 2/2] target/arm: Add DynamIQ Shared Unit control registers

DynamIQ Shared Unit (DSU) contains system control registers in the SCU and L3 logic which are implemented as the system registers for the cores in the cluster. Add DSU control registers and enable it to the supported cores. Signed-off-by: Chen Baozi --- target/arm/cpu_tcg.c | 52

[Qemu-devel] qemu on sparc host

Hello, I'm trying to emulate an x86 application on linux for sparc by using qemu user space emulator. However, it doesn't work correctly. Any ideas? Yours, sincerely Chen Baozi