next() in
> a counting loop. Change it to use drive_get() directly. This makes
> the unit numbers explicit in the code.
Acked-by: Edgar E. Iglesias
>
> Cc: Alistair Francis
> Cc: "Edgar E. Iglesias"
> Cc: Peter Maydell
> Cc: qemu-...@nongnu.org
> Signed-
next() in a
> counting loop. Change it to use drive_get() directly. This makes the
> unit numbers explicit in the code.
Acked-by: Edgar E. Iglesias
>
> Cc: "Edgar E. Iglesias"
> Signed-off-by: Markus Armbruster
> ---
> hw/microblaze/petalogix_m
in two
> counting loops, one of them in a helper function. Change it to use
> drive_get() directly. This makes the unit numbers explicit in the
> code.
Acked-by: Edgar E. Iglesias
>
> Cc: "Edgar E. Iglesias"
> Cc: Alistair Francis
> Cc: Peter Maydell
get_next() in
> several counting loops. Change it to use drive_get() directly. This
> makes the unit numbers explicit in the code.
Acked-by: Edgar E. Iglesias
>
> Cc: Alistair Francis
> Cc: "Edgar E. Iglesias"
> Cc: Peter Maydell
> Cc: qemu-...@nongnu.org
> Signe
-
> > -bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
> > - MMUAccessType access_type, int mmu_idx,
> > - bool probe, uintptr_t retaddr)
> > -{
> > -cs->exception_index = 0xaa;
> > -cpu_loop_exit_restore(cs, retaddr);
> > -}
> > -
> > -#else /* !CONFIG_USER_ONLY */
> > -
> > +#ifndef CONFIG_USER_ONLY
> > static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu,
> > MMUAccessType access_type)
> > {
> >
>
> To the best of my knowledge:
> Reviewed-by: Philippe Mathieu-Daudé
>
> But I'd feel safer with an Ack-by from Edgar :)
Sorry for the delays!
Reviewed-by: Edgar E. Iglesias
ZynqMP eFuse device
> >
> > hw/nvram/xlnx-efuse.c | 9 ++---
> > hw/nvram/xlnx-versal-efuse-ctrl.c | 20 +++-
> > hw/nvram/xlnx-zynqmp-efuse.c | 18 --
> > 3 files changed, 33 insertions(+), 14 deletions(-)
> >
>
> Series:
> Reviewed-by: Philippe Mathieu-Daudé
>
>
Reviewed-by: Edgar E. Iglesias
/char/cadence_uart: add clock support")
> 5b49a34c6800 ("hw/arm/xilinx_zynq: connect uart clocks to slcr")
Thanks Bin,
On the entire series:
Reviewed-by: Edgar E. Iglesias
On Wed, Sep 01, 2021 at 11:27:24AM +0800, Bin Meng wrote:
> Read or write to uart registers when unclocked or in reset should be
> ignored. Add the check there, and as a result of this, the check in
> uart_write_tx_fifo() is now unnecessary.
Hi Bin,
I thought I had replied to this but it must
; See changes in docs/system/arm/xlnx-versal-virt.rst for detail.
Thanks Tong,
On the entire series:
Acked-by: Edgar E. Iglesias
Tested-by: Edgar E. Iglesias
On Mon, Aug 23, 2021 at 08:10:50PM +0100, Peter Maydell wrote:
> On Mon, 23 Aug 2021 at 17:42, Philippe Mathieu-Daudé
> wrote:
> >
> > This series aim to kill a recent class of bug, the infamous
> > "DMA reentrancy" issues found by Alexander while fuzzing.
> >
> > Introduce the 'bus_perm' field
On Mon, Aug 23, 2021 at 02:43:26PM +1000, Alistair Francis wrote:
> On Mon, Aug 23, 2021 at 12:11 PM Bin Meng wrote:
> >
> > At present when input clock is disabled, any character transmitted
> > to tx fifo can still show on the serial line, which is wrong.
> >
> > Fixes: b636db306e06
h this change, upstream U-Boot boots properly again with:
> >
> > $ qemu-system-arm -M xilinx-zynq-a9 -m 1G -display none -serial null
> > -serial stdio \
> > -device loader,file=u-boot-dtb.bin,addr=0x400,cpu-num=0
> >
> > Fixes: 38867cb7ec90 ("h
},
> +};
> +
Nitpick, I'd probably drop this blank line and spell out the unsigned int below.
Also, we might want consider asserting that every array member has been
initialized. Eg assert(info->name) in the loop below. Unless perhaps something
already bails out in those cases (e.g sysbu
On Wed, Aug 18, 2021 at 08:15:24PM -0700, Tong Ho wrote:
> Add unimplemented APU mmio region to xlnx-versal for booting
> bare-metal guests built with standalone bsp published at:
>
> https://github.com/Xilinx/embeddedsw/tree/master/lib/bsp/standalone/src/arm/ARMv8/64bit
Reviewed
On Wed, Aug 18, 2021 at 09:02:59PM -0700, Tong Ho wrote:
> This series implements the Xilinx eFUSE and BBRAM devices for
> the Versal and ZynqMP product families.
>
> Furthermore, both new devices are connected to the xlnx-versal-virt
> board and the xlnx-zcu102 board.
Hi Tong,
A few general
On Mon, Aug 02, 2021 at 06:13:54PM -1000, Richard Henderson wrote:
> The kernel will fix up unaligned accesses, so emulate that
> by allowing unaligned accesses to succeed.
Reviewed-by: Edgar E. Iglesias
>
> Cc: Edgar E. Iglesias
> Signed-off-by: Richard Henderson
On Thu, Jul 29, 2021 at 08:00:50AM -1000, Richard Henderson wrote:
> On 7/29/21 3:26 AM, Peter Maydell wrote:
> > On Thu, 29 Jul 2021 at 01:54, Richard Henderson
> > wrote:
> > >
> > > Cc: Edgar E. Iglesias
> > > Signed-off-by: Richard Henderson
>
On Wed, Jun 23, 2021 at 06:55:49AM -0700, Richard Henderson wrote:
> On 6/23/21 6:43 AM, Edgar E. Iglesias wrote:
> > On Tue, Jun 22, 2021 at 08:48:16AM -0700, Richard Henderson wrote:
> > > Move delayed branch handling to tb_stop, where we can re-use other
> &g
On Tue, Jun 22, 2021 at 08:48:16AM -0700, Richard Henderson wrote:
> Move delayed branch handling to tb_stop, where we can re-use other
> end-of-tb code, e.g. the evaluation of flags. Honor single stepping.
> Validate that we aren't losing state by overwriting is_jmp.
Hi Richard,
This patch
OBJECT(s), "xram-irq-orgate",
> > >lpd.xram.irq_orgate, TYPE_OR_IRQ);
> >
>
> Fixes: a55b441b2ca ("hw/arm: versal: Add support for the XRAMs")
>
> > Reviewed-by: Richard Henderson
>
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
On Sun, Jun 20, 2021 at 02:32:47PM -0700, Richard Henderson wrote:
> By moving the code here, we can re-use other end-of-tb code,
> e.g. the evaluation of flags. Honor single stepping.
Hi Richard,
Unfortunately this patch seems to break one of the CRIS tests.
tests/tcg/cris/bare/check_xarith.s
On Thu, Jun 03, 2021 at 11:03:09AM +0200, Philippe Mathieu-Daudé wrote:
> Use the Exception Status Register definitions from "cpu.h".
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/helper.c | 16 -
On Thu, Jun 03, 2021 at 11:03:08AM +0200, Philippe Mathieu-Daudé wrote:
> See 'MicroBlaze Processor Reference Guide' UG081 (v9.0),
> Table 1-11: "Exception Status Register (ESR)".
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
>
On Thu, Jun 03, 2021 at 11:03:10AM +0200, Philippe Mathieu-Daudé wrote:
> Per the 'MicroBlaze Processor Reference Guide' UG081 (v9.0),
> "Hardware Exceptions" chapter:
>
> Exception Causes:
>
> * Instruction Bus Exception
>
> The instruction On-chip Peripheral Bus exception is caused by
On Thu, Jun 03, 2021 at 11:03:07AM +0200, Philippe Mathieu-Daudé wrote:
> If exceptions are disabled, we must not get a transaction failure.
> Assert they are enabled passed that point.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/microblaze/op_helper.c | 4 +---
> 1 file changed, 1
On Thu, Jun 03, 2021 at 11:03:06AM +0200, Philippe Mathieu-Daudé wrote:
> Extract FPU helpers to their own file: fpu_helper.c,
> so it is easier to focus on the generic helpers in
> op_helper.c.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
On Thu, Jun 03, 2021 at 11:03:05AM +0200, Philippe Mathieu-Daudé wrote:
> IEC binary prefixes ease code review: the unit is explicit.
>
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/mmu.c | 5 +++--
> 1 file changed,
On Wed, May 19, 2021 at 07:57:33PM +0200, Philippe Mathieu-Daudé wrote:
> On 5/19/21 2:03 AM, miny...@acm.org wrote:
> > From: Corey Minyard
> >
> > It's an ADC, put it where it belongs.
> >
> > Cc: Edgar E. Iglesias
> > Cc: Alistair Francis
> > C
ing the PHY address to 7,
> so let's use it.
>
> Cc: Bin Meng
> Signed-off-by: Guenter Roeck
Acked-by: Edgar E. Iglesias
> ---
> hw/arm/xilinx_zynq.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zy
: a generic one and the qdev one.
> Merge them into a reset_enter handler (keeping the IRQ lowering
> to a reset_hold one), and remove the qemu_register_reset() call.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> --
to a enter/hold resettable ones, and
> remove the qemu_register_reset() call.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/timer/etraxfs_timer.c | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletions(-)
>
> diff --gi
On Sun, May 02, 2021 at 12:13:49AM +0200, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé
>
> TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
> handler is called automatically when its qbus parent is reset
> (we don't need to register it manually).
>
> Convert
On Sun, May 02, 2021 at 12:13:49AM +0200, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé
>
> TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
> handler is called automatically when its qbus parent is reset
> (we don't need to register it manually).
>
> Convert
From: "Edgar E. Iglesias"
Connect the support for the Versal Accelerator RAMs (XRAMs).
Reviewed-by: Luc Michel
Acked-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
docs/system/arm/xlnx-versal-virt.rst | 1 +
include/hw/arm/xlnx-versal.h | 13 ++
h
From: "Edgar E. Iglesias"
Add a model of the Xilinx Versal Accelerator RAM (XRAM).
This is mainly a stub to make firmware happy. The size of
the RAMs can be probed. The interrupt mask logic is
modelled but none of the interrups will ever be raised
unless injected.
Signed-off-b
From: "Edgar E. Iglesias"
This series adds support for the 4x1MB Versal Accelerator RAMs (XRAMs).
Most of the controller is dummy, but it's got enough to make firmware
and some of our test SW happy.
Cheers,
Edgar
ChangeLog:
v1 -> v2:
* Reduce list of included files in both .h and
On Mon, Mar 08, 2021 at 04:54:26PM +, Peter Maydell wrote:
> On Tue, 2 Mar 2021 at 11:09, Edgar E. Iglesias
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > Add a model of the Xilinx Versal Accelerator RAM (XRAM).
> > This is mainly a stub to
On Tue, Mar 02, 2021 at 11:16:10PM +0800, Bin Meng wrote:
> Hi Edgar,
Hi Bin,
>
> On Tue, Mar 2, 2021 at 11:03 PM Edgar E. Iglesias
> wrote:
> >
> > On Mon, Mar 01, 2021 at 09:20:07PM +0800, Bin Meng wrote:
> > > From: Xuzhou Cheng
> > >
> > &g
On Mon, Mar 01, 2021 at 09:20:07PM +0800, Bin Meng wrote:
> From: Xuzhou Cheng
>
> ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
> is unimplemented. When QSPI is programmed to use DMA mode, QEMU will
> crash. This is observed when testing VxWorks 7.
>
> This adds a Xilinx
From: "Edgar E. Iglesias"
Add a model of the Xilinx Versal Accelerator RAM (XRAM).
This is mainly a stub to make firmware happy. The size of
the RAMs can be probed. The interrupt mask logic is
modelled but none of the interrups will ever be raised
unless injected.
Signed-off-b
From: "Edgar E. Iglesias"
Connect the support for the Versal Accelerator RAMs (XRAMs).
Signed-off-by: Edgar E. Iglesias
---
docs/system/arm/xlnx-versal-virt.rst | 1 +
include/hw/arm/xlnx-versal.h | 13 ++
hw/arm/xlnx-versal.c
From: "Edgar E. Iglesias"
This series adds support for the 4x1MB Versal Accelerator RAMs (XRAMs).
Most of the controller is dummy, but it's got enough to make firmware
and some of our test SW happy.
Cheers,
Edgar
Edgar E. Iglesias (2):
hw/misc: versal: Add a model of the XRAM contr
On Wed, Feb 24, 2021 at 08:50:20PM +0800, Bin Meng wrote:
> From: Xuzhou Cheng
>
> ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
> is unimplemented. When QSPI is programmed to use DMA mode, QEMU will
> crash. This is observed when testing VxWorks 7.
>
> This adds a Xilinx
On Tue, Feb 23, 2021 at 05:23:43PM +0800, Bin Meng wrote:
> Hi Edgar,
>
> On Tue, Feb 23, 2021 at 5:21 PM Edgar E. Iglesias
> wrote:
> >
> > On Mon, Feb 22, 2021 at 09:05:10PM +0800, Bin Meng wrote:
> > > From: Xuzhou Cheng
> > >
> > &g
On Tue, Feb 23, 2021 at 05:20:36PM +0800, Bin Meng wrote:
> Hi Edgar,
>
> On Tue, Feb 23, 2021 at 5:01 PM Edgar E. Iglesias
> wrote:
> >
> > On Mon, Feb 22, 2021 at 09:05:12PM +0800, Bin Meng wrote:
> > > From: Xuzhou Cheng
> > >
> > > Add
On Mon, Feb 22, 2021 at 09:15:00PM +0800, Bin Meng wrote:
> From: Xuzhou Cheng
>
> Add a Xilinx CSU DMA module to ZynqMP SoC, and connent the stream
> link of GQSPI to CSU DMA.
>
> Signed-off-by: Xuzhou Cheng
> Signed-off-by: Bin Meng
Reviewed-by: Edgar E. Iglesias
On Mon, Feb 22, 2021 at 09:05:10PM +0800, Bin Meng wrote:
> From: Xuzhou Cheng
>
> ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
> is unimplemented. When QSPI is programmed to use DMA mode, QEMU will
> crash. This is observed when testing VxWorks 7.
>
> This adds a Xilinx
only
> include the QSPI registers.
>
> Signed-off-by: Xuzhou Cheng
> Signed-off-by: Bin Meng
Reviewed-by: Edgar E. Iglesias
>
> ---
>
> Changes in v4:
> - Modify XLNX_ZYNQMP_SPIPS_R_MAX
>
> Changes in v3:
> - new patch: xilinx_spips: Remove DMA related code fro
;
> #define DP_ADDR 0xfd4a
> #define DP_IRQ 113
> @@ -63,6 +64,8 @@
> #define RTC_ADDR0xffa6
> #define RTC_IRQ 26
>
> +
> +
These blank lines look un-related, if you remove them, this looks good to me:
Reviewed-b
hw/arm/xlnx-zynqmp.c
>
> Let's clean them up.
>
> Signed-off-by: Xuzhou Cheng
> Signed-off-by: Bin Meng
Reviewed-by: Edgar E. Iglesias
>
> ---
>
> Changes in v4:
> - remove one change that is not a checkpatch warning
>
> include/hw/arm/xlnx-zynqmp.h |
On Mon, Feb 22, 2021 at 08:50:46AM +, Stefan Sandström wrote:
> Hi,
>
> > On 22 Feb 2021, at 09:41, Philippe Mathieu-Daudé wrote:
> >
> > Hi Edgar,
> >
> > On 2/22/21 9:33 AM, Edgar E. Iglesias wrote:
> >> From: Stefan Sandstrom
> &g
On Mon, Feb 22, 2021 at 09:41:16AM +0100, Philippe Mathieu-Daudé wrote:
> Hi Edgar,
>
> On 2/22/21 9:33 AM, Edgar E. Iglesias wrote:
> > From: Stefan Sandstrom
> >
> > Add and fix deallocation of temporary TCG registers in CRIS code
> > generation.
>
From: Stefan Sandstrom
Add and fix deallocation of temporary TCG registers in CRIS code
generation.
Tested-by: Edgar E. Iglesias
Reviewed-by: Edgar E. Iglesias
Change-Id: I17fce5d95bdc4418337ba885d53ba97afb1bafcc
Signed-off-by: Stefan Sandström
Reviewed-by: Richard Henderson
Message-Id
From: "Edgar E. Iglesias"
The following changes since commit 00d8ba9e0d62ea1c7459c25aeabf9c8bb7659462:
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-20210221' into
staging (2021-02-21 19:52:58 +)
are available in the Git repository at:
g...@github.co
Henderson
Reviewed-by: Edgar E. Iglesias
Message-Id: <20210128003223.3561108-3-f4...@amsat.org>
Signed-off-by: Edgar E. Iglesias
---
target/cris/mmu.h | 2 +-
target/cris/mmu.c | 24
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/cris/m
From: Philippe Mathieu-Daudé
Replace the 0/1/2 magic values by the corresponding MMUAccessType.
We can remove a comment as enum names are self explicit.
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
Message-Id: <20210128003223.356110
+ Richard (Since he had comments on v1)
On Fri, 19 Feb 2021, 13:44 Stefan Sandström, wrote:
> From: Stefan Sandstrom
>
> Add and fix deallocation of temporary TCG registers in CRIS code
> generation.
>
> Tested-by: Edgar E. Iglesias
> Reviewed-by: Edgar E.
next version.
Other than that, the patch looks good to me.
So, with those issues fixed, feel free to add the following tags:
Tested-by: Edgar E. Iglesias
Reviewed-by: Edgar E. Iglesias
Best regards,
Edgar
>
> Change-Id: I17fce5d95bdc4418337ba885d53ba97afb1bafcc
> Signed-off
On Thu, Feb 18, 2021 at 08:56:43AM +, Stefan Sandström wrote:
> From: Stefan Sandstrom
>
> Add and fix deallocation of temporary TCG registers in CRIS code
> generation.
Thanks Stefan,
Unfortunately, this patch does not apply. I'm not sure why.
Perhaps it got corrupted by the email systems
>
> Alistair
Hi Sai,
It would be great, if EMMC somehow could be made optional.
In any case, I think this is OK!
Reviewed-by: Edgar E. Iglesias
Could you please also add an example command-line in
docs/system/arm/xlnx-versal-virt.rst?
Thanks,
Edgar
>
> > ---
> > hw
From: "Edgar E. Iglesias"
Use nr_apu_cpus in favor of hard coding 2.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index b0777166e8..628e77ef66 100644
--
From: "Edgar E. Iglesias"
This is a minor clean-up making it a little easier to play around
with different CPU configurations.
Cheers,
Edgar
Edgar E. Iglesias (1):
hw/arm: versal: Use nr_apu_cpus in favor of hard coding 2
hw/arm/xlnx-versal.c | 4 ++--
1 file changed, 2 insert
On Wed, Feb 10, 2021 at 06:10:10PM +0800, Bin Meng wrote:
> From: Xuzhou Cheng
>
> There are some coding convention warnings in xlnx-zynqmp.c and
> xlnx-zynqmp.h, as reported by:
>
> $ ./scripts/checkpatch.pl include/hw/arm/xlnx-zynqmp.h
> $ ./scripts/checkpatch.pl hw/arm/xlnx-zynqmp.c
>
>
On Wed, Feb 10, 2021 at 06:10:09PM +0800, Bin Meng wrote:
> From: Xuzhou Cheng
>
> ZynqMP QSPI supports SPI transfer using DMA mode, but currently this
> is unimplemented. When QSPI is programmed to use DMA mode, QEMU will
> crash. This is observed when testing VxWorks 7.
>
> This adds a basic
by: Xuzhou Cheng
> Signed-off-by: Bin Meng
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
> ---
>
> (no changes since v1)
>
> hw/ssi/xilinx_spips.c | 23 ++-
> 1 file changed, 14 insertions(+), 9
On Wed, Feb 10, 2021 at 06:10:13PM +0800, Bin Meng wrote:
> From: Xuzhou Cheng
>
> Now that the XLNX CSU DMA model is implemented, the existing codes
> in the ZynqMP QSPIS are useless and should be removed.
We should also modify XLNX_ZYNQMP_SPIPS_R_MAX in the header file.
Otherwise, this looks
On Wed, Feb 10, 2021 at 06:10:11PM +0800, Bin Meng wrote:
> From: Xuzhou Cheng
>
> Insert XLNX CSU DMA module to ZynqMP SoC, and connent the stream
> link of GQSPI to CSU DMA.
>
> Signed-off-by: Xuzhou Cheng
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v3:
> - new patch: xlnx-zynqmp:
On Wed, Feb 10, 2021 at 05:08:01PM +0800, Bin Meng wrote:
> On Tue, Feb 9, 2021 at 10:30 AM Bin Meng wrote:
> >
> > Hi Edgar,
> >
> > On Mon, Feb 8, 2021 at 11:17 PM Edgar E. Iglesias
> > wrote:
> > >
> > >
> > >
> > > O
the
> > > > > > > > > other type.
> > > > > > > >
> > > > > > > > If we change view and see this from the perspective of
> m25p80, it models the
> > > > > > > > commands a certain way and provide
On Mon, 8 Feb 2021, 15:10 Bin Meng, wrote:
> Hi Edgar,
>
> On Mon, Feb 8, 2021 at 8:44 PM Edgar E. Iglesias
> wrote:
> >
> > On Mon, Feb 08, 2021 at 01:25:24PM +0800, Bin Meng wrote:
> > > From: Xuzhou Cheng
> > >
> > > ZynqMP QSPI
On Mon, Feb 8, 2021 at 3:45 PM Bin Meng wrote:
> Hi Edgar,
>
> On Mon, Feb 8, 2021 at 10:34 PM Edgar E. Iglesias
> wrote:
> >
> >
> >
> > On Mon, 8 Feb 2021, 15:10 Bin Meng, wrote:
> >>
> >> Hi Edgar,
> >>
> >> On Mon, Fe
rk
into the DMA. The DMA model is not upstream but can be found here:
https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c
Feel free to send a patch to upstream with that model (perhaps changing
the filename to something more suitable, e.g xlnx-csu-stream-dma.c).
You can use --author=
On Fri, Feb 05, 2021 at 11:18:28AM +, Peter Maydell wrote:
> On Fri, 5 Feb 2021 at 10:31, Philippe Mathieu-Daudé wrote:
> > 1/ virtio-mmio must be sysbus-device,
>
> Yes.
>
> > 2/ we can not sysbus-map out of main memory so private container
> > is incorrect, and Versal can not use
nteger. We can remove the documentation as enum
> > names are self explicit.
> >
> > Signed-off-by: Philippe Mathieu-Daudé
> > ---
> > target/cris/mmu.h | 2 +-
> > target/cris/mmu.c | 24
> > 2 files changed, 13 insertions(+), 13 deletion
-by: Philippe Mathieu-Daudé
> > ---
> > target/cris/helper.c | 4 ++--
> > target/cris/mmu.c| 13 ++---
> > 2 files changed, 8 insertions(+), 9 deletions(-)
> Reviewed-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
Can this go through the trivial tree?
Thanks,
Edgar
From: Joe Komlodi
Using the cfg.use_non_secure bitfield and the MMU access type, we can determine
if the access should be secure or not.
Signed-off-by: Joe Komlodi
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E. Iglesias
Message-Id: <1611274735-303873-4-git-send-email-koml...@xilinx.
From: Joe Komlodi
Using MMUAccessType makes it more clear what the variable's use is.
No functional change.
Signed-off-by: Joe Komlodi
Reviewed-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E. Iglesias
Message-Id: <1611274735-303873-3-git-send-email-k
From: "Edgar E. Iglesias"
The following changes since commit 9cd69f1a270235b652766f00b94114f48a2d603f:
Merge remote-tracking branch
'remotes/stefanberger/tags/pull-tpm-2021-01-25-1' into staging (2021-01-26
09:51:02 +)
are available in the Git repository at:
g...@github.co
.
Interfaces and their corresponding values are taken from:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-vivado-microblaze-ref.pdf
page 153.
Signed-off-by: Joe Komlodi
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E. Iglesias
Message-Id: <1611274735-303873-2-
face
>
> It works by enabling or disabling the use of the non_secure[3:0] signals.
>
> Interfaces and their corresponding values are taken from:
> https://www.xilinx.com/support/documentation/sw_manuals/xilinx2020_2/ug984-vivado-microblaze-ref.pdf
> page 153.
Thanks Joe!
Reviewed-by: E
On Thu, Jan 21, 2021 at 04:18:54PM -0800, Joe Komlodi wrote:
> Using MMUAccessType makes it more clear what the variable's use is.
> No functional change.
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E. Iglesias
>
> Signed-off-by: Joe Komlodi
> ---
> target/mi
On Thu, Jan 21, 2021 at 04:18:55PM -0800, Joe Komlodi wrote:
> Using the cfg.use_non_secure bitfield and the MMU access type, we can
> determine
> if the access should be secure or not.
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E. Iglesias
>
> Signed-off-
On Fri, Jan 22, 2021 at 01:21:53PM +, Peter Maydell wrote:
> Just noticed this wasn't cc'd to the Xilinx folks. Would one
> of you like to review it?
Looks good to me but we need to also update the test cases in
tests/qtest/xlnx-can-test.c.
Cheers,
Edgar
>
> thanks
> -- PMM
>
> On Mon,
On Wed, 13 Jan 2021, 11:19 Damien Hedde, wrote:
>
> This is ok but I'm afraid we may end up doing this kind of thing in a
> lot of devices. So maybe we should consider changing the behavior of
> device_is_in_reset() so that it returns false in the reset-exit case.
> What do you think ? (I've a
From: "Edgar E. Iglesias"
Correct the indexing into s->cpu_ctlr for vCPUs.
Signed-off-by: Edgar E. Iglesias
---
hw/intc/arm_gic.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index c60dc6b5e6..af41e2fb44 100644
From: "Edgar E. Iglesias"
Hi,
Found this while debugging an issue with lockups during boot of
Linux on Xen.
In the particular setup, I'm running without EL3 firmware so group0
interrupts are disabled on the physical interface and enabled on the
virtual interface.
Looks like we'r
uic.h header where it more naturally belongs.
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> include/hw/intc/ppc-uic.h | 7 +++
> include/hw/ppc/ppc4xx.h | 9 -
>
On Sat, Dec 12, 2020 at 12:15:30AM +, Peter Maydell wrote:
> In a following commit we will move the PPC UIC implementation to
> its own file in hw/intc. To prevent checkpatch complaining about that
> code-motion, fix up the minor style issues first.
Reviewed-by: Edgar E. Iglesia
rather than a rewrite (in new code it
> would be better to use tracepoints).
>
> The default property values for dcr-base and use-vectors are set to
> match those use by most of our boards with a UIC.
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E. Iglesias
>
> Signed
leaking the array of IRQs returned by ppcuic_init().
>
> Fixes: Coverity CID 1421992
> Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E. Iglesias
> ---
> hw/ppc/virtex_ml507.c | 21 -
> 1 file changed, 16 insertions(+),
cr)
> > -> "Register (slcr) ARM_PLL_CTRL"
> > 25.10.4 PLLs
> > -> "Software-Controlled PLL Update"
> >
> > Fixes: 38867cb7ec9 ("hw/misc/zynq_slcr: add clock generation for uarts")
> > Reported-by: Gaoning Pan
> > Signed-off-b
t; > +const char irq_name[] = "dwc_usb3";
> > +const char compat[] = "snps,dwc3";
>
> Minor coding style side note, but I'm not hugely fond of
> code blocks in the middle of functions just for declaring
> variables. You could either put these variable declarations
> at the top of the function, or if you think the code in the
> block is self contained and worth putting in its own function
> you could do that.
>
Hi Sai, I beleive I had already reviewed a previous version of this
patch so after you fix the stuff the Peter pointed out feel free to add my
Rb:
Reviewed-by: Edgar E. Iglesias
Cheers,
Edgar
_TLBX].
>
> Reported-by: Euler Robot
> Signed-off-by: Alex Chen
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/mmu.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/microblaze/mmu.c b/target/microblaze/mmu.c
> in
On Thu, Oct 22, 2020 at 05:47:33PM +0530, Sai Pavan Boddu wrote:
> This patch series attempts to make 'hcd-xhci' an independent model so it can
> be used by both pci and system-bus interface.
On the series:
Reviewed-by: Edgar E. Iglesias
>
> Changes for V2:
> Make XH
On Fri, Oct 23, 2020 at 10:35:49AM +0300, Pavel Dovgalyuk wrote:
> This patch sets min_cpus field for xlnx-versal-virt platform,
> because it always creates XLNX_VERSAL_NR_ACPUS cpus even with
> -smp 1 command line option.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by:
On Sat, Oct 10, 2020 at 12:31:28PM -0500, Richard Henderson wrote:
> The linux microblaze port only implements rt signal handing,
> not the old style. This allows our linux-test to pass for mb,
> if you have a cross-compiler available for the build.
Tested-by: Edgar E. Iglesias
On Mon, Oct 12, 2020 at 05:02:57PM +0100, Alex Bennée wrote:
>
> Alistair Francis writes:
>
> > On Fri, Oct 9, 2020 at 10:07 AM Alex Bennée wrote:
> >>
> >> Hi,
> >>
> >> This series adds the ability to append FDT data for blobs loaded by
> >> the generic loader. My principle use-case was to
On Tue, Sep 29, 2020 at 04:25:40PM +0530, Sai Pavan Boddu wrote:
> This module emulates control registers of versal usb2 controller, this is
> added
> just to make guest happy. In general this module would control the phy-reset
> signal from usb controller, data coherency of the transactions,
On Tue, Sep 29, 2020 at 04:25:41PM +0530, Sai Pavan Boddu wrote:
> From: Vikram Garhwal
>
> This patch adds skeleton model of dwc3 usb controller attached to
> xhci-sysbus device. It defines global register space of DWC3 controller,
> global registers control the AXI/AHB interfaces properties,
problem (likely trying to connect a clock to a device
> >> pre-dating the Clock API, thus not expecting clocks).
> >>
> >> Signed-off-by: Philippe Mathieu-Daudé
> >
> > Reviewed-by: Luc Michel
>
> Reviewed-by: Damien Hedde
Reviewed-by: Edgar E. Iglesia
201 - 300 of 2628 matches
Mail list logo
