Re: [PATCH v10 7/7] Versal: Connect DWC3 controller with virt-versal

On Thu, Sep 24, 2020 at 07:50:56PM +0530, Sai Pavan Boddu wrote: > From: Vikram Garhwal > > Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its placed > in iou of lpd domain and configure it as dual port host controller. Add the > respective guest dts nodes for "xlnx-versal-virt"

Re: [PATCH 00/13] dma: Let the DMA API take MemTxAttrs argument and propagate MemTxResult

On Wed, 16 Sep 2020, 15:48 Philippe Mathieu-Daudé, wrote: > On 9/4/20 5:44 PM, Philippe Mathieu-Daudé wrote: > > Salvaging cleanups patches from the RFC series "Forbid DMA write > > accesses to MMIO regions" [*], propagating MemTxResult and > > adding documentation. > > > > Philippe

Re: [PATCH v6 7/7] Versal: Connect DWC3 controller with virt-versal

On Wed, Sep 16, 2020 at 05:11:09PM +0530, Sai Pavan Boddu wrote: > From: Vikram Garhwal > > Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its placed > in iou of lpd domain and configure it as dual port host controller. Add the > respective guest dts nodes for "xlnx-versal-virt"

Re: [PATCH v5 5/7] misc: Add versal-usb2-regs module

On Thu, Sep 10, 2020 at 12:01:07PM +0530, Sai Pavan Boddu wrote: > This module emulates control registers of versal usb2 controller, this is > added > just to make guest happy. In general this module would control the phy-reset > signal from usb controller, data coherency of the transactions,

Re: [PATCH v5 7/7] Versal: Connect DWC3 controller with virt-versal

On Thu, Sep 10, 2020 at 12:01:09PM +0530, Sai Pavan Boddu wrote: > From: Vikram Garhwal > > Connect dwc3 controller and usb2-reg module to virt-versal. > Configure it as dual port host controller. > > Signed-off-by: Vikram Garhwal > Signed-off-by: Sai Pavan Boddu > --- >

Re: [PATCH v5 1/7] usb/hcd-xhci: Make dma read/writes hooks pci free

On Thu, Sep 10, 2020 at 12:01:03PM +0530, Sai Pavan Boddu wrote: > This patch starts making the hcd-xhci.c pci free, as part of this > restructuring dma read/writes are handled without passing pci object. > > Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias > --

Re: [PATCH 3/6] hw/dma/xilinx_axidma: Rename StreamSlave as StreamSink

> .parent= TYPE_OBJECT, > > -.instance_size = sizeof(struct XilinxAXIDMAStreamSlave), > > +.instance_size = sizeof(struct XilinxAXIDMAStreamSink), > > .class_init= xilinx_axidma_stream_class_init, > > .class_data = _axidma_data_stream_class, > > .interfaces = (InterfaceInfo[]) { > > @@ -646,7 +646,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = { > > static const TypeInfo xilinx_axidma_control_stream_info = { > > .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM, > > .parent= TYPE_OBJECT, > > -.instance_size = sizeof(struct XilinxAXIDMAStreamSlave), > > +.instance_size = sizeof(struct XilinxAXIDMAStreamSink), > > .class_init= xilinx_axidma_stream_class_init, > > .class_data= _axidma_control_stream_class, > > .interfaces = (InterfaceInfo[]) { > > > > Acked-by: Paolo Bonzini Reviewed-by: Edgar E. Iglesias

Re: [PATCH 2/6] hw/core/stream: Rename StreamSlave as StreamSink

tead of LAST and > have a flow-control mechanism that doesn't refer to valid/ready. IMO, > since we're not matching specific protocol names, it would be fine to > switch to generic terms like Source and Sink. > > Therefore, > > Acked-by: Paolo Bonzini &g

Re: [PATCH 4/6] hw/net/xilinx_axienet: Rename StreamSlave as StreamSink

t; > -.instance_size = sizeof(struct XilinxAXIEnetStreamSlave), > > +.instance_size = sizeof(struct XilinxAXIEnetStreamSink), > > .class_init= xilinx_enet_data_stream_class_init, > > .interfaces = (InterfaceInfo[]) { > > { TYPE_STREAM_SINK }, > > @@ -1057,7 +1057,7 @@ static const TypeInfo xilinx_enet_data_stream_info = { > > static const TypeInfo xilinx_enet_control_stream_info = { > > .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, > > .parent= TYPE_OBJECT, > > -.instance_size = sizeof(struct XilinxAXIEnetStreamSlave), > > +.instance_size = sizeof(struct XilinxAXIEnetStreamSink), > > .class_init= xilinx_enet_control_stream_class_init, > > .interfaces = (InterfaceInfo[]) { > > { TYPE_STREAM_SINK }, > > > > Acked-by: Paolo Bonzini Reviewed-by: Edgar E. Iglesias

[PATCH v2 1/1] hw/arm: versal-virt: Correct the tx/rx GEM clocks

From: "Edgar E. Iglesias" Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock. This matches the setup with the fixed-link 100Mbit PHY. It also avoids the following warnings from the Linux kernel driver: eth0: unable to generate target frequency: 12500 Hz Reviewed-by

[PATCH v2 0/1] hw/arm: versal-virt: Correct the tx/rx GEM clocks

From: "Edgar E. Iglesias" This corrects the Ethernet tx/rx clocks in the generated DTB. Avoids a Linux kernel warning. Cheers, Edgar ChangeLog: v1 -> v2: * Fix commit message typo, I -> It Edgar E. Iglesias (1): hw/arm: versal-virt: Correct the tx/rx GEM clocks hw/arm/xl

Re: [PATCH v1 1/1] hw/arm: versal-virt: Correct the tx/rx GEM clocks

On Wed, Sep 09, 2020 at 06:15:14PM +0200, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock. > This matches the setup with the fixed-link 100Mbit PHY. > I also avoids the following warnings from t

[PATCH v1 1/1] hw/arm: versal-virt: Correct the tx/rx GEM clocks

From: "Edgar E. Iglesias" Correct the GEMs tx/rx clocks to use the 125Mhz fixed-clock. This matches the setup with the fixed-link 100Mbit PHY. I also avoids the following warnings from the Linux kernel driver: eth0: unable to generate target frequency: 12500 Hz Signed-off-b

[PATCH v1 0/1] hw/arm: versal-virt: Correct the tx/rx GEM clocks

From: "Edgar E. Iglesias" This corrects the Ethernet tx/rx clocks in the generated DTB. Avoids a Linux kernel warning. Cheers, Edgar Edgar E. Iglesias (1): hw/arm: versal-virt: Correct the tx/rx GEM clocks hw/arm/xlnx-versal-virt.c | 2 +- 1 file changed, 1 insertion(+),

Re: [PATCH v3 00/19] target/microblaze improvements

> > * cpu vmstate is filled in > * interrupt logging is tidied. > > > r~ Looks good, none of the test issues were relatd. Thanks Richard! On all the patches I had not previously reviewed: Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Can you take the pull-req via your trees? Cheers, Edgar

Re: [PATCH 00/13] dma: Let the DMA API take MemTxAttrs argument and propagate MemTxResult

@nongnu.org/msg72924.html On the whole series: Reviewed-by: Edgar E. Iglesias > > Klaus Jensen (1): > pci: pass along the return value of dma_memory_rw > > Philippe Mathieu-Daudé (12): > docs/devel/loads-stores: Add regexp for DMA functions > dma: Document addr

Re: [PATCH 03/13] dma: Document address_space_map/address_space_unmap() prototypes

mory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t > len); > > +/** > + * address_space_map: Map a physical memory region into a DMA controller > + *virtual address It may be easier to understand this if you change DMA controll

Re: [PATCH v2 12/12] target/microblaze: Diagnose invalid insns in delay slots

Therefore, log a GUEST_ERROR and treat these cases as nops, to > avoid corner cases which could put qemu into an invalid state. > > Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias > Signed-off-by: Richard Henderson > --- > v2: Log pc as well. > --- &

Re: [PATCH v2 05/12] target/microblaze: Fill in VMStateDescription for cpu

32(fsr, CPUMBState), > +VMSTATE_UINT32(btr, CPUMBState), > +VMSTATE_UINT32(edr, CPUMBState), > +VMSTATE_UINT32(slr, CPUMBState), > +VMSTATE_UINT32(shr, CPUMBState), > +VMSTATE_UINT64(ear, CPUMBState), > + > +VMSTATE_UINT32(btarget, CPUMBState), > +VMSTATE_UINT32(imm, CPUMBState), > +VMSTATE_UINT32(iflags, CPUMBState), > + > +VMSTATE_UINT32(res_val, CPUMBState), > +VMSTATE_UINTTL(res_addr, CPUMBState), > + > +VMSTATE_UINT32_ARRAY(pvr.regs, CPUMBState, 13), pvr.regs are also elaboration time setup and should be read-only during the VM's lifetime. If you fix those, this looks good to me.: Reviewed-by: Edgar E. Iglesias

Re: [PATCH v2 04/12] target/microblaze: Rename mmu structs

On Thu, Sep 03, 2020 at 12:26:42AM -0700, Richard Henderson wrote: > Introduce typedefs and follow CODING_STYLE for naming. > Rename struct microblaze_mmu to MicroBlazeMMU. > Rename struct microblaze_mmu_lookup to MicroBlazeMMULookup. > > Signed-off-by: Richard Henderson Revie

Re: [RFC PATCH 00/12] hw: Forbid DMA write accesses to MMIO regions

On Thu, Sep 03, 2020 at 07:53:33PM +0200, Paolo Bonzini wrote: > On 03/09/20 17:50, Edgar E. Iglesias wrote: > >>> Hmm, I guess it would make sense to have a configurable option in KVM > >>> to isolate passthrough devices so they only can DMA to guest RAM... &g

Re: [RFC PATCH 00/12] hw: Forbid DMA write accesses to MMIO regions

On Thu, Sep 03, 2020 at 05:46:39PM +0200, Paolo Bonzini wrote: > On 03/09/20 16:24, Edgar E. Iglesias wrote: > >> [*] I do wonder about hardware-device-passthrough setups; I > >> don't think I would care to pass through an arbitrary device > >> to an untrusted gues

Re: [RFC PATCH 00/12] hw: Forbid DMA write accesses to MMIO regions

On Thu, Sep 03, 2020 at 02:58:19PM +0100, Peter Maydell wrote: > On Thu, 3 Sep 2020 at 14:37, Laszlo Ersek wrote: > > Peter mentions an approach at the end of > > that I believe > > to understand, but -- according to him -- it seems too

Re: [RFC PATCH 12/12] dma: Assert when device writes to indirect memory (such MMIO regions)

On Thu, Sep 03, 2020 at 01:08:31PM +0200, Philippe Mathieu-Daudé wrote: > Assert DMA accesses are done on direct memory (in particular > to catch invalid accesses to MMIO regions). Hi Philippe, Is the motivation for this to make it easier to find DMA programming errors? Shouldn't guest SW use

Re: [PATCH v3 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property

ard can specify > the PHY address for each GEM instance. > > Signed-off-by: Bin Meng Hi Bin, It looks like there's a change here compared to v2 to keep addr 0 as broadcast? Perhaps it would be useful to add a comment in the code about it. Anyway: Reviewed-by: Edgar E. Iglesias > >

Re: [PATCH] target/arm: Configure number of pmu counters

/* set number of pmu counters to 4 */ /* Set default number of PMU counters */ That way if the default changes you don't need to edit both code and comment. With those changes: Reviewed-by: Edgar E. Iglesias > +cpu->pmcrn = 4; > + > if (tcg_enabled()) { >

Re: [PATCH 0/6] target/microblaze: Use tcg_gen_lookup_and_goto_ptr

On Mon, Aug 31, 2020 at 11:40:12AM -0700, Richard Henderson wrote: > Based-on: <20200831160601.833692-1-richard.hender...@linaro.org> > ("[PULL 00/76] target/microblaze improvements") > > Hello again, Edgar. > > I had dropped the tcg_gen_lookup_and_goto_ptr patch from the > previous omnibus

Re: [PATCH 0/6] target/microblaze: Use tcg_gen_lookup_and_goto_ptr

is seems to fix the problem we ran into before. Series looks good both in review and testing except for minor typo in a comment. With the typo in patch #4 fixed: Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias > > > > Follow-up question: The manual says that s

Re: [PATCH 4/6] target/microblaze: Handle DISAS_EXIT_NEXT in delay slot

/* > + * Finish finish any return-from branch. Typo, 2x finish. With that fixed: Reviewed-by: Edgar E. Iglesias

Re: [PATCH v2 00/76] target/microblaze improvements

o me and it also passes my tests. So once you fix #27 feel free to add my RB & TB tags on the entire series. It's probably easiest if you send a pull-req via one of your trees. Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias Thanks again for working on this! Cheers, Edgar >

Re: [PATCH v2 27/76] target/microblaze: Check singlestep_enabled in gen_goto_tb

to avoid breaking bisection. Looks like this part slipped over to the next patch. With that fixed: Reviewed-by: Edgar E. Iglesias > +gen_helper_raise_exception(cpu_env, tmp); > +tcg_temp_free_i32(tmp); > +} else if (use_goto_tb(dc, dest)) { > tcg_gen_goto_tb(n

Re: [PATCH v1 2/2] target/microblaze: Improve transaction failure handling

On Fri, Aug 28, 2020 at 01:34:08PM -0700, Richard Henderson wrote: > On 8/28/20 4:39 AM, Edgar E. Iglesias wrote: > > +if ((access_type == MMU_INST_FETCH && cpu->cfg.iopb_bus_exception) || > > +(access_type != MMU_INST_FETCH &

Re: [PATCH 00/77] target/microblaze improvements

On Fri, 28 Aug 2020, 15:36 Richard Henderson, wrote: > On 8/27/20 10:09 AM, Edgar E. Iglesias wrote: > > It seems to be getting out of sync when getting a slave-error and the > core > > is not setup to take exceptions for slave errors. Looks like a > pre-existing > >

Re: [PATCH 00/77] target/microblaze improvements

On Tue, Aug 25, 2020 at 01:58:33PM -0700, Richard Henderson wrote: > Well, this is larger than I expected. > > I started off thinking conversion to decodetree would be quick, > after I reviewed the mttcg patches last week. Then I realized > that this could also use conversion to the generic

[PATCH v1 1/2] target/microblaze: Use CPU properties to conditionalize bus exceptions

From: "Edgar E. Iglesias" Use CPU properties, instead of PVR fields, to conditionalize bus exceptions. Fixes: 2867a96ffb ("target/microblaze: Add props enabling exceptions on failed bus accesses") Signed-off-by: Edgar E. Iglesias --- target/microblaze/op_helper.c | 4 ++-

[PATCH v1 2/2] target/microblaze: Improve transaction failure handling

From: "Edgar E. Iglesias" When the CPU has exceptions disabled, avoid unwinding CPU state and clobbering registers if we're not going to raise any exception. Signed-off-by: Edgar E. Iglesias --- target/microblaze/op_helper.c | 19 +++ 1 file changed, 7 inserti

[PATCH v1 0/2] target/microblaze: Improve bus fault handling

From: "Edgar E. Iglesias" Richards recent MicroBlaze patches exposed a bug in the MB ports bus fault handling. If the core is not setup for exceptions, we clobber the CPU state when preparing to raise one. This fixes the bug. Best regards, Edgar Edgar E. Iglesias (2): target/micro

Re: [PATCH v2 2/2] util/hexdump: Reorder qemu_hexdump() arguments

ave the FILE* argument > coming first). > > Reorder the arguments as "fp, prefix, buf, size" which is > more logical. > > Suggested-by: Peter Maydell > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias > --- > include/qemu-common.h|

Re: [PATCH v2 1/2] util/hexdump: Convert to take a void pointer argument

d-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias > --- > Since v1: > - renamed argument 'bufptr' (Peter Maydell) > --- > include/qemu-common.h| 3 ++- > hw/dma/xlnx_dpdma.c | 2 +- > hw/net/fsl_etsec/etsec.c | 2 +- > hw/sd/sd.c

Re: [PATCH 66/77] target/microblaze: Use tcg_gen_lookup_and_goto_ptr

On Tue, Aug 25, 2020 at 01:59:39PM -0700, Richard Henderson wrote: > When goto_tb cannot be used due to branch page crossing, > or due to indirect jumping, tcg_gen_lookup_and_goto_ptr > can be used instead. > > Signed-off-by: Richard Henderson Hi Richard, This patch is for some reason causing

Re: [PATCH 73/77] target/microblaze: Convert dec_stream to decodetree

On Tue, Aug 25, 2020 at 01:59:46PM -0700, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/microblaze/insns.decode | 6 > target/microblaze/translate.c | 64 ++ > 2 files changed, 55 insertions(+), 15 deletions(-) > > diff --git

Re: [PATCH 62/77] target/microblaze: Try to keep imm and delay slot together

On Tue, Aug 25, 2020 at 01:59:35PM -0700, Richard Henderson wrote: > If the last insn on a page is imm, or a branch with delay slot, > then end a tb early if this has not begun the tb. If it has > begun the tb, then we can allow the tb to span two pages as if > the imm plus its consumer, or

Re: [PATCH 00/77] target/microblaze improvements

On Thu, Aug 27, 2020 at 04:19:44AM -0700, Richard Henderson wrote: > On 8/27/20 3:22 AM, Edgar E. Iglesias wrote: > > Thanks. Here's another issue, it seems some branches are jumping > > to the wrong address. > > > > This is a disasm from a failing case: > >

Re: [PATCH 00/77] target/microblaze improvements

On Thu, Aug 27, 2020 at 03:01:57AM -0700, Richard Henderson wrote: > On 8/27/20 2:11 AM, Edgar E. Iglesias wrote: > > So a first general regression is that opcode 0 no longer > > traps as an illegal instruction (seems to be treated as an > > add with all r0). > > Oops

Re: [PATCH 64/77] target/microblaze: Convert mbar to decodetree

On Thu, Aug 27, 2020 at 02:58:06AM -0700, Richard Henderson wrote: > On 8/27/20 2:24 AM, Edgar E. Iglesias wrote: > >> +/* > >> + * Instruction access memory barrier. > >> + * End the TB so that we recognize self-modified code immediately. > >&

Re: [PATCH 64/77] target/microblaze: Convert mbar to decodetree

On Tue, Aug 25, 2020 at 01:59:37PM -0700, Richard Henderson wrote: > Split this out of the normal branch instructions, as it requires > special handling. End the TB only for an instruction barrier. > > Signed-off-by: Richard Henderson > --- > target/microblaze/insns.decode | 2 + >

Re: [PATCH 00/77] target/microblaze improvements

On Tue, Aug 25, 2020 at 01:58:33PM -0700, Richard Henderson wrote: > Well, this is larger than I expected. > > I started off thinking conversion to decodetree would be quick, > after I reviewed the mttcg patches last week. Then I realized > that this could also use conversion to the generic

Re: [PATCH 5/8] xlnx-zcu102: Use TYPE_ZCU102_MACHINE constant

On Wed, Aug 26, 2020 at 02:43:31PM -0400, Eduardo Habkost wrote: > This will make future conversion to use OBJECT_DECLARE* easier. > > Signed-off-by: Eduardo Habkost Reviewed-by: Edgar E. Iglesias > --- > Cc: Alistair Francis > Cc: "Edgar E. Iglesias" >

Re: [PATCH 00/77] target/microblaze improvements

On Tue, Aug 25, 2020 at 01:58:33PM -0700, Richard Henderson wrote: > Well, this is larger than I expected. > > I started off thinking conversion to decodetree would be quick, > after I reviewed the mttcg patches last week. Then I realized > that this could also use conversion to the generic

Re: [PATCH 02/77] tests/tcg: Do not require FE_TOWARDZERO

On Tue, Aug 25, 2020 at 01:58:35PM -0700, Richard Henderson wrote: > This is optional in ISO C, and not all cpus provide it. > > Cc: Alex Bennée > Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias > --- > tests/tcg/multiarch/float_convs.c | 2 ++ >

Re: [PATCH 03/77] tests/tcg: Do not require FE_* exception bits

On Tue, Aug 25, 2020 at 01:58:36PM -0700, Richard Henderson wrote: > Define anything that is missing as 0, so that flags & FE_FOO > is false for any missing FOO. > > Cc: Alex Bennée > Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias > ---

Re: [PATCH 01/77] tests/tcg: Add microblaze to arches filter

On Tue, Aug 25, 2020 at 01:58:34PM -0700, Richard Henderson wrote: > Not attempting to use a single cross-compiler for both > big-endian and little-endian at this time. > > Cc: Alex Bennée > Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias > --- > tests

Re: [PATCH 00/77] target/microblaze improvements

On Tue, Aug 25, 2020 at 01:58:33PM -0700, Richard Henderson wrote: > Well, this is larger than I expected. > Wow, thanks for working on this Richard! I'll run some tests on it and go through the patches. Thanks, Edgar > I started off thinking conversion to decodetree would be quick, > after

[PULL v1 6/8] target/microblaze: mbar: Trap sleeps from user-space

From: "Edgar E. Iglesias" Trap mbar-sleeps from user-space. Reviewed-by: Richard Henderson Reported-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/microblaze/translate.

[PULL v1 7/8] microblaze: petalogix-ml605: Add device-tree source

From: "Edgar E. Iglesias" Add a device-tree source for petalogix-ml605 and recompile the DTB. Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- pc-bios/petalogix-ml605.dtb | Bin 9982 -> 9882 bytes pc-bios/petalogix-ml

[PULL v1 8/8] microblaze: petalogix-s3adsp1800: Add device-tree source

From: "Edgar E. Iglesias" Add a device-tree source for petalogix-s3adsp1800 and recompile the DTB. This also removes the unused mpmc node which causes compilation warnings. Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- pc-bios

[PULL v1 3/8] target/microblaze: mbar: Add support for data-access barriers

From: "Edgar E. Iglesias" Add support for data-access barriers. Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/microblaze/translate.

[PULL v1 0/8] Xilinx queue 2020-08-14

From: "Edgar E. Iglesias" The following changes since commit 8367a77c4d3f6e1e60890f5510304feb2c621611: Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request' into staging (2020-08-23 16:34:43 +0100) are available in the Git repositor

[PULL v1 4/8] target/microblaze: swx: Use atomic_cmpxchg

From: "Edgar E. Iglesias" Use atomic_cmpxchg to implement the atomic cmpxchg sequence. Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 21 + 1 file changed, 13 insertions(+), 8

[PULL v1 5/8] configure: microblaze: Enable mttcg

From: "Edgar E. Iglesias" Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- configure | 1 + 1 file changed, 1 insertion(+) diff --git a/configure b/configure index 67832e3bab..b8f5b81a67 100755 --- a/configure +++ b/configure @@ -7782,6 +7782,7 @@ case &qu

[PULL v1 1/8] target/microblaze: mbar: Transfer dc->rd to mbar_imm

From: "Edgar E. Iglesias" Transfer dc->rd to mbar_imm to improve the readability when comparing to the specs. No functional change. Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 6 -- 1 fi

[PULL v1 2/8] target/microblaze: mbar: Move LOG_DIS to before sleep

From: "Edgar E. Iglesias" Move LOG_DIS log to before sleeping handling so that it logs for sleep instructions aswell. Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 3 ++- 1 file changed, 2 insert

Re: [PATCH v1 0/2] pc-bios: petalogix: Re-generate DTB and add DTS files

On Fri, Aug 21, 2020 at 01:02:59PM +0200, Philippe Mathieu-Daudé wrote: > Hi Edgar, > > On 8/20/20 9:43 PM, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > This adds missing device-tree source files for the petalogix boards > > with

[PATCH v1 1/2] microblaze: petalogix-ml605: Add device-tree source

From: "Edgar E. Iglesias" Add a device-tree source for petalogix-ml605 and recompile the DTB. Signed-off-by: Edgar E. Iglesias --- pc-bios/petalogix-ml605.dtb | Bin 9982 -> 9882 bytes pc-bios/petalogix-ml605.dts | 350 2 files changed, 3

[PATCH v1 2/2] microblaze: petalogix-s3adsp1800: Add device-tree source

From: "Edgar E. Iglesias" Add a device-tree source for petalogix-s3adsp1800 and recompile the DTB. This also removes the unused mpmc node which causes compilation warnings. Signed-off-by: Edgar E. Iglesias --- pc-bios/petalogix-s3adsp1800.dtb | Bin 8259 -> 8161 bytes pc-b

[PATCH v1 0/2] pc-bios: petalogix: Re-generate DTB and add DTS files

From: "Edgar E. Iglesias" This adds missing device-tree source files for the petalogix boards with recompiled DTBs. Cheers, Edgar Edgar E. Iglesias (2): microblaze: petalogix-ml605: Add device-tree source microblaze: petalogix-s3adsp1800: Add device-tree source pc-bios/petal

[PATCH v1 1/1] target/microblaze: mbar: Trap sleeps from user-space

From: "Edgar E. Iglesias" Trap mbar-sleeps from user-space. Reported-by: Richard Henderson Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/microblaze/translate.c b/target/microblaze/transla

[PATCH v1 0/1] target/microblaze: mbar: Trap sleeps from user-space

From: "Edgar E. Iglesias" As suggested by Richard, trap mbar/sleeps from user-space. Cheers, Edgar Edgar E. Iglesias (1): target/microblaze: mbar: Trap sleeps from user-space target/microblaze/translate.c | 5 + 1 file changed, 5 insertions(+) -- 2.25.1

Re: [PATCH v1 3/5] target/microblaze: mbar: Add support for data-access barriers

On Mon, Aug 17, 2020 at 08:42:04AM -0700, Richard Henderson wrote: > On 8/17/20 7:01 AM, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Add support for data-access barriers. > > > > Signed-off-by: Edgar E. Iglesias > > --- &g

Re: [PATCH v1 4/5] target/microblaze: swx: Use atomic_cmpxchg

On Mon, Aug 17, 2020 at 08:52:16AM -0700, Richard Henderson wrote: > On 8/17/20 7:01 AM, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Use atomic_cmpxchg to implement the atomic cmpxchg sequence. > > > > Signed-off-by: Edgar

Re: [PATCH v9 1/4] hw/net/can: Introduce Xilinx ZynqMP CAN controller

tcan,id=socketcan0,if=vcan0,canbus=canbus0 \ > > -object can-host-socketcan,id=socketcan1,if=vcan0,canbus=canbus1 > > > > To create virtual CAN on the host machine, please check the QEMU CAN docs: > > https://github.com/qemu/qemu/blob/master/docs/can.txt > > > >

Re: [PATCH] hw/net/xilinx_axienet: Remove unused code

On Fri, Aug 14, 2020 at 03:30:07PM +0200, Philippe Mathieu-Daudé wrote: > Most of the MDIOBus fields are unused. The ADVERTISE_10HALF > definition is unused. Remove unused code. Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/net/xil

[PATCH v1 4/5] target/microblaze: swx: Use atomic_cmpxchg

From: "Edgar E. Iglesias" Use atomic_cmpxchg to implement the atomic cmpxchg sequence. Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 21 + 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/target/microblaze/translate.

[PATCH v1 1/5] target/microblaze: mbar: Transfer dc->rd to mbar_imm

From: "Edgar E. Iglesias" Transfer dc->rd to mbar_imm to improve the readability when comparing to the specs. No functional change. Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/targ

[PATCH v1 0/5] target/microblaze: Enable MTTCG

From: "Edgar E. Iglesias" This series adds translation for memory barrier instructions and changes the store-exclusive implementation to use cmpxhg rather than relying on single-threaded TCG. This is primarily in preparation for future AMP machines. Cheers, Edgar Edgar E. I

[PATCH v1 3/5] target/microblaze: mbar: Add support for data-access barriers

From: "Edgar E. Iglesias" Add support for data-access barriers. Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 5 + 1 file changed, 5 insertions(+) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index c1be76d4c8..c58f334

[PATCH v1 5/5] configure: microblaze: Enable mttcg

From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- configure | 1 + 1 file changed, 1 insertion(+) diff --git a/configure b/configure index 2acc4d1465..2f7adaa6ae 100755 --- a/configure +++ b/configure @@ -8162,6 +8162,7 @@ case "$target_name" in mic

[PATCH v1 2/5] target/microblaze: mbar: Move LOG_DIS to before sleep

From: "Edgar E. Iglesias" Move LOG_DIS log to before sleeping handling so that it logs for sleep instructions aswell. Signed-off-by: Edgar E. Iglesias --- target/microblaze/translate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/microblaze/translate.

Re: [PATCH] target/arm: Clarify HCR_EL2 ARMCPRegInfo type

t; Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Edgar E. Iglesias > --- > target/arm/helper.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 455c92b891..9aeb8ebfa9 100644 > --- a/target/arm/helper.c > +++ b/targe

Re: [PATCH v8 2/4] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers

On Tue, Aug 04, 2020 at 02:11:43PM -0700, Vikram Garhwal wrote: > Connect CAN0 and CAN1 on the ZynqMP. Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Vikram Garhwal > --- > hw/arm/xlnx-zcu102.c | 20 > hw/arm/xlnx-zyn

Re: [PATCH v8 1/4] hw/net/can: Introduce Xilinx ZynqMP CAN controller

on the host machine, please check the QEMU CAN docs: > https://github.com/qemu/qemu/blob/master/docs/can.txt Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Vikram Garhwal > --- > hw/net/can/Makefile.objs |1 + > hw/net/can/xlnx-zynqmp-can.c | 1152 > ++

[PATCH v1 1/1] docs/system/arm: Document the Xilinx Versal Virt board

From: "Edgar E. Iglesias" Document the Xilinx Versal Virt board. Signed-off-by: Edgar E. Iglesias --- docs/system/arm/xlnx-versal-virt.rst | 176 +++ docs/system/target-arm.rst | 1 + MAINTAINERS | 3 +- 3 files ch

[PATCH v1 0/1] docs/system/arm: Document the Xilinx Versal Virt board

From: "Edgar E. Iglesias" Hi, This adds some basic documentation for the Xilinx Versal Virt board, including a few command-line examples on how to run ARM Trusterd Firmware, U-boot, Xen and Linux. If this looks OK I'll send similar basic documentation for the ZynqMP and Zynq. Be

Re: [PATCH v7 1/4] hw/net/can: Introduce Xilinx ZynqMP CAN controller

On Wed, Jul 08, 2020 at 09:23:54PM +, Vikram Garhwal wrote: > Hi Edgar, > Thanks for reviewing the patch. Please see some comments. > > > -Original Message- > > From: Edgar E. Iglesias > > Sent: Tuesday, July 7, 2020 5:49 AM > > To: Vikram Garhw

Re: [PATCH v7 1/4] hw/net/can: Introduce Xilinx ZynqMP CAN controller

On Thu, Jun 25, 2020 at 12:33:24PM -0700, Vikram Garhwal wrote: > The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus > implementation. Bus connection and socketCAN connection for each CAN module > can be set through command lines. > > Example for using single CAN: >

Re: [PATCH v7 2/4] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers

On Thu, Jun 25, 2020 at 12:33:25PM -0700, Vikram Garhwal wrote: > Connect CAN0 and CAN1 on the ZynqMP. > > Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias > Signed-off-by: Vikram Garhwal > --- > hw/arm/xlnx-zynqmp.c | 28

Re: [PATCH 09/14] hw/display/xlnx_dp: Replace disabled DPRINTF() by error_report()

On Tue, May 26, 2020 at 08:22:47AM +0200, Philippe Mathieu-Daudé wrote: > DPRINTF() calls are disabled by default, so when unexpected > data is used, the whole process abort without information. > > Display a bit of information with error_report() before crashing. Reviewed-by: Edgar

Re: [PATCH v2] tests/acceptance: Add a boot test for the xlnx-versal-virt machine

ow. Great, thanks Thomas! Reviewed-by: Edgar E. Iglesias > > Reviewed-by: Philippe Mathieu-Daudé > Tested-by: Philippe Mathieu-Daudé > Signed-off-by: Thomas Huth > --- > v2: Added "tags=device:pl011" and "tags=device:arm_gicv3" > > tests/accepta

Re: [PATCH v1 0/1] target/microblaze: Add GDB XML files

On Thu, May 21, 2020 at 09:02:14PM -0700, Joe Komlodi wrote: > Hi all, > > This adds GDB XML files for Microblaze CPUs. > For Microblaze, it's split up into core and stack protect XML files. Hi Joe, Can you please add a license header to microblaze-core.xml? I think you wrote this on your own

Re: [PATCH v9 59/74] microblaze: convert to cpu_interrupt_request

On Thu, May 21, 2020 at 12:39:56PM -0400, Robert Foley wrote: > From: "Emilio G. Cota" > > Cc: "Edgar E. Iglesias" > Reviewed-by: Richard Henderson > Reviewed-by: Alex Bennée > Signed-off-by: Emilio G. Cota > Signed-off-by: Robert Foley Reviewed

Re: [PATCH v9 47/74] cris: convert to cpu_interrupt_request

On Thu, May 21, 2020 at 12:39:44PM -0400, Robert Foley wrote: > From: "Emilio G. Cota" > > Cc: "Edgar E. Iglesias" > Reviewed-by: Richard Henderson > Reviewed-by: Alex Bennée > Signed-off-by: Emilio G. Cota > Signed-off-by: Robert Foley Reviewed

Re: [PATCH v9 10/74] cris: convert to helper_cpu_halted_set

On Thu, May 21, 2020 at 12:39:07PM -0400, Robert Foley wrote: > From: "Emilio G. Cota" > > And fix the temp leak along the way. > > Cc: "Edgar E. Iglesias" > Reviewed-by: Richard Henderson > Reviewed-by: Alex Bennée > Signed-off-by: Emilio G. Co

Re: [PATCH v9 14/74] microblaze: convert to helper_cpu_halted_set

On Thu, May 21, 2020 at 12:39:11PM -0400, Robert Foley wrote: > From: "Emilio G. Cota" > > Cc: "Edgar E. Iglesias" > Reviewed-by: Richard Henderson > Reviewed-by: Alex Bennée > Signed-off-by: Emilio G. Cota > Signed-off-by: Robert Foley Reviewed

Re: [PATCH v5 1/4] hw/net/can: Introduce Xilinx ZynqMP CAN controller

On Sun, May 17, 2020 at 12:24:01AM -0700, Vikram Garhwal wrote: > The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus > implementation. Bus connection and socketCAN connection for each CAN module > can be set through command lines. Hi Vikram, Have a look at

Re: [PATCH 3/4] hw/char/xilinx_uartlite: Replace hw_error() by qemu_log_mask()

w_error() calls by qemu_log_mask(). Reviewed-by: Edgar E. Iglesias > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/char/xilinx_uartlite.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c &

Re: [PATCH 02/24] display/xlnx_dp: Fix to realize "i2c-ddc" and "aux-to-i2c-bridge"

s, then we've always been missing these > two devices, yet nobody noticed. > > Fix by realizing them in xlnx_dp_realize(). Reviewed-by: Edgar E. Iglesias > > Fixes: 58ac482a66de09a7590f705e53fc6a3fb8a055e8 > Cc: KONRAD Frederic > Cc: Alistair Francis > Cc: &qu

[PULL v1 14/14] target/microblaze: monitor: Increase the number of registers reported

From: Joe Komlodi Increase the number of registers reported to match GDB. Registers that aren't modeled are reported as 0. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Message-Id: <1589393329-223076-4-git-send-email-koml...@xilinx.com> Signed-off-by: Edgar E. Ig

[PULL v1 13/14] target/microblaze: gdb: Fix incorrect SReg reporting

-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Message-Id: <1589393329-223076-3-git-send-email-koml...@xilinx.com> Signed-off-by: Edgar E. Iglesias --- target/microblaze/gdbstub.c | 59 ++--- 1 file changed, 49 insertions(+), 10 deletions(-) diff --git a/

[PULL v1 11/14] target/microblaze: Fix FPU2 instruction check

From: Joe Komlodi The check to see if we can use FPU2 instructions would return 0 if cfg.use_fpu == 2, rather than returning the PVR2_USE_FPU2_MASK. This would cause all FPU2 instructions (fsqrt, flt, fint) to not be used. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Message-Id

[PULL v1 09/14] MAINTAINERS: Add myself as streams maintainer

From: "Edgar E. Iglesias" Since we're missing a maintainer, add myself. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20200506082513.18751-10-edgar.igles...@gmail.com> --- MAINTAINERS | 6 ++ 1 file chang

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