On Thu, May 21, 2020 at 12:39:07PM -0400, Robert Foley wrote:
> From: "Emilio G. Cota"
>
> And fix the temp leak along the way.
>
> Cc: "Edgar E. Iglesias"
> Reviewed-by: Richard Henderson
> Reviewed-by: Alex Bennée
> Signed-off-by: Emilio G. Co
On Thu, May 21, 2020 at 12:39:11PM -0400, Robert Foley wrote:
> From: "Emilio G. Cota"
>
> Cc: "Edgar E. Iglesias"
> Reviewed-by: Richard Henderson
> Reviewed-by: Alex Bennée
> Signed-off-by: Emilio G. Cota
> Signed-off-by: Robert Foley
Reviewed
On Sun, May 17, 2020 at 12:24:01AM -0700, Vikram Garhwal wrote:
> The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
> implementation. Bus connection and socketCAN connection for each CAN module
> can be set through command lines.
Hi Vikram,
Have a look at
w_error() calls by qemu_log_mask().
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/char/xilinx_uartlite.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c
&
s, then we've always been missing these
> two devices, yet nobody noticed.
>
> Fix by realizing them in xlnx_dp_realize().
Reviewed-by: Edgar E. Iglesias
>
> Fixes: 58ac482a66de09a7590f705e53fc6a3fb8a055e8
> Cc: KONRAD Frederic
> Cc: Alistair Francis
> Cc: &qu
From: Joe Komlodi
Increase the number of registers reported to match GDB.
Registers that aren't modeled are reported as 0.
Signed-off-by: Joe Komlodi
Reviewed-by: Edgar E. Iglesias
Message-Id: <1589393329-223076-4-git-send-email-koml...@xilinx.com>
Signed-off-by: Edgar E. Ig
-by: Joe Komlodi
Reviewed-by: Edgar E. Iglesias
Message-Id: <1589393329-223076-3-git-send-email-koml...@xilinx.com>
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/gdbstub.c | 59 ++---
1 file changed, 49 insertions(+), 10 deletions(-)
diff --git a/
From: Joe Komlodi
The check to see if we can use FPU2 instructions would return 0 if
cfg.use_fpu == 2, rather than returning the PVR2_USE_FPU2_MASK.
This would cause all FPU2 instructions (fsqrt, flt, fint) to not be used.
Signed-off-by: Joe Komlodi
Reviewed-by: Edgar E. Iglesias
Message-Id
From: "Edgar E. Iglesias"
Since we're missing a maintainer, add myself.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20200506082513.18751-10-edgar.igles...@gmail.com>
---
MAINTAINERS | 6 ++
1 file chang
From: "Edgar E. Iglesias"
Stream descriptor by descriptor from memory instead of
buffering entire packets before pushing. This enables
non-packet streaming clients to work and also lifts the
limitation that our internal DMA buffer needs to be able
to hold entire packets.
Reviewed-by
From: "Edgar E. Iglesias"
Add DMA memory-region property to externally control what
address-space this DMA operates on.
Reviewed-by: Alistair Francis
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <202005060
From: Joe Komlodi
Increase the number of Microblaze registers QEMU will report when
talking to GDB.
Signed-off-by: Joe Komlodi
Reviewed-by: Edgar E. Iglesias
Message-Id: <1589393329-223076-2-git-send-email-koml...@xilinx.com>
Signed-off-by: Edgar E. Iglesias
---
target/microblaze
From: "Edgar E. Iglesias"
Some stream clients stream an endless stream of data while
other clients stream data in packets. Stream interfaces
usually have a way to signal the end of a packet or the
last beat of a transfer.
This adds an end-of-packet flag to the push interface.
guest encounters an exception.
Signed-off-by: Tong Ho
Reviewed-by: Edgar E. Iglesias
Reviewed-by: Luc Michel
Message-Id: <20200512143649.21655-2-edgar.igles...@gmail.com>
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 1 +
1 file changed, 1 insertion(+)
diff
From: "Edgar E. Iglesias"
Add support for stream fragments.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
Message-Id: <20200506082513.18751-9-edgar.igles...@gmail.com>
---
hw/dma/xilinx_axidma.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletion
From: "Edgar E. Iglesias"
Add support for fragmented packets from the DMA.
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Message-Id: <20200506082513.18751-7-edgar.igles...@gmail.com>
---
hw/net/xilinx_axienet.c | 38 +++---
From: "Edgar E. Iglesias"
Split the shared stream_class_init function to assign
stream->push with better type-safety.
Reviewed-by: Alistair Francis
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <202005
From: "Edgar E. Iglesias"
The following changes since commit 035b448b84f3557206abc44d786c5d3db2638f7d:
Merge remote-tracking branch 'remotes/gkurz/tags/9p-next-2020-05-14' into
staging (2020-05-14 10:58:30 +0100)
are available in the Git repository at:
g...@github.com:edgarig
From: "Edgar E. Iglesias"
Remove unncessary cast, buf is already uint8_t *.
No functional change.
Reviewed-by: Alistair Francis
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Reviewed-by: Philippe Mathieu-Daudé
Message-Id: <20200506082513.18751-4-edgar.igles
From: "Edgar E. Iglesias"
Auto-clear PHY CR Autoneg bits. This makes this model
work with recent Linux kernels.
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
Message-Id: <20200506082513.18751-2-edgar.igles...@gmail.com>
---
hw/net/xilinx_axienet.c | 4 ++--
On Thu, May 07, 2020 at 04:18:17PM +0100, Peter Maydell wrote:
> Provide a minimal documentation of the Versatile Express boards
> (vexpress-a9, vexpress-a15).
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> docs/system/arm
On Thu, May 07, 2020 at 04:18:19PM +0100, Peter Maydell wrote:
> Provide a minimal documentation of the Musca boards.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> docs/system/arm/musca.rst | 31 +++
> docs/system/t
On Thu, May 07, 2020 at 04:18:18PM +0100, Peter Maydell wrote:
> Add basic documentation of the MPS2 board models.
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Peter Maydell
> ---
> docs/system/arm/mps2.rst | 29 +
> docs/system/t
On Thu, May 07, 2020 at 04:18:16PM +0100, Peter Maydell wrote:
> Sort the board index into alphabetical order. (Note that we need to
> sort alphabetically by the title text of each file, which isn't the
> same ordering as sorting by the filename.)
Reviewed-by: Edgar E. Iglesias
&g
On Wed, May 13, 2020 at 11:08:45AM -0700, Joe Komlodi wrote:
> Add dynamic GDB register XML for Microblaze, and modify the config file to
> use XML when building for Microblaze.
> For the dynamic XML to be read, there still needs to be a core XML file.
Hi Joe,
I was looking a little closer at
ght now to maintain
> compatibility with GDB.
Hi Joe,
I've taken patches #2 - 4 into my queue.
Patch #1 needs some more work.
Thanks,
Edgar
>
> Thanks!
> Joe
>
> Reviewed-by: Edgar E. Iglesias
>
> Changelog:
> v1 -> v2
> - 1/4: Added missing core XML file
>
On Thu, May 07, 2020 at 04:18:15PM +0100, Peter Maydell wrote:
> Add 'Arm' to the Integrator/CP document title, for consistency with
> the titling of the other documentation of Arm devboard models
> (versatile, realview).
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by
On Wed, May 13, 2020 at 11:08:48AM -0700, Joe Komlodi wrote:
> Increase the number of registers reported to match GDB.
>
> Registers that aren't modeled are reported as 0.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Joe Komlodi
> ---
> target/microb
On Wed, May 13, 2020 at 11:08:46AM -0700, Joe Komlodi wrote:
> Increase the number of Microblaze registers QEMU will report when
> talking to GDB.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Joe Komlodi
> ---
> target/microblaze/cpu.c | 2 +-
> target/micr
ister GDB wants to its
> location in the SRegs array.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Joe Komlodi
> ---
> target/microblaze/gdbstub.c | 59
> +
> 1 file changed, 49 insertions(+), 10 deletions(-)
>
>
On Mon, May 11, 2020 at 10:05:47AM -0700, Joe Komlodi wrote:
> Hi all,
>
> This series adds dynamic GDB XML support for Micraoblaze CPUs, and fixes
> an issue when reporting Microblaze SRegs through GDB.
>
> The SRegs used to be printed out by iterating over the SReg array, but the
> SReg array
o maintain compatibility with GDB.
>
> Thanks!
> Joe
Thanks Joe!
Reviewed-by: Edgar E. Iglesias
>
> Joe Komlodi (4):
> target/microblaze: gdb: Add dynamic GDB XML register support
> target/microblaze: gdb: Extend the number of registers presented to
> GDB
> tar
On Mon, May 11, 2020 at 10:49:05AM -0700, Joe Komlodi wrote:
> Hi all,
>
> This fixes a backwards if statement that caused Microblaze FPU2 instructions
> to not be executed, even if use-fpu=2 in the DTS.
>
> Thanks!
> Joe
Reviewed-by: Edgar E. Iglesias
>
>
On Tue, May 12, 2020 at 08:24:50PM +0530, Sai Pavan Boddu wrote:
> Add a property "jumbo-max-len", which sets default value of jumbo frames
> up to 16,383 bytes. Add Frame length checks for standard and jumbo
> frames.
Reviewed-by: Edgar E. Iglesias
>
> Signe
On Tue, May 12, 2020 at 08:24:49PM +0530, Sai Pavan Boddu wrote:
> Fix the code style for register definitions.
>
Reviewed-by: Edgar E. Iglesias
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/net/cadence_gem.c | 204
> ++-
>
guest encounters an exception.
Signed-off-by: Tong Ho
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 20b7427811..92b3630804
From: "Edgar E. Iglesias"
We're missing mfs from EDR support, this adds it.
Showed up in Xilinx Versal PLM code.
Cheers,
Edgar
Tong Ho (1):
target/microblaze: Add MFS Rd,EDR translation
target/microblaze/translate.c | 1 +
1 file changed, 1 insertion(+)
--
2.20.1
On Sat, May 09, 2020 at 03:09:01PM +0200, Philippe Mathieu-Daudé wrote:
> Restrict init_machine(), setup_post() and has_memory()
> to system-mode.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/sysemu/accel.h | 2 ++
> 1 file
On Sat, May 09, 2020 at 03:09:03PM +0200, Philippe Mathieu-Daudé wrote:
> When HVF is not available, the tcg_allowed variable does not exist.
Typo in commit message tcg_allowed -> hvf_allowed.
With that fixed:
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe M
On Sat, May 09, 2020 at 03:09:02PM +0200, Philippe Mathieu-Daudé wrote:
> When TCG is not available, the tcg_allowed variable does not exist.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/sysemu/tcg.h | 2 +-
> 1 file changed,
On Fri, May 08, 2020 at 04:30:41PM +0530, Sai Pavan Boddu wrote:
> Add a property "jumbo-max-len", which can be configured for jumbo frame size
> up to 16,383 bytes, and also introduce new register GEM_JUMBO_MAX_LEN.
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/net/cadence_gem.c | 21
p = tx_packet;
> +p = s->tx_packet;
> total_bytes = 0;
> }
>
> @@ -1612,6 +1610,17 @@ static void gem_realize(DeviceState *dev, Error **errp)
>
> s->nic = qemu_new_nic(_gem_info, >conf,
>object_get_typename(OBJECT(dev)), dev->id, s);
> +
> +s->tx_packet = g_new0(uint8_t, MAX_FRAME_SIZE);
> +s->rx_packet = g_new0(uint8_t, MAX_FRAME_SIZE);
Hi Sai,
Since you're only using MAX_FRAME_SIZE these could be arrays
in CadenceGEMState.
With that change:
Reviewed-by: Edgar E. Iglesias
On Fri, May 08, 2020 at 04:30:36PM +0530, Sai Pavan Boddu wrote:
> During wrap around and reset, queues are pointing to initial base
> address of queue 0, irrespective of what queue we are dealing with.
> Fix it by assigning proper base address every time.
Reviewed-by: Edgar E.
On Fri, May 08, 2020 at 04:30:35PM +0530, Sai Pavan Boddu wrote:
> Enabling debug breaks the build, Fix them and make debug statements
> always compilable. Fix few statements to use sized integer casting.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Sai Pavan Boddu
>
On Wed, May 06, 2020 at 01:53:33PM +0200, Philippe Mathieu-Daudé wrote:
> Hi Edgar,
Hi Philippe,
>
> On 5/6/20 10:25 AM, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Some stream clients stream an endless stream of data while
> > o
From: "Edgar E. Iglesias"
Stream descriptor by descriptor from memory instead of
buffering entire packets before pushing. This enables
non-packet streaming clients to work and also lifts the
limitation that our internal DMA buffer needs to be able
to hold entire packets.
Reviewed-by
From: "Edgar E. Iglesias"
Add support for fragmented packets from the DMA.
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 38 +++---
1 file changed, 31 insertions(+), 7 deletions(-)
diff --gi
From: "Edgar E. Iglesias"
Add DMA memory-region property to externally control what
address-space this DMA operates on.
Reviewed-by: Alistair Francis
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/dma/xilinx_axidma.c | 30 +++-
From: "Edgar E. Iglesias"
Some stream clients stream an endless stream of data while
other clients stream data in packets. Stream interfaces
usually have a way to signal the end of a packet or the
last beat of a transfer.
This adds an end-of-packet flag to the push interface.
From: "Edgar E. Iglesias"
Since we're missing a maintainer, add myself.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 1f84e3ae2c..d3663d6c9a 100644
--- a/M
From: "Edgar E. Iglesias"
Remove unncessary cast, buf is already uint8_t *.
No functional change.
Reviewed-by: Alistair Francis
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: "Edgar E. Iglesias"
Split the shared stream_class_init function to assign
stream->push with better type-safety.
Reviewed-by: Alistair Francis
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 18 --
1 fil
From: "Edgar E. Iglesias"
Add support for stream fragments.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/dma/xilinx_axidma.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axid
From: "Edgar E. Iglesias"
Auto-clear PHY CR Autoneg bits. This makes this model
work with recent Linux kernels.
Reviewed-by: Francisco Iglesias
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --gi
From: "Edgar E. Iglesias"
Hi,
When modeling pipelines of processing nodes that communicate
through streaming interfaces (e.g AXI-Stream), some of these
nodes send packets while others may just stream unpacketized data.
The purpose of this series is to add an end-of-packet flag, e.
On Thu, Apr 30, 2020 at 06:24:36PM +0200, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Add support for fragmented packets from the DMA.
In v2 I'll add a check in the tx-path for packets larger than c_txmem...
Cheers,
Edgar
>
> Signed-off-by: Edgar E.
From: "Edgar E. Iglesias"
Calling access_el3_aa32ns() works for AArch32 only cores
but it does not handle 32-bit EL2 on top of 64-bit EL3
for mixed 32/64-bit cores.
Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
and only use the latter.
Fixes: 68e9c2fe65 ("target-ar
From: "Edgar E. Iglesias"
Hi,
Laurent reported hitting the assert in access_el3_aa32ns()
when accessing 32-bit versions of some of the virtualization
regs when EL3 is 64-bit.
I think we got this wrong back then and it seems to me like
we should merge access_
On Mon, May 04, 2020 at 04:21:25PM +0200, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> Calling access_el3_aa32ns() works for AArch32 only cores
> but it does not handle 32-bit EL2 on top of 64-bit EL3
> for mixed 32/64-bit cores.
>
>
On Mon, May 04, 2020 at 07:36:08PM +0530, Sai Pavan Boddu wrote:
> From: Tong Ho
>
> Two defects are fixed:
>
> 1/ Detection of multicast frames
> 2/ Treating drop of mis-addressed frames as non-error
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Tong Ho
On Mon, May 04, 2020 at 07:36:07PM +0530, Sai Pavan Boddu wrote:
> TX_LAST bit should not be set by hardware, its set by guest to inform
> the last bd of the frame.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Sai Pavan Boddu
> Signed-off-by: Edgar E. Iglesias
On Mon, May 04, 2020 at 07:36:06PM +0530, Sai Pavan Boddu wrote:
> Mask all interrupt on reset.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/net/cadence_gem.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/hw/ne
On Mon, May 04, 2020 at 07:36:05PM +0530, Sai Pavan Boddu wrote:
> Advertise support of clear-on-read for ISR registers.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/net/cadence_gem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(
On Mon, May 04, 2020 at 07:36:04PM +0530, Sai Pavan Boddu wrote:
> Jumbo frames of size 10240 bytes is added.
Hi Sai,
I think we should make this a property since it's a design
configuration option (10240 being the default).
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/net/cadence_gem.c | 5
place...
Anyway, the logic looks good to me:
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/net/cadence_gem.c | 31 ++-
> 1 file changed, 22 insertions(+), 9 deletions(-)
>
> diff --git a/hw/net/cadence_gem.c b/h
1_STATUS + i] = 0x;
> +s->regs_ro[GEM_INT_Q1_ENABLE + i] = 0xE319;
> +s->regs_ro[GEM_INT_Q1_DISABLE + i] = 0xE319;
Shouldn't these be 0xf319?
Perhaps I'm looking at old specs but mine says bits upper bits [31:12]
are reserved and re
On Mon, May 04, 2020 at 07:36:01PM +0530, Sai Pavan Boddu wrote:
> Set irq's specific to a queue, present implementation is setting q1 irq
> based on q0 status.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/net/
On Mon, May 04, 2020 at 07:35:59PM +0530, Sai Pavan Boddu wrote:
> Enabling debug breaks the build, Fix them and make debug statements
> always compilable. Fix few statements to use sized integer casting.
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/net/cadence_gem.c | 28
le easier to read, e.g:
s->rx_desc_addr[q] = gem_get_rx_queue_base_addr(s, q);
vs
s->rx_desc_addr[q] = gem_get_queue_base_addr(s, false, q);
Anyway, this looks good to me:
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/net/cadence_gem.c | 29 +++
From: "Edgar E. Iglesias"
Calling access_el3_aa32ns() works for AArch32 only cores
but it does not handle 32-bit EL2 on top of 64-bit EL3
for mixed 32/64-bit cores.
Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns()
and only use the latter.
Fixes: 68e9c2fe65 ("target-ar
On Mon, May 04, 2020 at 12:01:07PM +0100, Peter Maydell wrote:
> On Tue, 28 Apr 2020 at 17:03, Edgar E. Iglesias
> wrote:
> >
> > From: "Edgar E. Iglesias"
> >
> > Calling access_el3_aa32ns() works for AArch32 only cores
> > but it does not handle 32
From: "Edgar E. Iglesias"
Hi,
Laurent reported hitting the assert in access_el3_aa32ns()
when accessing 32-bit versions of some of the virtualization
regs when EL3 is 64-bit.
I think we got this wrong back then and it seems to me like
we should remove direct usage of access_
From: "Edgar E. Iglesias"
Since we're missing a maintainer, add myself.
Signed-off-by: Edgar E. Iglesias
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8cbc1fac2b..9f504e32df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
From: "Edgar E. Iglesias"
Add support for stream fragments.
Signed-off-by: Edgar E. Iglesias
---
hw/dma/xilinx_axidma.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
index 101d32a965..87be9ca
From: "Edgar E. Iglesias"
Stream descriptor by descriptor from memory instead of
buffering entire packets before pushing. This enables
non-packet streaming clients to work and also lifts the
limitation that our internal DMA buffer needs to be able
to hold entire packets.
Signed-off-b
From: "Edgar E. Iglesias"
Add support for fragmented packets from the DMA.
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 31 ---
1 file changed, 24 insertions(+), 7 deletions(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axien
From: "Edgar E. Iglesias"
Auto-clear PHY CR Autoneg bits. This makes this model
work with recent Linux kernels.
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/net/xilinx_axienet.
From: "Edgar E. Iglesias"
Remove unncessary cast, buf is already uint8_t *.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index
From: "Edgar E. Iglesias"
Add DMA memory-region property to externally control what
address-space this DMA operates on.
Signed-off-by: Edgar E. Iglesias
---
hw/dma/xilinx_axidma.c | 30 +++---
1 file changed, 23 insertions(+), 7 deletions(-)
diff --gi
From: "Edgar E. Iglesias"
Some stream clients stream an endless stream of data while
other clients stream data in packets. Stream interfaces
usually have a way to signal the end of a packet or the
last beat of a transfer.
This adds an end-of-packet flag to the push interface.
From: "Edgar E. Iglesias"
Split the shared stream_class_init function to assign
stream->push with better type-safety.
Signed-off-by: Edgar E. Iglesias
---
hw/net/xilinx_axienet.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/net/xilin
From: "Edgar E. Iglesias"
Hi,
When modeling pipelines of processing nodes that communicate
through streaming interfaces (e.g AXI-Stream), some of these
nodes send packets while others may just stream unpacketized data.
The purpose of this series is to add an end-of-packet flag, e.
On Tue, Apr 28, 2020 at 05:35:46PM +, Vikram Garhwal wrote:
> Hi Edgar,
> Thanks for review.
>
> > -Original Message-
> > From: Edgar E. Iglesias
> > Sent: Tuesday, April 28, 2020 9:28 AM
> > To: Vikram Garhwal
> > Cc: qemu-devel@nongnu.org; Ja
From: "Edgar E. Iglesias"
Add the pvr-user2 property to control the user-defined
PVR1 User2 register.
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c | 2 ++
2 files changed, 3
From: "Edgar E. Iglesias"
Add the pvr-user1 property to control the user-defined
PVR0 User1 field.
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c | 4 +++-
2 files changed, 4 insert
From: "Edgar E. Iglesias"
Add the unaligned-exceptions property to control if the core
traps unaligned memory accesses.
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c
From: "Edgar E. Iglesias"
Add the div-zero-exception property to control if the core
traps divizions by zero.
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c | 4 ++
From: "Edgar E. Iglesias"
Add the ill-opcode-exception property to control if illegal
instructions will raise exceptions.
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c
From: "Edgar E. Iglesias"
Add the opcode-0x0-illegal CPU property to control if the core
should trap opcode zero as illegal.
Reviewed-by: Alistair Francis
Reviewed-by: Luc Michel
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 1 +
target/microblaze/cpu.c
From: "Edgar E. Iglesias"
The following changes since commit 648db19685b7030aa558a4ddbd3a8e53d8c9a062:
Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2020-04-29' into
staging (2020-04-29 15:07:33 +0100)
are available in the Git repository at:
g...@github.co
On Wed, Apr 22, 2020 at 05:56:09PM -0700, Vikram Garhwal wrote:
> Add myself as Xilinx CAN maintainer.
Hi Vikram,
I think it would be good to add Francisco Iglesias
as co-maintainer since he's been involved with this too.
Anyway:
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-b
@@
> #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
> #define XLNX_ZYNQMP_NUM_GEMS 4
> #define XLNX_ZYNQMP_NUM_UARTS 2
> +#define XLNX_ZYNQMP_NUM_CAN 2
> #define XLNX_ZYNQMP_NUM_SDHCI 2
> #define XLNX_ZYNQMP_NUM_SPIS 2
> #define XLNX_ZYNQMP_NUM_GDMA_CH 8
> @@ -92,6 +94,7 @@
On Wed, Apr 22, 2020 at 05:56:06PM -0700, Vikram Garhwal wrote:
> XlnxCAN is developed based on SocketCAN, QEMU CAN bus implementation.
> Bus connection and socketCAN connection for each CAN module can be set
> through command lines.
+ Damien (there's a reset question for you inline)
+ Francisco
From: "Edgar E. Iglesias"
Calling access_el3_aa32ns() works for AArch32 only cores
but it does not handle 32-bit EL2 on top of 64-bit EL3
for mixed 32/64-bit cores.
Fold access_el3_aa32ns() into access_el3_aa32ns_aa64any()
and replace all direct uses of the aa32 on
From: "Edgar E. Iglesias"
Hi,
Laurent reported hitting the assert in access_el3_aa32ns()
when accessing 32-bit versions of some of the virtualization
regs when EL3 is 64-bit.
I think we got this wrong back then and it seems to me like
we should remove direct usage of access_
From: "Edgar E. Iglesias"
Add support for the RTC.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 0afee48672..7e749e1926 100644
--
From: "Edgar E. Iglesias"
Move misplaced comment.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index c73b2fe755..cc696e44c0 100644
--- a/hw/arm/xlnx-versal.
From: "Edgar E. Iglesias"
Add support for SD.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 46 +++
1 file changed, 46 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index d7be1ad494..0afee48
From: "Edgar E. Iglesias"
Embedd the ADMAs into the SoC type.
Suggested-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 14 +++---
include/hw/arm/xlnx-versal.h | 3 ++-
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/h
From: "Edgar E. Iglesias"
Add support for SD.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal.c | 31 +++
include/hw/arm/xlnx-versal.h | 12
2 files changed, 43 insertions(+)
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xln
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