On Mon, Jul 01, 2019 at 02:33:11PM +0100, Alex Bennée wrote:
>
> Edgar E. Iglesias writes:
>
> > On Fri, Jun 28, 2019 at 02:16:41PM +0200, Richard Henderson wrote:
> >> On 6/28/19 1:39 PM, Luc Michel wrote:
> >> > Add a TCG trace at the begining of a translat
On Fri, Jun 28, 2019 at 02:16:41PM +0200, Richard Henderson wrote:
> On 6/28/19 1:39 PM, Luc Michel wrote:
> > Add a TCG trace at the begining of a translation block recording the
> > first and last (past-the-end) PC values.
> >
> > Signed-off-by: Luc Michel
> > ---
> > This can be used to trace
+ Francisco
On Thu, 28 Mar. 2019, 16:26 Peter Maydell, wrote:
> In the stripe8() function we use a variable length array; however
> we know that the maximum length required is MAX_NUM_BUSSES. Use
> a fixed-length array and an assert instead.
>
> Signed-off-by: Peter Maydell
> ---
>
On Tue, Mar 12, 2019 at 06:36:05PM +0100, Markus Armbruster wrote:
Hi,
Here are some steps. If you have a hard time finding any particular file
let me know and I can send them to you.
> = hw/arm/xilinx_zynq.c =
> "Edgar E. Iglesias" (maintainer:Xilinx Zynq)
>
Hi Damien and others,
A few questions from my side.
We sometimes see that wires from generic GPIO blocks get connected to reset
inputs.
This happens both to off-chip perihperals but we also see it on-chip.
To avoid having GPIO modules know that some of their outputs are being used as
reset
On Sun, Mar 03, 2019 at 10:59:30AM +, Peter Maydell wrote:
> On Sat, 2 Mar 2019 at 19:41, Philippe Mathieu-Daudé wrote:
> >
> > Hi Damien,
> >
> > On 3/1/19 5:52 PM, Peter Maydell wrote:
> > > On Fri, 1 Mar 2019 at 15:34, Damien Hedde
> > > wrote:
> > >> On 3/1/19 12:43 PM, Peter Maydell
for those made by the CPU via its MMU. For
microblaze this makes no difference because none of the
target CPU code needs to make loads or stores by physical
address.
Signed-off-by: Peter Maydell
[EI: Add space in qemu_log()]
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.c | 2
From: "Edgar E. Iglesias"
Create an unimplemented GPIO area instead of leaving it unassigned.
Reviewed-by: Luc Michel
Signed-off-by: Edgar E. Iglesias
---
hw/microblaze/petalogix_s3adsp1800_mmu.c | 4
1 file changed, 4 insertions(+)
diff --git a/hw/microblaze/petalogix_s3adsp
From: "Edgar E. Iglesias"
Add MicroBlaze CPU properties to enable exceptions on failed
bus accesses.
Reviewed-by: Luc Michel
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.c | 12 +++-
target/microblaze/cpu.h | 2 ++
2 files c
From: "Edgar E. Iglesias"
The following changes since commit e56b86bc7735dd076939fa33a76e1ee9d5907e47:
Merge remote-tracking branch 'remotes/marcel/tags/rdma-pull-request' into
staging (2019-01-21 19:19:47 +)
are available in the Git repository at:
g...@github.com:edgarig
Michel
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 48 +---
> 1 file changed, 5 insertions(+), 43 deletions(-)
>
> diff --git a/gdbstub.c b/gdbstub.c
> index bfc7afb5096..5d6cbea9d35 100644
> --- a/gdbstub.c
> +++ b/gdbstub.c
er need more, or need
> more bits in cflags for other purposes, we could make
> tb_hash_func() take more data (and expand qemu_xxhash7()
> to qemu_xxhash8()).
>
> Signed-off-by: Peter Maydell
> Reviewed-by: Richard Henderson
Reviewed-by: Edgar E. Iglesias
> ---
> v
o parent the CPUs into it".
>
> The restriction on how many clusters can exist in the system
> is imposed by TCG code which will be added in a subsequent commit,
> but the check to enforce it in cluster.c fits better in this one.
>
> Signed-off-by: Peter Maydell
Reviewed-by:
ing clusters and putting CPUs in them.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> This is a preparatory patch that is necessary for the series
> "[PATCH v3 0/4] tcg: support heterogenous CPU clusters"
> (20190121152218.9592-1-peter.mayd...@linaro.
ly after all the child objects are added, so move
> the realize of rpu_cluster. (The apu_cluster is already
> realized after child population.)
>
> Signed-off-by: Peter Maydell
> Reviewed-by: Richard Henderson
> Reviewed-by: Luc Michel
> Reviewed-by: Alistair Francis
From: "Edgar E. Iglesias"
This adds the necessary properties to MicroBlaze cores to enable exceptions
on failed bus accesses. There's no board that acutally uses this yet.
This also adds an unimplemented device to the s3adsp1800 board since I used
that board to test this feature. The
From: "Edgar E. Iglesias"
Add MicroBlaze CPU properties to enable exceptions on failed
bus accesses.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.c | 12 +++-
target/microblaze/cpu.h | 2 ++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --gi
On Mon, Dec 10, 2018 at 03:28:16PM +, Alex Bennée wrote:
> Hi,
>
> This is very much a work in progress but I'm posting it in the hope of
> getting some feedback from the architecture maintainers.
>
> When I originally enabled tcg tests I only enabled linux-user tests for
> architectures
On Mon, Dec 10, 2018 at 03:28:27PM +, Alex Bennée wrote:
> Evidently upstream gcc doesn't like this opcode.
>
> Signed-off-by: Alex Bennée
Hi Alex, this is probably an example of missmatching CRISv10 vs CRISv32
versions in toolchain usage.
Cheers,
Edgar
> ---
>
On Mon, Dec 10, 2018 at 03:28:16PM +, Alex Bennée wrote:
> Hi,
>
> This is very much a work in progress but I'm posting it in the hope of
> getting some feedback from the architecture maintainers.
>
> When I originally enabled tcg tests I only enabled linux-user tests for
> architectures
On Mon, Dec 10, 2018 at 06:32:49PM +, Peter Maydell wrote:
> On Mon, 10 Dec 2018 at 18:31, Peter Maydell wrote:
> >
> > On Mon, 10 Dec 2018 at 17:57, Peter Maydell
> > wrote:
> > >
> > > Switch the microblaze target from the old unassigned_access hook
> > > to the transaction_failed hook.
>
for those made by the CPU via its MMU. For
> > > microblaze this makes no difference because none of the
> > > target CPU code needs to make loads or stores by physical
> > > address.
Thanks Peter, this looks good.
Reviewed-by: Edgar E. Iglesias
Tested-by: Edgar E.
From: "Edgar E. Iglesias"
Plug a couple of "board creation time" memory leaks.
Reported-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx
From: "Edgar E. Iglesias"
This series fixes the memory leaks in versal board creation
reported by Peter Maydell.
Best regards,
Edgar
Edgar E. Iglesias (1):
hw/arm: versal: Plug memory leaks
hw/arm/xlnx-versal-virt.c | 2 ++
1 file changed, 2 insertions(+)
--
2.17.1
> > From: "Edgar E. Iglesias"
> >
> > Add a virtual Xilinx Versal board.
> >
> > This board is based on the Xilinx Versal SoC. The exact
> > details of what peripherals are attached to this board
> > will remain in control of QEMU. QEMU wil
On Fri, Nov 23, 2018 at 10:17:20AM +0100, Luc Michel wrote:
> Change the thread info related packets handling to support multiprocess
> extension.
>
> Add the CPUs class name in the extra info to help differentiate
> them in multiprocess mode.
Reviewed-by: Edgar E. Iglesias
From: "Edgar E. Iglesias"
Correct the nr of IRQs to 192.
Signed-off-by: Edgar E. Iglesias
---
include/hw/arm/xlnx-versal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index 76fb9de391..ec7c859
From: "Edgar E. Iglesias"
Use IRQs 111 - 118 for virtio-mmio. The interrupts we're currently
using 160+ are not available in the Versal GIC.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c| 4 ++--
include/hw/arm/xlnx-versal.h | 6 +++---
2 files changed, 5 insert
From: "Edgar E. Iglesias"
Reduce number of virtio-mmio instances. This is in preparation
for correcting the interrupt setup for Versal.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/xlnx-ver
From: "Edgar E. Iglesias"
The Versal GIC has 192 IRQs not 256 as we previously had setup.
This series fixes the setup and moves the virtio-mmio nodes
to use other reserved interrupts.
Since we don't have 32 reserved lines, we also reduce the number of
virtio-mmio regions to 8 (we do
From: "Edgar E. Iglesias"
Remove bogus virtio-mmio creation. This was an accidental
left-over an experiment.
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-versal-virt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index
On Tue, Nov 27, 2018 at 02:05:51PM +0100, Greg Kurz wrote:
> Because it is a recommended coding practice (see HACKING).
>
> Signed-off-by: Greg Kurz
Reviewed-by: Edgar E. Iglesias
> ---
> hw/ppc/ppc440_bamboo.c |5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(
On Tue, Nov 27, 2018 at 02:06:12PM +0100, Greg Kurz wrote:
> Because it is a recommended coding practice (see HACKING).
>
> Signed-off-by: Greg Kurz
Reviewed-by: Edgar E. Iglesias
> ---
> hw/ppc/virtex_ml507.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
&g
On Fri, Nov 23, 2018 at 05:09:35PM +, Peter Maydell wrote:
> On Fri, 23 Nov 2018 at 16:59, Edgar E. Iglesias
> wrote:
> > Not sure if it's too late to even get the removal of the assert into this
> > release? Peter?
>
> If you're happy that removing the assert i
On Fri, Nov 23, 2018 at 06:02:25PM +0100, Edgar E. Iglesias wrote:
> On Fri, Nov 23, 2018 at 05:59:45PM +0100, Edgar E. Iglesias wrote:
> > On Fri, Nov 23, 2018 at 05:46:17PM +0100, Philippe Mathieu-Daudé wrote:
> > > Hi Edgar,
> >
> > Hi Philippe,
> >
>
On Fri, Nov 23, 2018 at 05:59:45PM +0100, Edgar E. Iglesias wrote:
> On Fri, Nov 23, 2018 at 05:46:17PM +0100, Philippe Mathieu-Daudé wrote:
> > Hi Edgar,
>
> Hi Philippe,
>
> >
> > On 23/11/18 14:54, Edgar E. Iglesias wrote:
> > > From: "Edgar E
On Fri, Nov 23, 2018 at 05:46:17PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Edgar,
Hi Philippe,
>
> On 23/11/18 14:54, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > Don't assert on RX descriptor settings when the receiver is
> >
On Fri, Nov 23, 2018 at 02:20:17PM +0100, Edgar E. Iglesias wrote:
> On Fri, Nov 23, 2018 at 02:59:32PM +0500, mbilal wrote:
> > Hi,
> >
> > Thanks for reply.
> >
> > According to your suggestion I've tested with 3.1 rc2 release and problem is
> > still ex
On Fri, Nov 23, 2018 at 11:30:35PM +0800, Mao Zhongyi wrote:
> Use DeviceClass rather than SysBusDeviceClass in
> etraxfs_timer_class_init().
>
> Cc: edgar.igles...@gmail.com
>
> Signed-off-by: Mao Zhongyi
> Signed-off-by: Zhang Shengju
Reviewed-by: Edgar E. Iglesias
From: "Edgar E. Iglesias"
Don't assert on RX descriptor settings when the receiver is
disabled. This fixes an issue with incoming packets on an
unused GEM.
Reported-by: mbilal
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 1 -
1 file changed, 1 deletion(-)
diff --gi
From: "Edgar E. Iglesias"
This fixes an issue with the GEM models reported by Bilal.
If a GEM's receiver is disabled, we shouldn't be asserting on
descriptor processing.
Cheers,
Edgar
Edgar E. Iglesias (1):
net: cadence_gem: Remove incorrect assert()
hw/net/cadence_gem.c | 1
On Fri, Nov 23, 2018 at 02:59:32PM +0500, mbilal wrote:
> Hi,
>
> Thanks for reply.
>
> According to your suggestion I've tested with 3.1 rc2 release and problem is
> still exist in this release also.
>
> Here is my reproducible scenario.
Thanks,
I've had a look and the assert looks bogus to
On Mon, Nov 19, 2018 at 11:12:45AM +0100, Luc Michel wrote:
>
>
> On 11/16/18 11:04 AM, Edgar E. Iglesias wrote:
> > On Thu, Nov 15, 2018 at 10:41:58AM +0100, Luc Michel wrote:
> >> Change the thread info related packets handling to support multiprocess
> >>
On Thu, Nov 15, 2018 at 10:41:51AM +0100, Luc Michel wrote:
Hi Luc,
I think I've either reviewed all of the patches or commented on all now.
Great work!
Thanks,
Edgar
> changes since v5:
> - patch 1Rebased on top of master
>
> - patch 2Cluster ID handling hardening to ensure
: Philippe Mathieu-Daudé
> Acked-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/gdbstub.c b/gdbstub.c
> index 89819a6a72..e0b844c040 100644
> --- a/gdbstub.c
> +++ b/g
iewed-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 20 +++-
> 1 file changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/gdbstub.c b/gdbstub.c
> index 0427d1c4f0..59eed3b878 100644
> --- a/gdbstub.c
> +++ b/gdbstub.c
> @
d-id it does not know about.
>
> Signed-off-by: Luc Michel
> Acked-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git a/gdbstub.c b/gdbstub.c
> index 59eed3b878..89819a6a72 100
On Thu, Nov 15, 2018 at 10:42:02AM +0100, Luc Michel wrote:
> Add support for the '!' extended mode packet. This is required for the
> multiprocess extension.
>
> Signed-off-by: Luc Michel
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 3 +++
> 1 file changed, 3 in
On Thu, Nov 15, 2018 at 10:42:01AM +0100, Luc Michel wrote:
> 'D' packets are used by GDB to detach from a process. In multiprocess
> mode, the PID to detach from is sent in the request.
>
> Signed-off-by: Luc Michel
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Ed
On Thu, Nov 15, 2018 at 10:42:03AM +0100, Luc Michel wrote:
> Add support for the vAttach packets. In multiprocess mode, GDB sends
> them to attach to additional processes.
>
> Signed-off-by: Luc Michel
Reviewed-by: Edgar E. Iglesias
> ---
&g
On Thu, Nov 15, 2018 at 10:42:00AM +0100, Luc Michel wrote:
> Add support for multiprocess extension in gdb_vm_state_change()
> function.
>
> Signed-off-by: Luc Michel
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 15
Luc Michel
> Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 47 +++
> 1 file changed, 27 insertions(+), 20 deletions(-)
>
> diff --git a/gdbstub.c b/gdbstub.c
> index 292dee8914..4cbc81ae5
On Thu, Nov 15, 2018 at 10:41:58AM +0100, Luc Michel wrote:
> Change the thread info related packets handling to support multiprocess
> extension.
>
> Add the CPUs class name in the extra info to help differentiate
> them in multiprocess mode.
>
> Signed-off-by: Luc Michel
> Reviewed-by:
ippe Mathieu-Daudé
> Reviewed-by: Alistair Francis
Reviewed-by: Edgar E. Iglesias
> ---
> gdbstub.c | 11 ---
> 1 file changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/gdbstub.c b/gdbstub.c
> index f1ec3481cb..d19b0137e8 100644
> --- a/gdbstub.c
> +++
@ -743,10 +773,41 @@ static CPUState *gdb_get_cpu(const GDBState *s,
> uint32_t pid, uint32_t tid)
> }
>
> return cpu;
> }
>
> +/* Return the cpu following @cpu, while ignoring
> + * unattached processes.
> + */
> +static CPUState *gdb_ne
gt; +
> +if (cpu == NULL) {
> +return NULL;
> +}
Not sure about this. If tid is zero, you fix up the wildcard by setting tid to
one.
Shouldn't you also retry find_cpu(tid) in that case?
Otherwise, tid doesn't seem to be used after the wildcard fixup.
Other than that, I think th
On Wed, Nov 14, 2018 at 11:14:31AM +0100, Luc Michel wrote:
> Hi Edgar,
>
> On 11/13/18 11:52 AM, Edgar E. Iglesias wrote:
> > On Sat, Nov 10, 2018 at 09:11:33AM +0100, Luc Michel wrote:
> >> Add a structure GDBProcess that represent processes from the GDB
>
On Wed, Nov 14, 2018 at 09:43:27AM +0100, Luc Michel wrote:
> Hi Edgar,
>
> On 11/13/18 12:06 PM, Edgar E. Iglesias wrote:
> > On Sat, Nov 10, 2018 at 09:11:34AM +0100, Luc Michel wrote:
> >> The gdb_get_cpu_pid() function does the PID lookup for the given CPU. I
entries (if you find a cluster but the
no valid entry in s->processes). Then we could perhaps eliminate the
scan of all objects at startup and also support CPU/Cluster hotplug.
Anyway, this looks good to me!
Reviewed-by: Edgar E. Iglesias
Cheers,
Edgar
> ---
> gdbstub.c | 60
cal but since both pid and cluster_id are uint32_t
you may end up with 0 here.
You may want to limit cluster_id's to something like the range 0 - INT32_MAX.
> +process->attached = false;
> +return 0;
> +}
> +
> +return object_child_foreach(child, find_cp
r Francis
> Reviewed-by: Philippe Mathieu-Daudé
> Tested-by: Philippe Mathieu-Daudé
Reviewed-by: Edgar E. Iglesias
> ---
> include/hw/cpu/cluster.h | 38 ++
> hw/cpu/cluster.c | 59
> MAINTAINERS
UARMState *env,
> uint32_t tgtmode, uint32_t regno)
> case 13:
> return env->banked_r13[bank_number(tgtmode)];
> case 14:
> -return env->banked_r14[bank_number(tgtmode)];
> +return env->banked_r14[r14_bank_number(tgtmode)];
> case 8 ... 12:
> switch (tgtmode) {
> case ARM_CPU_MODE_USR:
>
>
> (it's one of the "no behavioural change" bits).
>
Reviewed-by: Edgar E. Iglesias
esses banked_r14[] with tgtmode == ARM_CPU_MODE_HYP,
>so no behavioural change
>
> Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
> ---
> target/arm/internals.h | 16
> target/arm/helper.c| 29 +++--
> targ
On Fri, Nov 09, 2018 at 05:35:53PM +, Peter Maydell wrote:
> The Cortex-A15 and Cortex-A7 both have EL2; now we've implemented
> it properly we can enable the feature bit.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
> ---
> target/arm/cpu.c | 2 ++
e the comment; there is no extra code
> needed to handle these operations in do_ats_write(), because
> arm_s1_regime_using_lpae_format() returns true for ARMMMUIdx_S1E2,
> which forces 64-bit PAR format.
>
> Signed-off-by: Peter Maydell
Oops, yes:
Reviewed-by: Edgar E. Iglesias
plement virtualization, add the missing
> code that sets these bits based on the reported ARMMMUFaultInfo.
>
> (These bits are named PTW and S in ARMv8, so we follow that
> convention in the new comments in this patch.)
>
> Signed-off-by: Peter Maydell
Reviewed-by: Edgar E.
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias
---
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/xlnx-versal.c| 323
include/hw/arm/xlnx-versal.h| 122 +++
4 files
-versal-virt.c b/hw/arm/xlnx-versal-virt.c
new file mode 100644
index 00..1e31a3f442
--- /dev/null
+++ b/hw/arm/xlnx-versal-virt.c
@@ -0,0 +1,494 @@
+/*
+ * Xilinx Versal Virtual board.
+ *
+ * Copyright (c) 2018 Xilinx Inc.
+ * Written by Edgar E. Iglesias
+ *
+ * This program is free
it's not needed)
* Embedd AddressSpace dma object in GEM
* Remove debug left-overs in arm-powerctl
* Enable PMU in Cortex-A72
* Rename cortex_a57_a53_cp_reginfo -> cortex_a72_a57_a53_cp_reginfo
Edgar E. Iglesias (2):
hw/arm: versal: Add a model of Xilinx Versal SoC
hw/arm: versal: Add a vir
On Tue, Oct 30, 2018 at 01:31:44PM +, Peter Maydell wrote:
> On 22 October 2018 at 18:35, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Add a virtual Xilinx Versal board.
> >
> > This board is based on the Xilinx Versal
From: "Edgar E. Iglesias"
Announce 64bit addressing support.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 16a8455128..
From: "Edgar E. Iglesias"
This patch series adds initial support for Xilinx's Versal SoC.
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardwa
From: "Edgar E. Iglesias"
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias
---
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/xlnx-versal.c| 323
include/hw/arm/xln
From: "Edgar E. Iglesias"
Add a virtual Xilinx Versal board.
This board is based on the Xilinx Versal SoC. The exact
details of what peripherals are attached to this board
will remain in control of QEMU. QEMU will generate an
FDT on the fly for Linux and other software to aut
From: "Edgar E. Iglesias"
Announce the availability of the various priority queues.
This fixes an issue where guest kernels would miss to
configure secondary queues due to inproper feature bits.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 8 +++-
1 file
On Sun, Oct 21, 2018 at 10:25:28PM +0100, Peter Maydell wrote:
> On 21 October 2018 at 20:24, Edgar E. Iglesias
> wrote:
> > On Fri, Oct 19, 2018 at 03:18:24PM +0100, Peter Maydell wrote:
> >> On 17 October 2018 at 22:39, Edgar E. Iglesias
> >> wrote:
&
On Fri, Oct 19, 2018 at 03:18:24PM +0100, Peter Maydell wrote:
> On 17 October 2018 at 22:39, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Add a model of Xilinx Versal SoC.
> >
> > Signed-off-by: Edgar E. Iglesias
> >
From: "Edgar E. Iglesias"
Add a virtual Xilinx Versal board.
This board is based on the Xilinx Versal SoC. The exact
details of what peripherals are attached to this board
will remain in control of QEMU. QEMU will generate an
FDT on the fly for Linux and other software to aut
From: "Edgar E. Iglesias"
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias
---
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/xlnx-versal.c| 324
include/hw/arm/xln
From: "Edgar E. Iglesias"
Announce 64bit addressing support.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 16a8455128..
From: "Edgar E. Iglesias"
Announce the availability of the various priority queues.
This fixes an issue where guest kernels would miss to
configure secondary queues due to inproper feature bits.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 8 +++-
1 file
From: "Edgar E. Iglesias"
This patch series adds initial support for Xilinx's Versal SoC.
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardwa
On Tue, Oct 16, 2018 at 05:15:36PM +0100, Peter Maydell wrote:
> On 11 October 2018 at 03:19, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Announce the availability of the various priority queues.
> > This fixes an issue where g
From: "Edgar E. Iglesias"
Add a virtual Xilinx Versal board.
This board is based on the Xilinx Versal SoC. The exact
details of what peripherals are attached to this board
will remain in control of QEMU. QEMU will generate an
FDT on the fly for Linux and other software to aut
From: "Edgar E. Iglesias"
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias
---
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/xlnx-versal.c| 324
include/hw/arm/xln
From: "Edgar E. Iglesias"
Implement support for 64bit descriptor addresses.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 47
1 file changed, 39 insertions(+), 8 deletions(-)
diff --gi
From: "Edgar E. Iglesias"
Add support for selecting the Memory Region that the GEM
will do DMA to.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 59 ++--
include/hw/net/cadence_gem.h | 2 ++
2 files changed, 39 insertions(+), 22
From: "Edgar E. Iglesias"
Add the ARM Cortex-A72.
Signed-off-by: Edgar E. Iglesias
---
target/arm/cpu64.c | 66 +++---
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index db71504cb5..
From: "Edgar E. Iglesias"
This patch series adds initial support for Xilinx's Versal SoC.
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardwa
From: "Edgar E. Iglesias"
When QEMU provides the equivalent of the EL3 firmware, we
need to enable HVCs in scr_el3 when turning on CPUs that
target EL2.
Reviewed-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
target/arm/arm-powerctl.c | 10 ++
1 file changed, 10
From: "Edgar E. Iglesias"
Announce the availability of the various priority queues.
This fixes an issue where guest kernels would miss to
configure secondary queues due to inproper feature bits.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence
From: "Edgar E. Iglesias"
Announce 64bit addressing support.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 550225c15b..
From: "Edgar E. Iglesias"
Add macro with max number of DMA descriptor words.
No functional change.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 4 ++--
include/hw/net/cadence_gem.h | 5
From: "Edgar E. Iglesias"
Add support for extended descriptors with optional 64bit
addressing and timestamping. QEMU will not yet provide
timestamps (always leaving the valid timestamp bit as zero).
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cad
From: "Edgar E. Iglesias"
Disable the Timestamping Unit feature bit since QEMU does not
yet support it. This allows guest SW to correctly probe for
its existance.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 2 +-
1 file changed, 1 inser
From: "Edgar E. Iglesias"
Use uint32_t instead of unsigned to describe 32bit descriptor words.
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 42 ++--
incl
On Tue, Oct 09, 2018 at 03:40:13PM +0200, Laurent Desnogues wrote:
> Hello,
>
> On Tue, Oct 9, 2018 at 3:19 PM Edgar E. Iglesias
> wrote:
> >
> > Another A72 related thing I wanted to check with you. A month or two ago I
> > was
> > looking at an issue w
On Tue, Oct 09, 2018 at 10:30:01AM +0100, Peter Maydell wrote:
> On 8 October 2018 at 22:34, Edgar E. Iglesias
> wrote:
> > On Mon, Oct 08, 2018 at 02:10:29PM +0100, Peter Maydell wrote:
> >> On 3 October 2018 at 16:07, Edgar E. Iglesias
> >> wrote:
&
On Mon, Oct 08, 2018 at 03:08:14PM +0100, Peter Maydell wrote:
> On 3 October 2018 at 16:07, Edgar E. Iglesias
> wrote:
> > In QEMU we'd like to have a virtual developer board with the Versal SoC
> > and a selected set of peripherals under the control of QEMU.
> > We'd
On Mon, Oct 08, 2018 at 02:19:09PM +0100, Peter Maydell wrote:
> On 3 October 2018 at 16:07, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Add a model of Xilinx Versal SoC.
> >
> > Signed-off-by: Edgar E. Iglesias
> >
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