On Mon, Oct 08, 2018 at 02:10:29PM +0100, Peter Maydell wrote:
> On 3 October 2018 at 16:07, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Add the ARM Cortex-A72.
> >
> > Signed-off-by: Edgar E.
On Mon, Oct 08, 2018 at 01:30:20PM +0100, Peter Maydell wrote:
> On 3 October 2018 at 16:07, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Add support for selecting the Memory Region that the GEM
> > will do DMA to.
> >
> &g
On Mon, Oct 08, 2018 at 01:41:36PM +0100, Peter Maydell wrote:
> On 3 October 2018 at 16:07, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > When QEMU provides the equivalent of the EL3 firmware, we
> > need to enable HVCs in scr_el3
On Mon, Oct 08, 2018 at 01:24:51PM +0100, Peter Maydell wrote:
> On 3 October 2018 at 16:07, Edgar E. Iglesias
> wrote:
> > From: "Edgar E. Iglesias"
> >
> > Add support for selecting the Memory Region that the GEM
> > will do DMA to.
From: "Edgar E. Iglesias"
Add the ARM Cortex-A72.
Signed-off-by: Edgar E. Iglesias
---
target/arm/cpu64.c | 59 ++
1 file changed, 59 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 800bff7..02e5
From: "Edgar E. Iglesias"
Announce 64bit addressing support.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index f93cd8e..fc81fb5 100644
--- a/hw/net/cad
From: "Edgar E. Iglesias"
Implement support for 64bit descriptor addresses.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 47 +++
1 file changed, 39 insertions(+), 8 deletions(-)
diff --git a/hw/net/cadence_gem.
From: "Edgar E. Iglesias"
Add support for selecting the Memory Region that the GEM
will do DMA to.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 63
include/hw/net/cadence_gem.h | 2 ++
2 files changed, 43 inserti
From: "Edgar E. Iglesias"
Add a virtual Xilinx Versal board.
This board is based on the Xilinx Versal SoC. The exact
details of what peripherals are attached to this board
will remain in control of QEMU. QEMU will generate an
FDT on the fly for Linux and other software to aut
From: "Edgar E. Iglesias"
Add support for extended descriptors with optional 64bit
addressing and timestamping. QEMU will not yet provide
timestamps (always leaving the valid timestamp bit as zero).
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c
From: "Edgar E. Iglesias"
Add a model of Xilinx Versal SoC.
Signed-off-by: Edgar E. Iglesias
---
default-configs/aarch64-softmmu.mak | 1 +
hw/arm/Makefile.objs| 1 +
hw/arm/xlnx-versal.c| 339
include/h
From: "Edgar E. Iglesias"
When QEMU provides the equivalent of the EL3 firmware, we
need to enable HVCs in scr_el3 when turning on CPUs that
target EL2.
Signed-off-by: Edgar E. Iglesias
---
target/arm/arm-powerctl.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/
From: "Edgar E. Iglesias"
Add macro with max number of DMA descriptor words.
No functional change.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 4 ++--
include/hw/net/cadence_gem.h | 5 -
2 files changed, 6 insertions(+), 3 deletions(-)
diff --gi
From: "Edgar E. Iglesias"
Disable the Timestamping Unit feature bit since QEMU does not
yet support it. This allows guest SW to correctly probe for
its existance.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: "Edgar E. Iglesias"
Use uint32_t instead of unsigned to describe 32bit descriptor words.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 42 +-
include/hw/net/cadence_gem.h | 2 +-
2 files changed, 22 inserti
From: "Edgar E. Iglesias"
Announce the availability of the various priority queues.
This fixes an issue where guest kernels would miss to
configure secondary queues due to inproper feature bits.
Signed-off-by: Edgar E. Iglesias
---
hw/net/cadence_gem.c | 6 +-
1 file changed, 5
From: "Edgar E. Iglesias"
This patch series adds initial support for Xilinx's Versal SoC.
Xilinx is introducing Versal, an adaptive compute acceleration platform
(ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
Processing Engines, Adaptable Hardwa
nd CPSR.J
> * new patch: boot kernels in Hyp mode if possible
>
> (I still have the same "guest EL0 segv" issue as for v1
> if I actually enable the EL2 feature on Cortex-A15.)
Reviewed-by: Edgar E. Iglesias
>
> thanks
> -- PMM
>
> Peter Maydell (6):
>
had bad race conditions that
> resulted in crashes if you tried to use it heavily.
>
> This API was only ever used in one device in the source
> tree, the Xilinx SPIPS. These three patches remove the
> now-unneeded code from the Xilinx device and then the
> core memory subsystem code.
On Tue, Aug 14, 2018 at 01:42:44PM +0100, Peter Maydell wrote:
> Now we have virtualization support in the GICv2 emulation,
> I thought I'd have a look at how much we were still missing
> for being able to enable EL2 support for AArch32.
> This set of patches fixes some minor missing pieces:
> *
he behaviour of the existing
> "SUBS PC, LR, #" instruction.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/translate.c | 31 +--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/t
On Tue, Aug 14, 2018 at 01:42:54PM +0100, Peter Maydell wrote:
> Implement the necessary support code for taking exceptions
> to Hyp mode in AArch32.
Hi Peter,
A general comment that I think this would be a little easier
to look at if it was split into two patches, one non-functional
change to
ime check wo do in msr_mrs_banked_exc_checks() had the
> correct code in it, but never got there because of the earlier
> "currmode == tgtmode" check. Special case ELR_Hyp.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/op_helper.
add the missing stanza to
> el3_no_el2_cp_reginfo.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> target/arm/helper.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index d
On Tue, Aug 14, 2018 at 01:42:48PM +0100, Peter Maydell wrote:
> Implement the AArch32 HVBAR register; we can do this just by
> making the existing VBAR_EL2 regdefs be STATE_BOTH.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
> ---
> target/arm/helper.c
t;
> Implement the accessors for these. This fixes in passing a bug
> where we weren't implementing the "RES0 from EL3 if EL2 not
> implemented" behaviour for AArch64 FAR_EL2.
>
> Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
> ---
> target/arm/help
ething other than RAZ/WI).
>
> Signed-off-by: Peter Maydell
Reviewed-by: Edgar E. Iglesias
> ---
> target/arm/helper.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 466c8ae492e..14fd78f587a 100644
> -
On Tue, Aug 14, 2018 at 01:42:49PM +0100, Peter Maydell wrote:
> The AArch32 HCR and HCR2 registers alias HCR_EL2
> bits [31:0] and [63:32]; implement them.
Reviewed-by: Edgar E. Iglesias
>
> Signed-off-by: Peter Maydell
> ---
> target
On Tue, Aug 14, 2018 at 01:42:46PM +0100, Peter Maydell wrote:
> ARMCPRegInfo structs will not default to .cp = 15 if they
^^^
I think you've got a typo here
Otherwise:
Reviewed-by: Edgar E. Iglesias
> are ARM_CP_STAT
: Peter Maydell
Reviewed-by: Edgar E. Iglesias
> ---
> target/arm/helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 8b07bf214ec..2c5e02c0b1a 100644
> --- a/target/arm/helper.c
> +++ b/t
86)
> ==13605==by 0x2AC69A: qbus_print (qdev-monitor.c:719)
> ==13605==by 0x2591E8: handle_hmp_command (monitor.c:3446)
>
> Use the new object_initialize_child() and sysbus_init_child_obj() to
> fix the issue.
>
> Signed-off-by: Thomas Huth
Reviewed-by: Edgar E. Iglesias
Pete
mapped
> only when virtualization extensions are requested. The
> XlnxZynqMPGICRegion struct has been enhanced to be able to catch all
> this information.
>
> Signed-off-by: Luc Michel
Looks good to me!
Reviewed-by: Edgar E. Iglesias
> ---
> hw/arm/xlnx-zynqmp.c
On Wed, Jun 27, 2018 at 05:34:15PM -0700, Guenter Roeck wrote:
> Hi Edgar,
>
> On 06/27/2018 03:47 PM, Edgar E. Iglesias wrote:
>
> >
> > Hi Guenter,
> >
> > Re: ml605
> > The thing to watch out for with kernel configs for microblaze systems is the
On Wed, Jun 27, 2018 at 01:59:15PM -0700, Guenter Roeck wrote:
> On Wed, Jun 27, 2018 at 05:01:34PM -0300, Philippe Mathieu-Daudé wrote:
> > Hi Guenter,
> >
> > On 06/27/2018 03:52 PM, Guenter Roeck wrote:
> > > Hi,
> > >
> > > I would like to add Microblaze "petalogix-ml605" and
On Wed, Jun 20, 2018 at 07:47:55PM +0530, Sai Pavan Boddu wrote:
> Qspi dma has a burst length of 64 bytes, So limit the transactions w.r.t
> dma-burst-size property.
Thanks Sai,
A nitpick, it's probably better to put dma_buf at thend of XlnxZynqMPQSPIPS
but in any case:
Reviewed-by: E
On Tue, May 29, 2018 at 02:47:05PM +0200, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias"
>
> The ZynqMP actually has Cortex-R5Fs with the optional FPU enabled.
Hi Peter,
Any comments on this series?
Cheers,
Edgar
>
> Cheers,
> Edgar
>
> ChangeLog
On Wed, Jun 20, 2018 at 02:00:00AM +0530, Sai Pavan Boddu wrote:
> Qspi dma has a burst length of 64 bytes, So limit transaction length to
> 64 max.
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/ssi/xilinx_spips.c | 20 +---
> include/hw/ssi/xilinx_spips.h | 5 -
>
From: "Edgar E. Iglesias"
Correct the masking of output addresses.
This fixes Coverity CID 1391441.
Fixes: commit 3924a9aa02
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Reported-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/mmu.
From: "Edgar E. Iglesias"
Remove the abort on a sequence of NOP/zero instructions.
Always return early and avoid decoding NOP/zero instructions.
This fixes Coverity CID 1391443.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/transl
From: "Edgar E. Iglesias"
The following changes since commit 3b2a4d3901b8b45840c0e0495ee1cbd13123739d:
Merge remote-tracking branch
'remotes/vivier2/tags/linux-user-for-3.0-pull-request' into staging (2018-06-12
16:42:53 +0100)
are available in the git repositor
From: "Edgar E. Iglesias"
Correct the masking of output addresses.
This fixes Coverity CID 1391441.
Fixes: commit 3924a9aa02
Reported-by: Peter Maydell
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/mmu.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/microbla
From: "Edgar E. Iglesias"
Remove the abort on a sequence of NOP/zero instructions.
Always return early and avoid decoding NOP/zero instructions.
This fixes Coverity CID 1391443.
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 15 ---
1 file
From: "Edgar E. Iglesias"
This series has fixes for the Coverity issues that Peter Maydell
reported.
CID 1391441
CID 1391443
Best regards,
Edgar
Edgar E. Iglesias (2):
target-microblaze: mmu: Correct masking of output addresses
target-microblaze: Rework NOP/zero instructio
On Thu, Jun 14, 2018 at 10:57:04AM +0530, Sai Pavan Boddu wrote:
> Qspi dma has a burst length of 64 bytes, So limit transaction length to
> 64 max.
Hi Sai,
Is this a v2 or a resend?
>
> Signed-off-by: Sai Pavan Boddu
> ---
> hw/ssi/xilinx_spips.c | 18 +++---
>
From: "Edgar E. Iglesias"
The ZynqMP has Cortex-R5Fs with the optional FPU enabled.
Reviewed-by: KONRAD Frederic
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
---
hw/arm/xlnx-zcu102.c | 2
From: "Edgar E. Iglesias"
Add the Cortex-R5F with the optional FPU enabled.
Reviewed-by: KONRAD Frederic
Reviewed-by: Alistair Francis
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
---
target/arm/cpu.c | 9 +
1 fi
From: "Edgar E. Iglesias"
The ZynqMP actually has Cortex-R5Fs with the optional FPU enabled.
Cheers,
Edgar
ChangeLog:
v1 -> v2:
* Update ZCU102 description to mention R5Fs
Edgar E. Iglesias (2):
target-arm: Add the Cortex-R5F
xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F
From: "Edgar E. Iglesias"
Fixup the indentation of cpu_mmu_index in preparation for
future edits.
No functional changes.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 16 +---
1 file
From: "Edgar E. Iglesias"
Remove argument b in eval_cc() as it is always set to zero.
No functional change.
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --gi
From: "Edgar E. Iglesias"
Cleanup debug log messages:
* Avoid long 80+ character lines.
* Remove D() macro and use qemu_log_mask.
* Remove logs that are not very useful
Suggested-by: Alistair Francis
Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Signed-off-b
From: "Edgar E. Iglesias"
Plug a temp leak.
Reported-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/microblaze/tra
From: "Edgar E. Iglesias"
Add explicit handling for MMU_R_TLBX and log accesses to
invalid MMU registers. We can now remove the state for
all regs but PID, ZPR and TLBX (0 - 2).
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
-
From: "Edgar E. Iglesias"
Consolidate MMU enabled checks to cpu_mmu_index().
No functional changes.
Suggested-by: Richard Henderson
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h| 4 +++-
target/
From: "Edgar E. Iglesias"
Add a R_TBLX_MISS MASK and SHIFT macros.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/mmu.c | 5 +++--
target/microblaze/mmu.h | 4
2 files changed, 7 insertions(+), 2 deletion
From: "Edgar E. Iglesias"
Fix moves to FSR. Not only bit 31 is accessible.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/
From: "Edgar E. Iglesias"
Cleanup eval_cond_jmp to use tcg_gen_movcond_i64().
No functional change.
Suggested-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 16 +
From: "Edgar E. Iglesias"
Simplify address computation using tcg_gen_addi_i32().
tcg_gen_addi_i32() already optimizes the case when the
immediate is zero.
No functional change.
Suggested-by: Richard Henderson
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
From: "Edgar E. Iglesias"
Reuse more code when decoding register numbers.
No functional changes.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 38 +-
1 file
From: "Edgar E. Iglesias"
Add support for extended access to TLBLO's upper 32 bits.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/helper.h| 4 ++--
target/microblaze/mmu.c | 18 ++
target/microblaze/mmu.h
From: "Edgar E. Iglesias"
Break out trap_illegal() to handle illegal operation traps.
We now generally stop translation of the current insn if
it's not valid.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
---
target/
On Thu, May 10, 2018 at 03:09:46PM -0300, Philippe Mathieu-Daudé wrote:
> Hi Edgar,
>
> On 05/03/2018 08:56 AM, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias"
> >
> > The ZynqMP has Cortex-R5Fs with the optional FPU enabled.
>
> What about u
From: "Edgar E. Iglesias"
Add a configurable output address mask, used to mimic the
configurable physical address bit width.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.c | 1 +
target/microblaze/mmu.c | 1
From: "Edgar E. Iglesias"
Break out trap_userspace() to avoid open coding it everywhere.
For privileged insns, we now always stop translation of the
current insn for cores without exceptions.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E
From: "Edgar E. Iglesias"
Use a table based conversion to map condition-codes between
MicroBlaze ISA encoding and TCG.
No functional change.
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 41 --
From: "Edgar E. Iglesias"
Setup MicroBlaze builds for 64bit addressing.
No functional change since the translator does not yet
emit 64bit addresses.
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
configure | 1 +
target/microblaze/cpu.h | 6 +++--
From: "Edgar E. Iglesias"
Tighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when
TCGv_i32 should be used.
This is in preparation for adding 64bit addressing support.
No functional change.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E
From: "Edgar E. Iglesias"
Convert env_btarget to i64.
No functional change.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 2 +-
target/microblaze/op_helper.c | 2 +-
target/microblaze/t
From: "Edgar E. Iglesias"
Make compute_ldst_addr always use a temp. This simplifies
the code a bit in preparation for adding support for
64bit addresses.
No functional change.
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Edgar E. Iglesias
-
From: "Edgar E. Iglesias"
Allow address sizes between 32 and 64 bits.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/microbla
From: "Edgar E. Iglesias"
Name special registers we support.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/t
From: "Edgar E. Iglesias"
Prepare for 64-bit addresses.
This makes no functional difference as the upper parts of
the 64-bit addresses are not yet reachable.
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/mmu.c | 14 +++---
target/
From: "Edgar E. Iglesias"
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/microblaze/translate.
From: "Edgar E. Iglesias"
Implement MFSE EAR to enable access to the upper part of EAR.
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/t
From: "Edgar E. Iglesias"
Conditionalize setting of PVR11_USE_MMU on the use_mmu
CPU property, otherwise we may incorrectly advertise an
MMU via PVR when the core in fact has none.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
-
From: "Edgar E. Iglesias"
Extend special registers to 64-bits. This is in preparation for
MFSE/MTSE, moves to and from extended special registers.
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
linux-user/microblaze/cpu_loop.c | 4 +-
target/microb
From: "Edgar E. Iglesias"
Use bool and extract32 to represent the to, clr and
clrset flags.
No functional change.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 15 +--
1 file
From: "Edgar E. Iglesias"
We already have a CPU property to control if a core has
an MMU or not. Remove USE_MMU PVR checks in favor of
looking at the property.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/hel
From: "Edgar E. Iglesias"
Today, when running QEMU in linux-user or with boards that don't
select a specific CPU version, we treat it as an invalid version
and log a message.
Instead, if no specific version was selected, fallback to our
latest CPU version.
Reviewed-by: Alistair Franc
From: "Edgar E. Iglesias"
Use TCGv for load/store addresses, allowing for future
computation of 64-bit load/store address.
No functional change.
Acked-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 2
From: "Edgar E. Iglesias"
Correct the PVR array size, there are 13 PVR registers.
Reviewed-by: Alistair Francis
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/microblaze/cpu.h b/target/microb
From: "Edgar E. Iglesias"
Bypass MMU translation when mmu-index MMU_NOMMU_IDX is used.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/helper.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --gi
From: "Edgar E. Iglesias"
Use bool instead of int to represent flags.
No functional change.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 10 +-
1 file changed, 5 insertions(+), 5 deletion
From: "Edgar E. Iglesias"
Use bool instead of unsigned int to represent flags.
Also, use extract32 instead of open coding the bit extract.
No functional change.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/t
From: "Edgar E. Iglesias"
Use bool instead of unsigned int to represent flags.
No functional change.
Reviewed-by: Alistair Francis
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/translate.c | 7 ---
1 file changed, 4 insertions(+), 3
From: "Edgar E. Iglesias"
Correct special register array sizes.
Reviewed-by: Richard Henderson
Signed-off-by: Edgar E. Iglesias
---
target/microblaze/cpu.h | 4 ++--
target/microblaze/translate.c | 5 ++---
2 files changed, 4 insertions(+), 5 deletions(-)
diff --gi
From: "Edgar E. Iglesias"
The following changes since commit 5a5c383b1373aeb6c87a0d6060f6c3dc7c53082b:
Merge remote-tracking branch
'remotes/vivier2/tags/linux-user-for-2.13-pull-request' into staging
(2018-05-25 10:04:36 +0100)
are available in the git repositor
n the max of a
> byte
> on the second argument (CID 1391286). This patch corrects this by adding the
> freeing of the strings and also changing to memset to zero instead on
> descriptor unaligned errors.
Perhaps this should have been two patches but in any case:
Reviewed-
From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Conditionalize setting of PVR11_USE_MMU on the use_mmu
CPU property, otherwise we may incorrectly advertise an
MMU via PVR when the core in fact has none.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
This series adds support for Extended Addressing to our MicroBlaze
models. It adds both the non-MMU load/store EA and the extended MMU
addressing.
There are several ways to implement this but since there are further
6
On Thu, May 17, 2018 at 10:34:38AM -0700, Richard Henderson wrote:
> On 05/16/2018 11:51 AM, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
> >
> > Convert env_btarget to i64.
> > No functional change.
> >
On Thu, May 17, 2018 at 10:26:00AM -0700, Richard Henderson wrote:
> On 05/16/2018 11:51 AM, Edgar E. Iglesias wrote:
> > -env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
> > +env->pvr.regs[11] = cpu->cfg.use_mmu ? PVR11_USE_MMU : 0 |
> > +
On Thu, May 17, 2018 at 11:48:35AM -0300, Philippe Mathieu-Daudé wrote:
> Hi Edgar,
>
> On 05/17/2018 11:22 AM, Philippe Mathieu-Daudé wrote:
> > On 05/16/2018 03:51 PM, Edgar E. Iglesias wrote:
> >> From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
On Thu, May 17, 2018 at 11:39:41AM -0300, Philippe Mathieu-Daudé wrote:
> On 05/16/2018 03:51 PM, Edgar E. Iglesias wrote:
> > From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
> >
> > Make compute_ldst_addr always use a temp. This simplifies
> &g
From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Consolidate MMU enabled checks to cpu_mmu_index().
No functional changes.
Suggested-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
---
ta
From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Fixup the indentation of cpu_mmu_index in preparation for
future edits.
No functional changes.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
---
target/microblaze/cpu.h | 16 +---
1 file chang
From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Plug a temp leak.
Reported-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
---
target/microblaze/translate.c | 13 +
1 file changed,
From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Add a R_TBLX_MISS MASK and SHIFT macros.
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.i
From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Convert env_btarget to i64.
No functional change.
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
---
target/microblaze/cpu.h | 2 +-
target/microblaze/op_helper.c | 2 +-
target/micro
From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Setup MicroBlaze builds for 64bit addressing.
No functional change since the translator does not yet
emit 64bit addresses.
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Edgar E.
From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
Cleanup eval_cond_jmp to use tcg_gen_movcond_i64().
No functional change.
Suggested-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
---
target
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