[Qemu-devel] [PATCH v1 07/29] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Tighten up TCGv_i32 vs TCGv type usage. Avoid using TCGv when TCGv_i32 should be used. This is in preparation for adding 64bit addressing support. No functional change. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xili

[Qemu-devel] [PATCH v1 04/29] target-microblaze: Fallback to our latest CPU version

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Today, when running QEMU in linux-user or with boards that don't select a specific CPU version, we treat it as an invalid version and log a message. Instead, if no specific version was selected, fallback to our latest CPU vers

[Qemu-devel] [PATCH v1 05/29] target-microblaze: Correct special register array sizes

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Correct special register array sizes. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/cpu.h | 4 ++-- target/microblaze/translate.c | 5 ++--- 2 files changed, 4 insertions(+)

[Qemu-devel] [PATCH v1 10/29] target-microblaze: Bypass MMU with MMU_NOMMU_IDX

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Bypass MMU translation when mmu-index MMU_NOMMU_IDX is used. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --g

[Qemu-devel] [PATCH v1 09/29] target-microblaze: Conditionalize setting of PVR11_USE_MMU

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Conditionalize setting of PVR11_USE_MMU on the use_mmu CPU property, otherwise we may incorrectly advertise an MMU via PVR when the core in fact has none. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>

[Qemu-devel] [PATCH v1 02/29] target-microblaze: dec_store: Use bool instead of unsigned int

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Use bool instead of unsigned int to represent flags. Also, use extract32 instead of open coding the bit extract. No functional change. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/micr

[Qemu-devel] [PATCH v1 00/29] target-microblaze: Add support for Extended Addressing

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> This series adds support for Extended Addressing to our MicroBlaze models. It adds both the non-MMU load/store EA and the extended MMU addressing. There are several ways to implement this but since there are further 6

[Qemu-devel] [PATCH v1 01/29] target-microblaze: dec_load: Use bool instead of unsigned int

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Use bool instead of unsigned int to represent flags. No functional change. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/translate.c | 7 --- 1 file changed, 4 insertions(+)

[Qemu-devel] [PATCH v1 03/29] target-microblaze: compute_ldst_addr: Use bool instead of int

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Use bool instead of int to represent flags. No functional change. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/translate.c | 10 +- 1 file changed, 5 insertions(+), 5 de

Re: [Qemu-devel] [PATCH v2 1/2] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA

On Wed, May 02, 2018 at 10:06:39PM +0200, Francisco Iglesias wrote: > Add a model of the generic DMA found on Xilinx ZynqMP. Hi Francisco, A few more comments: > > Signed-off-by: Francisco Iglesias <frasse.igles...@gmail.com> > Signed-off-by: Edgar E. Iglesias <edga

[Qemu-devel] [PULL v1 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Make the TLBX MISS bit read-only. Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.co

[Qemu-devel] [PULL v1 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Do not clobber the IMM register on reversed load/stores. Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/translate

[Qemu-devel] [PULL v1 2/5] target-microblaze: Fix trap checks for FPU insns

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Fix trap checks for FPU insns when extended FPU insns are enabled. Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Ed

[Qemu-devel] [PULL v1 0/5] Xilinx queue 2018-04-30

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> The following changes since commit 6f0c4706b35dead265509115ddbd2a8d1af516c1: Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180427-pull-request' into staging (2018-04-27 12:27:59 +0100) are available in th

[Qemu-devel] [PULL v1 4/5] target-microblaze: mmu: Make TLBSX write-only

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Make TLBSX write-only and guest-error log reads from it. Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Edgar E. Iglesia

[Qemu-devel] [PULL v1 1/5] target-microblaze: Respect MSR.PVR as read-only

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit. Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/micr

Re: [Qemu-devel] [PATCH v13 20/30] sdbus: add trace events

On Fri, Apr 27, 2018 at 12:55:21PM +0100, Peter Maydell wrote: > On 13 February 2018 at 04:07, Philippe Mathieu-Daudé wrote: > > Signed-off-by: Philippe Mathieu-Daudé > > Reviewed-by: Alistair Francis > > > @@ -39,6 +45,7 @@ int

Re: [Qemu-devel] [PATCH v1 1/2] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA

frasse.igles...@gmail.com> > Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > hw/dma/Makefile.objs | 1 + > hw/dma/xlnx-zdma.c | 833 > + > include/hw/dma/xlnx-zdma.h | 84 + > 3 files

[Qemu-devel] [PATCH v2 4/5] target-microblaze: mmu: Make TLBSX write-only

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Make TLBSX write-only and guest-error log reads from it. Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/mmu.c

[Qemu-devel] [PATCH v2 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Make the TLBX MISS bit read-only. Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/mmu.c | 4 1 file changed,

[Qemu-devel] [PATCH v2 1/5] target-microblaze: Respect MSR.PVR as read-only

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-

[Qemu-devel] [PATCH v2 2/5] target-microblaze: Fix trap checks for FPU insns

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Fix trap checks for FPU insns when extended FPU insns are enabled. Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/transl

[Qemu-devel] [PATCH v2 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Do not clobber the IMM register on reversed load/stores. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mi

[Qemu-devel] [PATCH v2 0/5] target-microblaze: Misc bug fixes

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Hi, This is a series of fixes for bugs I ran into when adding support for extended addressing. It would be nice to get these into 2.12 if it's not too late. Cheers, Edgar ChangeLog: v1 -> v2: * Corrected fix makin

Re: [Qemu-devel] [PATCH v2] migration: discard non-migratable RAMBlocks

On Fri, Apr 20, 2018 at 10:14:15AM +0200, KONRAD Frederic wrote: > > > On 04/19/2018 07:45 PM, Edgar E. Iglesias wrote: > > On Thu, Apr 19, 2018 at 06:32:07PM +0100, Peter Maydell wrote: > > > On 13 April 2018 at 08:52, Cédric Le Goater <c...@kaod.org> wrote: &

Re: [Qemu-devel] [PATCH v1 1/5] target-microblaze: Respect MSR.PVR as read-only

On Thu, Apr 19, 2018 at 11:17:58AM -1000, Richard Henderson wrote: > On 04/19/2018 10:33 AM, Edgar E. Iglesias wrote: > > On Thu, Apr 19, 2018 at 09:56:40AM -1000, Richard Henderson wrote: > >> On 04/19/2018 01:21 AM, Edgar E. Iglesias wrote: > >>> static inline v

Re: [Qemu-devel] [PATCH v1 1/5] target-microblaze: Respect MSR.PVR as read-only

On Thu, Apr 19, 2018 at 09:56:40AM -1000, Richard Henderson wrote: > On 04/19/2018 01:21 AM, Edgar E. Iglesias wrote: > > static inline void msr_write(DisasContext *dc, TCGv v) > > { > > -TCGv t; > > - > > -t = tcg_temp_new(); > > dc->

Re: [Qemu-devel] [PATCH v2] migration: discard non-migratable RAMBlocks

On Thu, Apr 19, 2018 at 06:32:07PM +0100, Peter Maydell wrote: > On 13 April 2018 at 08:52, Cédric Le Goater wrote: > > On the POWER9 processor, the XIVE interrupt controller can control > > interrupt sources using MMIO to trigger events, to EOI or to turn off > > the sources.

[Qemu-devel] [PATCH v1 5/5] target-microblaze: mmu: Make the TLBX MISS bit read-only

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Make the TLBX MISS bit read-only. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/mmu.c | 4 1 file changed, 4 insertions(+) diff --git a/target/microblaze/mmu.c b/target/

[Qemu-devel] [PATCH v1 2/5] target-microblaze: Fix trap checks for FPU insns

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Fix trap checks for FPU insns when extended FPU insns are enabled. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-

[Qemu-devel] [PATCH v1 3/5] target-microblaze: Don't clobber the IMM reg for ld/st reversed

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Do not clobber the IMM register on reversed load/stores. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/mi

[Qemu-devel] [PATCH v1 1/5] target-microblaze: Respect MSR.PVR as read-only

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Respect MSR.PVR as read-only. We were wrongly overwriting the PVR bit. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/cpu.h | 4 +++- target/microblaze/translate.c | 8 +-

[Qemu-devel] [PATCH v1 0/5] target-microblaze: Misc bug fixes

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Hi, This is a series of fixes for bugs I ran into when adding support for extended addressing. It would be nice to get these into 2.12 if it's not too late. Cheers, Edgar Edgar E. Iglesias (5): target-microblaze: Respect

[Qemu-devel] [PATCH v1 4/5] target-microblaze: mmu: Make TLBSX write-only

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Make TLBSX write-only and guest-error log reads from it. Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- target/microblaze/mmu.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/t

[Qemu-devel] TCG MicroBlaze 64-bit extended addressing

Hello, I'm looking at adding support for MicroBlaze extended addressing allowing 32bit cores to reach a 64-bit address space. The ABI for MicroBlaze remains 32-bits. It's basically a PAE-like MMU extension + a new set of extended address Load/Store instructions for the non-MMU mode. I'm

Re: [Qemu-devel] microblaze stack pointer?

On Wed, Apr 04, 2018 at 02:30:26PM +0200, Laurent Vivier wrote: > Hi, Hi Laurent, > > cleaning up linux-user signal handling functions, I found something weird. > > In get_sp_from_cpustate(), SP is regs[14]: > > linux-user/microblaze/target_signal.h > > 24) static inline abi_ulong

Re: [Qemu-devel] [PATCH 5/8] sdcard: Implement the UHS-I SWITCH_FUNCTION entries (Spec v3)

ed-off-by: Philippe Mathieu-Daudé <f4...@amsat.org> > > This should ideally have a Signed-off-by: from somebody @xilinx.com as > well as you, then. Hi Philippe, Feel free to add my SoB on the next spin of this: Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Ch

Re: [Qemu-devel] [PATCH v6 02/23] exec: add ram_debug_ops support

On Tue, Jan 30, 2018 at 04:34:37PM -0600, Brijesh Singh wrote: > > > On 1/30/18 3:59 PM, Edgar E. Iglesias wrote: > > On Mon, Jan 29, 2018 at 11:41:11AM -0600, Brijesh Singh wrote: > >> Currently, the guest memory access for the debug purpose is performed > >>

Re: [Qemu-devel] [PATCH v6 02/23] exec: add ram_debug_ops support

On Mon, Jan 29, 2018 at 11:41:11AM -0600, Brijesh Singh wrote: > Currently, the guest memory access for the debug purpose is performed > using the memcpy(). Lets extend the 'struct MemoryRegion' to include > ram_debug_ops callbacks. The ram_debug_ops can be used to override > memcpy() with

Re: [Qemu-devel] [PATCH v6 01/23] memattrs: add debug attribute

dell <peter.mayd...@linaro.org> > Cc: Edgar E. Iglesias" <edgar.igles...@xilinx.com> > Cc: Richard Henderson <richard.hender...@linaro.org> > Cc: Paolo Bonzini <pbonz...@redhat.com> > Signed-off-by: Brijesh Singh <brijesh.si...@amd.com> Reviewed-by: E

[Qemu-devel] [PULL v2 8/9] xlnx-zynqmp-pmu: Connect the IPI device to the PMU

From: Alistair Francis <alistair.fran...@xilinx.com> Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- hw/microblaz

[Qemu-devel] [PULL v2 0/9] Xilinx queue

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> The following changes since commit 2077fef91d5eb8e3745a84fabd87a5ee7d2b535d: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180125' into staging (2018-01-25 17:04:47 +) are available in th

[Qemu-devel] [PULL v2 2/9] xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU

still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Edgar E. Iglesias

[Qemu-devel] [PULL v2 5/9] xlnx-pmu-iomod-intc: Add the PMU Interrupt controller

From: Alistair Francis <alistair.fran...@xilinx.com> Add the PMU IO Module Interrupt controller device. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@

[Qemu-devel] [PULL v2 1/9] microblaze: boot.c: Don't try to find NULL file

ilinx.com> Reported-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- hw/microblaze/boot.c | 2 +- 1 file

[Qemu-devel] [PULL v2 7/9] xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device

From: Alistair Francis <alistair.fran...@xilinx.com> This is the initial version of the Inter Processor Interrupt device. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Signed-off-by: Edgar E. Igl

[Qemu-devel] [PULL v2 4/9] aarch64-softmmu.mak: Use an ARM specific config

o.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- default-configs/aarch64-softmmu.mak | 1 + hw/arm/Makefile.objs| 2 +- hw/

[Qemu-devel] [PULL v2 3/9] xlnx-zynqmp-pmu: Add the CPU and memory

From: Alistair Francis <alistair.fran...@xilinx.com> Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Signed-off-by: Edgar E. Iglesias <edga

Re: [Qemu-devel] [PATCH v5 3/9] xlnx-zynqmp-pmu: Add the CPU and memory

On Tue, Jan 16, 2018 at 03:22:26PM -0800, Alistair Francis wrote: > Connect the MicroBlaze CPU and the ROM and RAM memory regions. > > Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> > Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- >

Re: [Qemu-devel] [PATCH v5 1/9] microblaze: boot.c: Don't try to find NULL pointer

<alistair.fran...@xilinx.com> > Reported-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > > hw/microblaze/boot.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

Re: [Qemu-devel] [PULL v1 0/8] Xilinx queue

On Tue, Jan 16, 2018 at 02:17:04PM +, Peter Maydell wrote: > On 16 January 2018 at 11:50, Edgar E. Iglesias <edgar.igles...@gmail.com> > wrote: > > From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> > > > > The following changes since c

[Qemu-devel] [PULL v1 7/8] xlnx-zynqmp-pmu: Connect the IPI device to the PMU

From: Alistair Francis <alistair.fran...@xilinx.com> Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- hw/microblaz

[Qemu-devel] [PULL v1 6/8] xlnx-zynqmp-ipi: Initial version of the Xilinx IPI device

From: Alistair Francis <alistair.fran...@xilinx.com> This is the initial version of the Inter Processor Interrupt device. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Signed-off-by: Edgar E. Igl

[Qemu-devel] [PULL v1 2/8] xlnx-zynqmp-pmu: Add the CPU and memory

From: Alistair Francis <alistair.fran...@xilinx.com> Connect the MicroBlaze CPU and the ROM and RAM memory regions. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Signed-off-by: Edgar E. Iglesias <edga

[Qemu-devel] [PULL v1 3/8] aarch64-softmmu.mak: Use an ARM specific config

o.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> --- default-configs/aarch64-softmmu.mak | 1 + hw/arm/Makefile.objs| 2 +- hw/display/Makefile.objs| 2 +- hw/dma/Makefile.objs

[Qemu-devel] [PULL v1 1/8] xlnx-zynqmp-pmu: Initial commit of the ZynqMP PMU

still going to follow the same split as maybe in future we can connect the PMU device to the ARM ZCU102 board. As the machine will be fairly small let's keep them both together in one file. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Edgar E. Iglesias

[Qemu-devel] [PULL v1 4/8] xlnx-pmu-iomod-intc: Add the PMU Interrupt controller

From: Alistair Francis <alistair.fran...@xilinx.com> Add the PMU IO Module Interrupt controller device. Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Signed-off-by: Edgar E. Iglesias <edga

[Qemu-devel] [PULL v1 0/8] Xilinx queue

From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> The following changes since commit f5213bd060b460c99e605472b7e03967db43: Merge remote-tracking branch 'remotes/juanquintela/tags/migration/20180115' into staging (2018-01-15 13:17:47 +) are available in the git rep

Re: [Qemu-devel] [PATCH 0/4] Trivial changes in "registerfields.h"

/deposit macros > hw/registerfields: add missing include > > include/hw/registerfields.h | 15 ++- > MAINTAINERS | 1 + > 2 files changed, 15 insertions(+), 1 deletion(-) Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>

Re: [Qemu-devel] [PATCH 00/12] Refactor get_phys_addr() not to return FSR values

check this hasn't broken Xen again :-) > > Based-on: 1512153879-5291-1-git-send-email-peter.mayd...@linaro.org > ([PATCH 0/7] armv8m: Implement TT, and other bugfixes) Hi Peter, Thans for working on this, the series looks good to me! Reviewed-by: Edgar E. Iglesias <edgar.igles...@x

Re: [Qemu-devel] [PATCH v5 01/23] memattrs: add debug attribute

On Fri, Dec 08, 2017 at 09:55:26AM +, Peter Maydell wrote: > On 7 December 2017 at 21:20, Brijesh Singh wrote: > > On 12/06/2017 04:03 PM, Peter Maydell wrote: > >> For instance, if a device gets a debug=1 transaction > >> should it refuse to do things like

Re: [Qemu-devel] [PATCH v4 0/8] Add the ZynqMP PMU and IPI

tair, I've merged this into mb-next for 2.12. Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Best regards, Edgar > > V4: > - Rename the ZCU102 machine to just ZynqMP > - Rename the PMC SoC to "xlnx,zynqmp-pmu-soc" > - Move the IPI device to the machine

Re: [Qemu-devel] [PATCH v8 00/13] Add support for the ZynqMP Generic QSPI

lnx-zcu102 board. > > Best regards, > Francisco Iglesias The entire series looks good to me: Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> I also ran some regressions tests on it: Tested-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> Thanks! Edgar >

Re: [Qemu-devel] [PATCH] arm: check regime, not current state, for ATS write PAR format

given that we are in freeze. > > > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> > > Tested-by: Stefano Stabellini <sstabell...@kernel.org> Hi, This looks like an OK workaround for the moment: Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>

Re: [Qemu-devel] [PATCH v3 0/8] Add the ZynqMP PMU and IPI

On Oct 10, 2017 7:59 PM, "Alistair Francis" <alistair.fran...@xilinx.com> wrote: On Tue, Oct 10, 2017 at 7:48 AM, Edgar E. Iglesias <edgar.igles...@gmail.com> wrote: > On Mon, Oct 09, 2017 at 05:12:39PM -0700, Alistair Francis wrote: >> On Sun, Oct 8, 201

Re: [Qemu-devel] [PATCH v3 0/8] Add the ZynqMP PMU and IPI

On Mon, Oct 09, 2017 at 05:12:39PM -0700, Alistair Francis wrote: > On Sun, Oct 8, 2017 at 3:20 PM, Edgar E. Iglesias > <edgar.igles...@xilinx.com> wrote: > > On Wed, Sep 20, 2017 at 03:01:31PM -0700, Alistair Francis wrote: > >> > >> This series adds the ZynqMP

Re: [Qemu-devel] [PATCH v5 0/7] Generalize MDIO framework

On Fri, Sep 22, 2017 at 02:13:16PM -0300, Philippe Mathieu-Daudé wrote: > Hi, > > I have a follow up series using multiples PHY on the MDIO bus based on this > series. Hi Philippe! I think this is a good improvement compared to todays state. It may make sense to have the generic mdio bus

Re: [Qemu-devel] [PATCH v3 0/8] Add the ZynqMP PMU and IPI

On Wed, Sep 20, 2017 at 03:01:31PM -0700, Alistair Francis wrote: > > This series adds the ZynqMP Power Management Unit (PMU) machine with basic > functionality. > > The machine only has the > - CPU > - Memory > - Interrupt controller > - IPI device > > connected, but that is enough to run

Re: [Qemu-devel] [PATCH v1 2/2] target-arm: Extend PAR format determination

On Mon, Sep 18, 2017 at 04:50:23PM +0100, Peter Maydell wrote: > On 11 July 2017 at 11:38, Edgar E. Iglesias <edgar.igles...@xilinx.com> wrote: > > Another way could also be to have get_phys_addr() fill in generic > > fields in the FaultInfo struct and then have a faultin

Re: [Qemu-devel] [PATCH Resend v2 0/5] Expose the secure and virt properties to the

e > and also add a virt property that can enable EL2. > > This series also does some machine/name tidying up and makes the first > move to deprecating the EP108 machine, which was just an early access > development board. > > V2: > - Add a virt option for setting EL2 T

Re: [Qemu-devel] [PATCH v2 2/2] Add a unique ID in the virt machine to be used as device ID

On Tue, Aug 22, 2017 at 10:04:25PM +0300, Michael S. Tsirkin wrote: > On Tue, Aug 22, 2017 at 03:13:57PM +, Diana Madalina Craciun wrote: > > On 08/11/2017 06:50 PM, Edgar E. Iglesias wrote: > > > On Fri, Aug 11, 2017 at 02:35:28PM +, Diana Madalina Craciun wrot

Re: [Qemu-devel] [PATCH v1 2/5] xlnx-zcu102: Manually create the machines

On Thu, Aug 17, 2017 at 11:52:04AM -0700, Alistair Francis wrote: > In preperation for future work let's manually create the Xilnx machines. > This will allow us to set properties for the machines in the future. > > Signed-off-by: Alistair Francis > --- > >

Re: [Qemu-devel] [PATCH v1 0/5] Expose the secure property to the machine

On Thu, Aug 17, 2017 at 11:51:59AM -0700, Alistair Francis wrote: > The EL2 and EL3 work is working well now and interanlly we now have > tests that expect to start in EL3 and transition through EL2 to EL1. To > make this easy to run let's expose the secure property to the machine > and then use

Re: [Qemu-devel] [PATCH for-2.10] mmio-interface: Mark as not user creatable

ntended to be created directly by the user. > > + */ > > +dc->user_creatable = false; > > } > > > > static const TypeInfo mmio_interface_info = { > > > > Reviewed-by: Thomas Huth <th...@redhat.com> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>

Re: [Qemu-devel] [PATCH v1 0/3] Fixup exclusive store logic

On Sat, Aug 12, 2017 at 11:24:30AM +0100, Peter Maydell wrote: > On 11 August 2017 at 23:17, Alistair Francis > wrote: > > I found some issues with the way exclusive store was working. This patch > > series seems to fix the test cases that were failing for me. > > > >

Re: [Qemu-devel] [PATCH v1 2/3] tcg/tcg-op: Expose the tcg_gen_ext_i* functions

On Fri, Aug 11, 2017 at 03:17:38PM -0700, Alistair Francis wrote: > Expose the tcg_gen_ext_i32() and tcg_gen_ext_i64() functions. > > Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Review

Re: [Qemu-devel] [PATCH v1 1/3] target/arm: Update the memops for exclusive load

> Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> > Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > > target/arm/translate-a64.c | 2 +- > 1 file changed, 1 insertio

Re: [Qemu-devel] [PATCH v1 3/3] target/arm: Correct exclusive store cmpxchg memop mask

igh register to be ignored. To fix this issue we hardcode the size to > be 64-bits long when operating on 32-bit pairs. Good catch Alistair! Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > > Signed-off-by: Alistair Francis <alistair.fran...@xilinx.c

Re: [Qemu-devel] [PATCH v2 2/2] Add a unique ID in the virt machine to be used as device ID

On Fri, Aug 11, 2017 at 02:35:28PM +, Diana Madalina Craciun wrote: > Hi Edgar, > > On 07/31/2017 06:16 PM, Edgar E. Iglesias wrote: > > On Wed, Jul 26, 2017 at 02:22:28PM +0200, Auger Eric wrote: > >> Hi Diana, > >> On 23/05/2017 13:12, Diana Craciun wro

Re: [Qemu-devel] [PATCH V2 for-2.10] xlnx-qspi: add a property for mmio-execution

On Fri, Aug 11, 2017 at 09:54:12AM +0200, KONRAD Frederic wrote: > This adds mmio-exec property to workaround the migration bug. > When enabled the migration is blocked and will return an error. > > Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.com> Thanks Fred! Re

Re: [Qemu-devel] [PATCH for-2.10 2/2] xilinx-spips: add a migration blocker when using mmio_execution

On Thu, Aug 10, 2017 at 10:11:13AM +0100, Peter Maydell wrote: > On 1 August 2017 at 10:41, Peter Maydell <peter.mayd...@linaro.org> wrote: > > On 1 August 2017 at 10:35, KONRAD Frederic <frederic.kon...@adacore.com> > > wrote: > >> > >> > &g

Re: [Qemu-devel] [Qemu-arm] [PATCH 09/15] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif

On Thu, Aug 03, 2017 at 03:05:17PM -0700, Richard Henderson wrote: > On 08/03/2017 08:38 AM, Edgar E. Iglesias wrote: > >> +uint32_t primask; > >> +uint32_t faultmask; > > It seems like these could be booleans? > > I was thinking the same thing

Re: [Qemu-devel] [Qemu-arm] [PATCH 8/8] target/arm: Implement new do_transaction_failed hook

On Fri, Aug 04, 2017 at 06:20:49PM +0100, Peter Maydell wrote: > Implement the new do_transaction_failed hook for ARM, which should > cause the CPU to take a prefetch abort or data abort. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Edgar E. Igl

Re: [Qemu-devel] [Qemu-arm] [PATCH 7/8] target/arm: Allow deliver_fault() caller to specify EA bit

constructing the syndrome values. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > target/arm/internals.h | 2 ++ > target/arm/op_helper.c | 10 +- > 2 files changed, 7 insertions(+

Re: [Qemu-devel] [Qemu-arm] [PATCH 6/8] target/arm: Factor out fault delivery code

Factor out the common code into a new function > deliver_fault(). I found this a bit hard to read but I think it looks OK :-) Acked-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> >

Re: [Qemu-devel] [Qemu-arm] [PATCH 5/8] hw/arm: Set ignore_memory_transaction_failures for most ARM boards

ranges with devices we don't yet handle > > New boards should not set the flag, but instead be written > like the mps2. For the Xilinx boards: Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>

Re: [Qemu-devel] [Qemu-arm] [PATCH 4/8] boards.h: Define new flag ignore_memory_transaction_failures

on memory transaction failures. Too many > of our legacy board models rely on the RAZ/WI behaviour and we > would break currently working guests when their "probe for device" > code provoked an external abort rather than a RAZ. > > Signed-off-by: Peter Maydell <peter.m

Re: [Qemu-devel] [Qemu-arm] [PATCH 3/8] cputlb: Support generating CPU exceptions on memory transaction failures

structuring and > redesign to attempt at this point. You're right but onsidering the lack of models for I caches and prefetching, I don't think that matters much... Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.

Re: [Qemu-devel] [Qemu-arm] [PATCH 2/8] cpu: Define new cpu_transaction_failed() hook

On Fri, Aug 04, 2017 at 06:20:43PM +0100, Peter Maydell wrote: > Currently we have a rather half-baked setup for allowing CPUs to > generate exceptions on accesses to invalid memory: the CPU has a > cpu_unassigned_access() hook which the memory system calls in > unassigned_mem_write() and

Re: [Qemu-devel] [Qemu-arm] [PATCH 2/8] cpu: Define new cpu_transaction_failed() hook

o_unaligned_access: Callback for unaligned access handling, if > * the target defines #ALIGNED_ONLY. > + * @do_transaction_failed: Callback for handling failed memory transactions Looks OK but I wonder if there you might want to clarify that this is a bus/slave failure and not a failure within the

Re: [Qemu-devel] [Qemu-arm] [PATCH 1/8] memory.h: Move MemTxResult type to memattrs.h

oth are used for the new-style > read_with_attrs and write_with_attrs callbacks, so memattrs.h > is a reasonable home for this rather than creating a whole > new header file for it. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.igl

Re: [Qemu-devel] [Qemu-arm] [PATCH 02/15] target/arm: Don't trap WFI/WFE for M profile

On Thu, Aug 03, 2017 at 01:28:28PM -0700, Richard Henderson wrote: > On 08/02/2017 09:43 AM, Peter Maydell wrote: > > M profile cores can never trap on WFI or WFE instructions. Check for > > M profile in check_wfx_trap() to ensure this. > > > > The existing code will do the right thing for v7M

Re: [Qemu-devel] [Qemu-arm] [PATCH 15/15] nvic: Implement "user accesses BusFault" SCS region behaviour

tinue to > act as RAZ/WI to user accesses. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > hw/intc/armv7m_nvic.c | 58 > --- > 1 file

Re: [Qemu-devel] [Qemu-arm] [PATCH 14/15] armv7m_nvic.h: Move from include/hw/arm to include/hw/intc

; Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > hw/intc/armv7m_nvic.c | 2 +- > include/hw/arm/armv7m.h| 2 +- > include/hw/{arm => intc}/armv7m_nvic.h | 0 > 3 files changed, 2 insertions(+), 2 deletions(-) > re

Re: [Qemu-devel] [Qemu-arm] [PATCH 13/15] target/arm: Create and use new function arm_v7m_is_handler_mode()

*/ > +static inline bool arm_v7m_is_handler_mode(CPUARMState *env) > +{ > +return env->v7m.exception != 0; The != 0 shouldn't be needed when you return a bool... Either way: Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > +} > + > /* Return the curre

Re: [Qemu-devel] [Qemu-arm] [PATCH 12/15] target/arm: Don't calculate lr in arm_v7m_cpu_do_interrupt() until needed

han it needs to be. > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > target/arm/helper.c | 15 --- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/targ

Re: [Qemu-devel] [Qemu-arm] [PATCH 11/15] target/arm: Make arm_cpu_dump_state() handle the M-profile XPSR

- T priv-thread > > Signed-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > target/arm/translate.c | 58 > ++ > 1 file changed, 40 insertions(+),

Re: [Qemu-devel] [Qemu-arm] [PATCH 09/15] target/arm: Don't store M profile PRIMASK and FAULTMASK in daif

On Wed, Aug 02, 2017 at 05:43:55PM +0100, Peter Maydell wrote: > We currently store the M profile CPU register state PRIMASK and > FAULTMASK in the daif field of the CPU state in its I and F > bits. This is a legacy from the original implementation, which > tried to share the cpu_exec_interrupt

Re: [Qemu-devel] [Qemu-arm] [PATCH 08/15] target/arm: Define and use XPSR bit masks

d-off-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > target/arm/cpu.h| 38 -- > target/arm/helper.c | 15 --- > 2 files changed, 36 insertions(+), 17 deletions(

Re: [Qemu-devel] [PATCH 07/15] target/arm: Fix outdated comment about exception exit

-by: Peter Maydell <peter.mayd...@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com> > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index fd8

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