Hi Cedric,
> From: Cédric Le Goater
> On 5/27/24 10:02, Jamin Lin wrote:
> > Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35
> CPU).
> >
> > AST2700 SOC and its interrupt controller are too complex to handle in
> > the common Aspeed
Hi Cedric,
> From: Cédric Le Goater
> Subject: Re: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
>
>
> Hello Jamin,
> > I refer to versal_create_apu_gic function,
> https://github.com/qemu/qemu/blob/master/hw/arm/xlnx-versal.c#L67
> > and updated aspeed_soc_ast2700_gic as following.
> > If
Hi Cedric,
> From: Cédric Le Goater
> Subject: Re: [PATCH v4 12/16] aspeed/soc: Add AST2700 support
>
> On 5/27/24 10:02, Jamin Lin wrote:
> > Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35
> CPU).
> >
> > AST2700 SOC and its int
Hi Cedric,
> From: Cédric Le Goater
> On 5/30/24 09:42, Jamin Lin wrote:
> > Hi Cedric,
> >> From: Cédric Le Goater > Hello Jamin
> >>
> >> On 5/27/24 10:02, Jamin Lin wrote:
> >>> AST2700 dram size calculation is not back compatible AST2600.
Hi Cedric,
> From: Cédric Le Goater >
> Hello Jamin
>
> On 5/27/24 10:02, Jamin Lin wrote:
> > AST2700 dram size calculation is not back compatible AST2600.
> > According to the DDR capacity hardware behavior, if users write the
> > data to address which is be
Hi Cedric,
> From: Cédric Le Goater
> On 5/28/24 12:02, Jamin Lin wrote:
> > Hi Cedric,
> >
> >> -Original Message-
> >> From: Cédric Le Goater
> >> Sent: Tuesday, May 28, 2024 5:56 PM
> >> To: Jamin Lin ; Peter Maydell
> >&g
Hi Cedric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, May 28, 2024 5:56 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ;
> Cleber
> Rosa ; Philippe Mathieu-Daudé ;
> Wainer dos Santos Mosche
Hi Cedric,
> From: Cédric Le Goater
> [ ... ]
>
> >> I don't think this is necessary to do so now. Possibly, increase the
> >> version number in the vmstate when resending a v5.
> >>
> > If I understand your request, do you mean to change as following in this
> patch?
> >
> > static const
Hi Cedric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, May 28, 2024 2:34 PM
> To: Jamin Lin ; Philippe Mathieu-Daudé
> ; Peter Maydell ; Andrew
> Jeffery ; Joel Stanley ;
> Alistair Francis ; Cleber Rosa ;
> Wainer dos Santos Moschetta
Hi Philippe,
> Hi Jamin,
>
> On 27/5/24 10:02, Jamin Lin wrote:
> > AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM
> Side
> > Address High Part(0x7C)"
> > register to support 64 bits dma dram address.
> > Add helper routines
Hi Cedric,
> On 5/27/24 10:02, Jamin Lin wrote:
> > AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM
> Side
> > Address High Part(0x7C)"
> > register to support 64 bits dma dram address.
> > Add helper routines functions to comput
P_UINT64("dram-base", AspeedSMCState, dram_base, 0),
> DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
> TYPE_MEMORY_REGION, MemoryRegion *),
> DEFINE_PROP_END_OF_LIST(),
> --
> 2.45.1
Reviewed-by: Jamin Lin
Thanks-Jamin
Hi Philippe, Cedric
> On 27/5/24 13:18, Cédric Le Goater wrote:
> > On 5/27/24 12:24, Philippe Mathieu-Daudé wrote:
> >> Hi Jamin,
> >>
> >> On 27/5/24 10:02, Jamin Lin wrote:
> >>> The SDRAM memory controller(DRAMC) controls the access to externa
GitHub release
repository :
https://github.com/AspeedTech-BMC/openbmc/releases/
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
tests/avocado/machine_aspeed.py | 62 +
1 file changed, 62 insertions(+)
diff --git a/tests
AST2700 wdt controller is similiar to AST2600's wdt, but
the AST2700 has 8 watchdogs, and they each have 0x80 of registers.
Introduce ast2700 object class and increase the number of regs(offset) of
ast2700 model.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
of SCU is defined in SCU280[25:23].
Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function
and trace-event for AST2700 SCU and SCUIO.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_scu.c | 306
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/ssi/aspeed_smc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 6e1a84c197..8a8d77b480 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi
Fix coding style issues from checkpatch.pl
Test command:
scripts/checkpatch.pl --no-tree -f hw/misc/aspeed_sdmc.c
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_sdmc.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff
Add AST2700 Evaluation board and its boot command.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
docs/system/arm/aspeed.rst | 39 ++
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/docs/system/arm
+--+
+>+17 |
UART12 | |
+->18 |
| |
| |
| |
+---+
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c | 355 ++
hw/intc/meson.build |
These macros are no longer used for ASPEED SOCs, so removes them.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_sdmc.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index
-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_sdmc.c | 190 +-
include/hw/misc/aspeed_sdmc.h | 5 +-
2 files changed, 193 insertions(+), 2 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 873d67c592..69a34903db
: Troy Lee
Signed-off-by: Jamin Lin
---
hw/ssi/aspeed_smc.c | 52 +++--
hw/ssi/trace-events | 2 +-
include/hw/ssi/aspeed_smc.h | 1 +
3 files changed, 46 insertions(+), 9 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index
d
memory I/O whose address range is from max_ram_size - ram_size to max_ram_size
and its read/write handler to emulate DDR capacity hardware behavior.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 94 -
include/hw/arm/
of GIC device.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 563
hw/arm/meson.build | 1 +
include/hw/arm/aspeed_soc.h | 26 +-
3 files changed, 588 insertions(+), 2 deletions(-)
create mode 100644 hw/arm
parameter to store
the start length, add helper routines function to compute the dma length
and update DMA_LENGTH mask to "1FF" to support dma 1 byte
length unit for AST2600 and AST1030.
Currently, only supports dma length 4 bytes aligned.
Signed-off-by: Troy Lee
Signed-off-by: Ja
loader,addr=0x43000,cpu-num=2\
-device loader,addr=0x43000,cpu-num=3\
-smp 4\
-drive file=${IMGDIR}/image-bmc,format=raw,if=mtd\
-serial mon:stdio\
-snapshot
Jamin Lin (16):
aspeed/wdt: Add AST2700 support
aspeed/sli: Add AST2700 support
aspeed/sdmc: remove redundant macros
aspeed
-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/ssi/aspeed_smc.c | 222 +++-
1 file changed, 220 insertions(+), 2 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index df0c63469c..b4006c8339 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi
architectures
at the same machine. Therefore, qemu will only support
to emulate CPU(cortex-a35) side for ast2700
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 32
1 file changed, 32 insertions(+)
diff --git a/hw/arm
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce dummy AST2700 SLI and SLIIO models.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_sli.c
> Hello Jamin,
>
>
> [ ... ]
>
> >> See my aspeed-9.1 branch, I did some changes, mostly in the last patch.
> >>
> >> * aspeed_smc_dma_len()
> >>
> >> - can use QEMU_ALIGN_UP(). simpler.
> >>
> >> * aspeed_smc_dma_rw():
> >>
> >> - dram_addr -> dma_dram_offset
> >> - There is no
| |
+---+
> Hi Cedric,
>
> > Hello Jamin
> >
> > On 4/16/24 11:18, Jamin Lin wrote:
> > > AST2700 interrupt controller(INTC) provides hardware interrupt
> > > interfaces to interrupt of processors PSP, SSP and
Hi Cedric,
> Hello Jamin
>
> On 4/16/24 11:18, Jamin Lin wrote:
> > AST2700 interrupt controller(INTC) provides hardware interrupt
> > interfaces to interrupt of processors PSP, SSP and TSP. In INTC, each
> > interrupt of INT 128 to INT136 combines 32 interrup
Hi Cedric,
>
> Hello Jamin
>
> On 5/15/24 11:01, Jamin Lin wrote:
> > Hi Cedric,
> >
> > Sorry reply you late.
> >> Hello Jamin,
> >>
> >> To handle the DMA DRAM Side Address High register, we should
> >> reintroduce an
Hi Cerdric,
> On 4/19/24 09:58, Jamin Lin wrote:
> > Hi Cedric,
> >> On 4/16/24 11:18, Jamin Lin wrote:
> >>> Initial definitions for a simple machine using an AST2700 SOC
> >>> (Cortex-a35
> >> CPU).
> >>>
> >
ect-failure", AspeedSMCState, inject_failure,
> false),
> +DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0),
> DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr,
>TYPE_MEMORY_REGION, MemoryRegion *),
> DEFINE_PROP_LINK(&
Hi Cedric,
Sorry reply you late.
> Hello Jamin,
>
> On 4/30/24 09:56, Jamin Lin wrote:
> > Hi Cedric,
> >
> >> -Original Message-
> >> From: Cédric Le Goater
> >> Sent: Tuesday, April 30, 2024 3:26 PM
> >> To: Jamin Lin
Hi Cedric,
Sorry reply you late.
> On 4/30/24 10:51, Jamin Lin wrote:
> > Hi Cedric,
> >> On 4/19/24 15:41, Cédric Le Goater wrote:
> >>> On 4/16/24 11:18, Jamin Lin wrote:
> >>>> DMA length is from 1 byte to 32MB for AST2600 and AST10x0 and DMA
>
Hi Cedric,
> On 4/19/24 15:41, Cédric Le Goater wrote:
> > On 4/16/24 11:18, Jamin Lin wrote:
> >> DMA length is from 1 byte to 32MB for AST2600 and AST10x0 and DMA
> >> length is from 4 bytes to 32MB for AST2500.
> >>
> >> In other words, if &qu
Hi Cedric,
> -Original Message-
> From: Cédric Le Goater
> Sent: Tuesday, April 30, 2024 3:26 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ;
> Cleber
> Rosa ; Philippe Mathieu-Daudé ;
> Wainer dos Santos Mosche
Hi Cedric,
> On 4/16/24 11:18, Jamin Lin wrote:
> > Initial definitions for a simple machine using an AST2700 SOC (Cortex-a35
> CPU).
> >
> > AST2700 SOC and its interrupt controller are too complex to handle in
> > the common Aspeed SoC framework. We
Hi Cedric,
>
> Hello Jamin,
>
> On 4/16/24 11:18, Jamin Lin wrote:
> > AST2700 support the maximum dram size is 8GiB and has a "DMA DRAM
> Side
> > Address High Part(0x7C)"
> > register to support 64 bits dma dram address.
> > Add helper routin
Add AST2700 Evaluation board and its boot command.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
docs/system/arm/aspeed.rst | 39 ++
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst
, the GIC irq
callback function is called and set irq to CPUs and
CPUs execute Interrupt Service Routine (ISR).
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c | 269 ++
hw/intc/meson.build | 1 +
hw/intc/trace-events
architectures
at the same machine. Therefore, qemu will only support
to emulate CPU(cortex-a35) side for ast2700
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/arm/aspeed.c | 32
1 file changed, 32 insertions(+)
diff --git a/hw/arm
release
repository :
https://github.com/AspeedTech-BMC/openbmc/releases/
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
tests/avocado/machine_aspeed.py | 62 +
1 file changed, 62 insertions(+)
diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado
These macros are no longer used for ASPEED SOCs, so removes them.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sdmc.c | 15 ---
1 file changed, 15 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 64cd1a81dc..74279bbe8e 100644
AST2700 wdt controller is similiar to AST2600's wdt, but
the AST2700 has 8 watchdogs, and they each have 0x80 of registers.
Introduce ast2700 object class and increase the number of regs(offset) of
ast2700 model.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
d
memory I/O whose address range is from max_ram_size - ram_size to max_ram_size
and its read/write handler to emulate DDR capacity hardware behavior.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 94 -
include/hw/arm/
parameter to store
the start length, add helper routines function to compute the dma length
and update DMA_LENGTH mask to "1FF" to fix dma moving
incorrect data length issue.
Currently, only supports dma length 4 bytes aligned.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
-by: Jamin Lin
---
hw/ssi/aspeed_smc.c | 222 +++-
1 file changed, 220 insertions(+), 2 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index a67cac3d0f..e768e5463c 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -185,7 +185,7
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce dummy AST2700 SLI and SLIIO models.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sli.c | 178
of GIC device.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 554
hw/arm/meson.build | 1 +
include/hw/arm/aspeed_soc.h | 26 +-
3 files changed, 579 insertions(+), 2 deletions(-)
create mode 100644 hw/arm
-by: Jamin Lin
---
hw/misc/aspeed_sdmc.c | 190 +-
include/hw/misc/aspeed_sdmc.h | 5 +-
2 files changed, 193 insertions(+), 2 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 873d67c592..69a34903db 100644
--- a/hw/misc/aspeed_sdmc.c
of SCU is defined in SCU280[25:23].
Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function
and trace-event for AST2700 SCU and SCUIO.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
---
hw/misc/aspeed_scu.c | 306
: Troy Lee
Signed-off-by: Jamin Lin
---
hw/ssi/aspeed_smc.c | 66 +++--
hw/ssi/trace-events | 2 +-
2 files changed, 59 insertions(+), 9 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 71abc7a2d8..a67cac3d0f 100644
--
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/ssi/aspeed_smc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 6e1a84c197..8a8d77b480 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -1448,7 +1448,7
Fix coding style issues from checkpatch.pl
Test command:
scripts/checkpatch.pl --no-tree -f hw/misc/aspeed_sdmc.c
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sdmc.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/hw/misc/aspeed_sdmc.c b
,addr=0x43000,cpu-num=3\
-smp 4\
-drive file=${IMGDIR}/image-bmc,format=raw,if=mtd\
-serial mon:stdio\
-snapshot
Jamin Lin (16):
aspeed/wdt: Add AST2700 support
aspeed/sli: Add AST2700 support
aspeed/sdmc: remove redundant macros
aspeed/sdmc: fix coding style
aspeed/sdmc: Add
> On 3/4/24 10:29, Jamin Lin wrote:
> > AST2700 fmc/spi controller's address decoding unit is 64KB and only
> > bits [31:16] are used for decoding. Introduce seg_to_reg and
> > reg_to_seg handlers for ast2700 fmc/spi controller.
> > In addition, adds ast2700 fmc, spi0
> >>
> > Hi Cedrice,
> >
> > Thanks for review and sorry reply you late.
> >
> >> On 3/4/24 10:29, Jamin Lin wrote:
> >>> The SDRAM memory controller(DRAMC) controls the access to external
> >>> DDR4 and DDR5 SDRAM and pow
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, March 4, 2024 11:50 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, March 4, 2024 10:47 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, March 7, 2024 6:43 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Ta
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, March 4, 2024 11:40 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Thursday, February 29, 2024 5:38 PM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Andrew Jeffery
> ; Joel Stanley ; Alistair
> Francis ; open list:ASPEED BMCs
> ; open list:All patches CC here
&g
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, March 4, 2024 11:54 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, March 4, 2024 10:36 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
> -Original Message-
> From: Cédric Le Goater
> Sent: Monday, March 4, 2024 10:32 PM
> To: Jamin Lin ; Peter Maydell
> ; Andrew Jeffery ;
> Joel Stanley ; Alistair Francis ; open
> list:ASPEED BMCs ; open list:All patches CC here
>
> Cc: Troy Lee ; Yunlin Tang
> -Original Message-
> From: Cédric Le Goater
> Sent: Thursday, February 29, 2024 4:32 PM
> To: Jamin Lin ; peter.mayd...@linaro.org;
> and...@codeconstruct.com.au; j...@jms.id.au; qemu-...@nongnu.org;
> qemu-devel@nongnu.org
> Cc: Troy Lee ; Yunlin Tang
>
>
into login prompt.
It is a temporary solution.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c| 135 +++
hw/intc/meson.build | 1 +
include/hw/intc/aspeed_vic.h | 29
3 files changed, 165 insertions(+)
create mode
ned-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/ssi/aspeed_smc.c | 326 +---
hw/ssi/trace-events | 2 +-
include/hw/ssi/aspeed_smc.h | 1 +
3 files changed, 309 insertions(+), 20 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_sm
keyboard.
Jamin Lin (9):
aspeed/wdt: Add AST2700 support
aspeed/sli: Add AST2700 support
aspeed/sdmc: Add AST2700 support
aspeed/smc: Add AST2700 support
aspeed/scu: Add AST2700 support
aspeed/intc: Add AST2700 support
aspeed/soc: Add AST2700 support
aspeed: Add an AST2700 eval board
aspeed_2700_sdmc and class with read/write operation and
reset handlers.
Define DRAMC necessary protected registers and
unprotected registers for AST2700 and increase
the register set to 0x1000.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sdmc.c | 215
of SCU is defined in SCU280[25:23].
Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function
and trace-event for AST2700 SCU and SCUIO.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_scu.c | 306 ++-
hw/misc/trace-events
into login prompt.
It is a temporary solution.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c| 135 +++
hw/intc/meson.build | 1 +
include/hw/intc/aspeed_vic.h | 29
3 files changed, 165 insertions(+)
create mode
d
memory I/O whose address range is from max_ram_size - ram_size to max_ram_size
and its read/write handler to emulate DDR capacity hardware behavior.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 94 -
include/hw/arm/
keyboard to trigger GICINT132 interrupt
until AST2700 boot into login prompt. It is a temporary solution.
If users encounter boot stck and no booting log,
please type any key from keyboard.
Jamin Lin (9):
aspeed/wdt: Add AST2700 support
aspeed/sli: Add AST2700 support
aspeed/sdmc: Add AST2700
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce new ast2700_sli and ast2700_sliio class
with instance_init and realize handlers.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc
AST2700 wdt controller is similiar to AST2600's wdt, but
the AST2700 has 8 watchdogs, and they each have a 0x80 of registers.
Introduce ast2700 object class and increse the number of regs(offset) of
ast2700 model.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/watchdog/wdt_aspeed.c
aspeed_2700_sdmc and class with read/write operation and
reset handlers.
Define DRAMC necessary protected registers and
unprotected registers for AST2700 and increase
the register set to 0x1000.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sdmc.c | 215
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Friday, March 1, 2024 11:49 PM
> To: Cédric Le Goater ; qemu-...@nongnu.org;
> qemu-devel@nongnu.org
> Cc: Jamin Lin ; Troy Lee
>
> Subject: Re: [PULL 2/2] aspeed: fix hardcode boot address 0
>
> H
> -Original Message-
> From: Philippe Mathieu-Daudé
> Sent: Thursday, February 29, 2024 5:17 PM
> To: Jamin Lin ; Cédric Le Goater ;
> Peter Maydell ; Andrew Jeffery
> ; Joel Stanley ; Alistair
> Francis ; open list:ASPEED BMCs
> ; open list:All patches CC here
&g
architectures
at the same machine. Therefore, qemu will only support
to emulate CPU(cortex-a35) side for ast2700
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/arm/aspeed.c | 32
1 file changed, 32 insertions(+)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
of SCU is defined in SCU280[25:23].
Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function
and trace-event for AST2700 SCU and SCUIO.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_scu.c | 306 ++-
hw/misc/trace-events
rs/ram/aspeed/
sdram_ast2700.c
It seems we should create a new function instead of aspeed_soc_dram_init
to support AST2700.
https://github.com/qemu/qemu/blob/master/hw/arm/aspeed_soc_common.c
Jamin Lin (8):
aspeed/wdt: Add AST2700 support
aspeed/sli: Add AST2700 support
aspeed/sdmc: Add AST2700
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce new ast2700_sli and ast2700_sliio class
with instance_init and realize handlers.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc
into login prompt.
It is a temporary solution.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c| 135 +++
hw/intc/meson.build | 1 +
include/hw/intc/aspeed_vic.h | 29
3 files changed, 165 insertions(+)
create mode
> -Original Message-
> From: Jamin Lin
> Sent: Thursday, February 29, 2024 3:53 PM
> To: Jamin Lin ; c...@kaod.org;
> peter.mayd...@linaro.org; and...@codeconstruct.com.au; j...@jms.id.au;
> qemu-...@nongnu.org; qemu-devel@nongnu.org
> Cc: Troy Lee ; Yunlin Tang
>
> -Original Message-
> From: Jamin Lin
> Sent: Thursday, February 29, 2024 3:43 PM
> To: c...@kaod.org; peter.mayd...@linaro.org; and...@codeconstruct.com.au;
> j...@jms.id.au; qemu-...@nongnu.org; qemu-devel@nongnu.org
> Cc: Troy Lee ; Jamin Lin
> ; Yunlin Tang
>
AST2700 wdt controller is similiar to AST2600's wdt, but
the AST2700 has 8 watchdogs, and they each have a 0x80 of registers.
Introduce ast2700 object class and increse the number of regs(offset) of
ast2700 model.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/watchdog/wdt_aspeed.c
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce new ast2700_sli and ast2700_sliio class
with instance_init and realize handlers.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc
of SCU is defined in SCU280[25:23].
Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function
and trace-event for AST2700 SCU and SCUIO.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_scu.c | 306 ++-
hw/misc/trace-events
into login prompt.
It is a temporary solution.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c| 135 +++
hw/intc/meson.build | 1 +
include/hw/intc/aspeed_vic.h | 29
3 files changed, 165 insertions(+)
create mode
AST2700 SLI engine is designed to accelerate the
throughput between cross-die connections.
It have CPU_SLI at CPU die and IO_SLI at IO die.
Introduce new ast2700_sli and ast2700_sliio class
with instance_init and realize handlers.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc
-by: Jamin Lin
---
hw/arm/aspeed_ast27x0.c | 462
hw/arm/meson.build | 1 +
include/hw/arm/aspeed_soc.h | 26 +-
3 files changed, 486 insertions(+), 3 deletions(-)
create mode 100644 hw/arm/aspeed_ast27x0.c
diff --git a/hw/arm/aspeed_ast27x0.c b/hw
rs/ram/aspeed/
sdram_ast2700.c
It seems we should create a new function instead of aspeed_soc_dram_init
to support AST2700.
https://github.com/qemu/qemu/blob/master/hw/arm/aspeed_soc_common.c
Jamin Lin (8):
aspeed/wdt: Add AST2700 support
aspeed/sli: Add AST2700 support
aspeed/sdmc: Add AST2700
aspeed_2700_sdmc and class with read/write operation and
reset handlers.
Define DRAMC necessary protected registers and
unprotected registers for AST2700 and increase
the register set to 0x1000.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_sdmc.c | 215
into login prompt.
It is a temporary solution.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/intc/aspeed_intc.c| 135 +++
hw/intc/meson.build | 1 +
include/hw/intc/aspeed_vic.h | 29
3 files changed, 165 insertions(+)
create mode
of SCU is defined in SCU280[25:23].
Both of them are not compatible AST2600 SOCs, adds a get_apb_freq function
and trace-event for AST2700 SCU and SCUIO.
Signed-off-by: Troy Lee
Signed-off-by: Jamin Lin
---
hw/misc/aspeed_scu.c | 306 ++-
hw/misc/trace-events
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