create_sq() was getting its
limit from when processing the host command, and sure enough it's
directly from the register field.
Reviewed-by: Keith Busch
did not fix little-endian guests
> on big-endian hosts. Fix this.
>
> Solves issue #1765.
>
> Fixes: 3f7fe8de3d49 ("hw/nvme: Implement shadow doorbell buffer support")
> Cc: qemu-sta...@nongnu.org
> Reported-by: Thomas Huth
> Signed-off-by: Klaus Jensen
Looks good!
Reviewed-by: Keith Busch
hile (nlb) {
> +if (nlb < ru->ruamw) {
> +ru->ruamw -= nlb;
> +break;
> +}
> +
> +nlb -= ru->ruamw;
> +//trace_pci_nvme_fdp_ruh_change(ruh->rgid, ruh->ruhid);
Please use the trace points if you find them useful, otherwise just delete
them instead of committing commented out code.
Beyond that, looks good! For the series:
Reviewed-by: Keith Busch
On Thu, Feb 16, 2023 at 05:48:06PM +0100, Jesper Devantier wrote:
> +static bool nvme_ns_init_fdp(NvmeNamespace *ns, Error **errp)
> +{
> +NvmeEnduranceGroup *endgrp = ns->endgrp;
> +NvmeRuHandle *ruh;
> +uint8_t lbafi = NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas);
> +unsigned int
This mostly looks fine. I need to clarify some spec decisions, though.
By default, FDP feature is disabled: "The default value of this Feature shall
be 0h." You can't change the value as long as namespaces exist within the
group, so FDP requires NS Mgmt be supported if you're going to enable it.
On Thu, Feb 16, 2023 at 06:35:27PM +0100, Klaus Jensen wrote:
> On Thu, Feb 16, 2023, at 18:23, Keith Busch wrote:
> > On Thu, Feb 16, 2023 at 05:48:05PM +0100, Jesper Devantier wrote:
> >> +enum NvmeDirective {
> >> +NVME_DIRECTIVE_SUPPORTED = 0x0,
> >>
On Thu, Feb 16, 2023 at 05:48:05PM +0100, Jesper Devantier wrote:
> +enum NvmeDirective {
> +NVME_DIRECTIVE_SUPPORTED = 0x0,
> +NVME_DIRECTIVE_ENABLED = 0x1,
> +};
What's this?
On Thu, Jan 19, 2023 at 01:10:57PM +1000, Alistair Francis wrote:
> On Thu, Jan 19, 2023 at 12:44 PM Keith Busch wrote:
> >
> > Further up, it says the "interrupt gateway" is responsible for
> > forwarding new interrupt requests while the level remains asserte
On Thu, Jan 19, 2023 at 10:41:42AM +1000, Alistair Francis wrote:
> On Thu, Jan 19, 2023 at 9:07 AM Keith Busch wrote:
> > ---
> > diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> > index c2dfacf028..f8f7af08dc 100644
> > --- a/hw/intc/sifive_plic.c
>
On Wed, Jan 18, 2023 at 09:33:05AM -0700, Keith Busch wrote:
> On Wed, Jan 18, 2023 at 03:04:06PM +, Peter Maydell wrote:
> > On Tue, 17 Jan 2023 at 19:21, Guenter Roeck wrote:
> > > Anyway - any idea what to do to help figuring out what is happening ?
> > >
Klaus,
This isn't going to help your issue, but there are at least two legacy
irq bugs in the nvme qemu implementation.
1. The admin queue breaks if start with legacy and later initialize
msix.
2. The legacy vector is shared among all queues, but it's being
deasserted when the first queue's
On Wed, Jan 18, 2023 at 03:04:06PM +, Peter Maydell wrote:
> On Tue, 17 Jan 2023 at 19:21, Guenter Roeck wrote:
> > Anyway - any idea what to do to help figuring out what is happening ?
> > Add tracing support to pci interrupt handling, maybe ?
>
> For intermittent bugs, I like recording the
On Thu, Jan 12, 2023 at 02:10:51PM +0100, Klaus Jensen wrote:
> Hi all (linux-nvme, qemu-devel, maintainers),
>
> On QEMU riscv64, which does not use MSI/MSI-X and thus relies on
> pin-based interrupts, I'm seeing occasional completion timeouts, i.e.
>
> nvme nvme0: I/O 333 QID 1 timeout,
On Mon, Jan 16, 2023 at 10:14:07PM +0100, Klaus Jensen wrote:
> I noticed that the Linux driver does not use the INTMS/INTMC registers
> to mask interrupts on the controller while processing CQEs. While not
> required by the spec, it is *recommended* in setups not using MSI-X to
> reduce the risk
On Fri, Jan 13, 2023 at 12:32:29PM +, Peter Maydell wrote:
> On Fri, 13 Jan 2023 at 08:55, Klaus Jensen wrote:
> >
> > +CC qemu pci maintainers
> >
> > Michael, Marcel,
> >
> > Do you have any comments on this thread? As you can see one solution is
> > to simply deassert prior to asserting,
On Thu, Jan 12, 2023 at 06:45:55PM +0100, Klaus Jensen wrote:
> On Jan 12 09:34, Keith Busch wrote:
> > On Thu, Jan 12, 2023 at 02:10:51PM +0100, Klaus Jensen wrote:
> > >
> > > The pin-based interrupt logic in hw/nvme seems sound enough to me, so I
> > > am w
On Thu, Jan 12, 2023 at 06:45:55PM +0100, Klaus Jensen wrote:
> On Jan 12 09:34, Keith Busch wrote:
> > On Thu, Jan 12, 2023 at 02:10:51PM +0100, Klaus Jensen wrote:
> > >
> > > The pin-based interrupt logic in hw/nvme seems sound enough to me, so I
> > > am w
On Thu, Jan 12, 2023 at 02:10:51PM +0100, Klaus Jensen wrote:
>
> The pin-based interrupt logic in hw/nvme seems sound enough to me, so I
> am wondering if there is something going on with the kernel driver (but
> I certainly do not rule out that hw/nvme is at fault here, since
> pin-based
On Wed, Dec 28, 2022 at 01:41:40PM -0600, Jonathan Derrick wrote:
> +static uint16_t nvme_ns_mgmt(NvmeCtrl *n, NvmeRequest *req)
> +{
> +NvmeCtrl *n_p = NULL; /* primary controller */
> +NvmeIdCtrl *id = >id_ctrl;
> +NvmeNamespace *ns;
> +NvmeIdNsMgmt id_ns = {};
> +uint8_t
rted by Guenter.
>
> Adding the missing update to the cq eventidx fixes the issue.
>
> Fixes: 3f7fe8de3d49 ("hw/nvme: Implement shadow doorbell buffer support")
> Cc: qemu-sta...@nongnu.org
> Cc: qemu-ri...@nongnu.org
> Reported-by: Guenter Roeck
> Signed-off-by: Klaus Jensen
Looks good.
Reviewed-by: Keith Busch
mu-sta...@nongnu.org
> Reported-by: Guenter Roeck
> Signed-off-by: Klaus Jensen
Looks good.
Reviewed-by: Keith Busch
ad respectively).
>
> Reviewed-by: Philippe Mathieu-Daudé
> Signed-off-by: Klaus Jensen
Looks good.
Reviewed-by: Keith Busch
When the request times out, the kernel should be printing the command ID.
What does that say? The driver thinks the 0 is invalid, so I'm just curious
what value it's expecting.
On Thu, Dec 8, 2022, 8:13 PM Guenter Roeck wrote:
> On Thu, Dec 08, 2022 at 10:47:42AM -0800, Guenter Roeck wrote:
> >
On Sun, Dec 04, 2022 at 11:06:13AM -0500, Stefan Hajnoczi wrote:
> On Thu, 1 Dec 2022 at 11:50, Klaus Jensen wrote:
> >
> > From: Klaus Jensen
> >
> > Hi,
> >
> > The following changes since commit c4ffd91aba1c3d878e99a3e7ba8aad4826728ece:
> >
> > Update VERSION for v7.2.0-rc3 (2022-11-29
ember from the above struct with this
patch.
Otherwise looks good.
Reviewed-by: Keith Busch
On Thu, Oct 27, 2022 at 01:00:45PM -0500, Jonathan Derrick wrote:
> +Parameters:
> +
> +``auto-ns-path=``
> + If specified indicates a support for dynamic management of nvme namespaces
> + by means of nvme create-ns command. This path points
> + to the storage area for backend images must
to bottom halfs and instead of
> calling nvme_post_cqes() immediately (causing an interrupt per cqe), we
> defer the call.
Nice change, looks good! Timers never did seem to be the best fit for
this.
Reviewed-by: Keith Busch
On Sun, Oct 02, 2022 at 11:59:42AM +0300, Maxim Levitsky wrote:
> On Thu, 2022-09-29 at 19:35 +0200, Paolo Bonzini wrote:
> > On 9/29/22 18:39, Christoph Hellwig wrote:
> > > On Thu, Sep 29, 2022 at 10:37:22AM -0600, Keith Busch wrote:
> > > > > I am aware, and I'
From: Keith Busch
Changes from v2:
Split the patch so that the function move is separate from the
functional change. This makes it immediately obvious what criteria is
changing. (Kevin Wolf)
Added received Tested-by tag in the changelog.
Keith Busch (2):
block: move
From: Keith Busch
An iov length needs to be aligned to the logical block size, which may
be larger than the memory alignment.
Tested-by: Jens Axboe
Signed-off-by: Keith Busch
---
block/file-posix.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/block/file-posix.c b
From: Keith Busch
There is only user of bdrv_qiov_is_aligned(), so move the alignment
function to there and make it static.
Signed-off-by: Keith Busch
---
block/file-posix.c | 21 +
block/io.c | 21 -
include/block/block-io.h | 1
On Thu, Sep 29, 2022 at 07:59:50PM +0200, Kevin Wolf wrote:
> Am 29.09.2022 um 18:09 hat Keith Busch geschrieben:
> > On Fri, Sep 23, 2022 at 08:34:51AM -0700, Keith Busch wrote:
> > >
> > > An iov length needs to be aligned to the logical block size, which may
>
I am aware, and I've submitted the fix to qemu here:
https://lists.nongnu.org/archive/html/qemu-block/2022-09/msg00398.html
On Thu, Sep 29, 2022 at 07:16:29PM +0300, Maxim Levitsky wrote:
> On Thu, 2022-09-29 at 09:48 -0600, Keith Busch wrote:
> > I am aware, and I've submitted the fix to qemu here:
> >
> > https://lists.nongnu.org/archive/html/qemu-block/2022-09/msg00398.html
> >
>
On Fri, Sep 23, 2022 at 08:34:51AM -0700, Keith Busch wrote:
>
> An iov length needs to be aligned to the logical block size, which may
> be larger than the memory alignment. And since this is only used with
> file-posix backing storage, move the alignment function to there, where
On Fri, Aug 26, 2022 at 11:12:04PM +0800, Jinhao Fan wrote:
> Use KVM's irqfd to send interrupts when possible. This approach is
> thread safe. Moreover, it does not have the inter-thread communication
> overhead of plain event notifiers since handler callback are called
> in the same system call
On Fri, Aug 26, 2022 at 05:45:21PM +0200, Klaus Jensen wrote:
> On Aug 26 09:34, Keith Busch wrote:
> > On Fri, Aug 26, 2022 at 11:12:04PM +0800, Jinhao Fan wrote:
> > > Use KVM's irqfd to send interrupts when possible. This approach is
> > > thread safe. Moreover,
On Wed, Aug 10, 2022 at 12:48:53AM +0800, 樊金昊 wrote:
>> The driver will create the cq with an allocated vector, but it's not
>> activated
>> until after the driver wires it up to a handler. I think that's what you're
>> observing with the incomplete MSIx table entry on creation.
>
> Also, I'm
On Mon, Aug 08, 2022 at 10:23:03AM +0800, Jinhao Fan wrote:
> at 12:35 PM, Jinhao Fan wrote:
>
> > static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *cq)
> > {
> > if (cq->irq_enabled) {
> > if (msix_enabled(&(n->parent_obj))) {
> > +/* Initialize CQ irqfd */
> > +
On Wed, Aug 03, 2022 at 09:46:05AM +0800, Jinhao Fan wrote:
> at 4:54 PM, Klaus Jensen wrote:
>
> > I am unsure if the compiler will transform that division into the shift
> > if it can infer that the divisor is a power of two (it most likely
> > will be able to).
> >
> > But I see no reason to
On Thu, Jul 28, 2022 at 10:25:19AM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> A set of fixes/changes to the ioeventfd support.
Series looks good.
Reviewed-by: Keith Busch
On Tue, Jul 26, 2022 at 11:32:57PM +0800, Jinhao Fan wrote:
> at 10:45 PM, Keith Busch wrote:
>
> > On Tue, Jul 26, 2022 at 04:55:54PM +0800, Jinhao Fan wrote:
> >> Hi Klaus and Keith,
> >>
> >> I just added support for interrupt masking. How can I test i
On Tue, Jul 26, 2022 at 04:55:54PM +0800, Jinhao Fan wrote:
>
> Hi Klaus and Keith,
>
> I just added support for interrupt masking. How can I test interrupt
> masking?
Are you asking about MSI masking? I don't think any drivers are using the
feature, so you'd need to modify one to test it. I
On Wed, Jul 13, 2022 at 09:11:41PM +0200, Mauricio Sandt wrote:
> On 13/07/2022 20:48, Keith Busch wrote:
> > I guess I'm missing the bigger picture here. You are supposed to be able to
> > retrieve these fields with ioctl's, so not sure what this has to do with
> > malware.
On Wed, Jul 13, 2022 at 08:06:26PM +0200, Mauricio Sandt wrote:
> My specific use case that required this patch is a piece of malware that used
> several IOCTLs to read model, firmware, and nqn from the NVMe attached to the
> VM. Modifying that info at the hypervisor level was a much better
On Sun, Jun 12, 2022 at 12:35:09AM +0200, Mauricio Sandt wrote:
> This small patch is the result of some recent malware research I did
> in a QEMU VM. The malware used multiple ways of querying info from
> the VM disk and I needed a clean way to change those values from the
> hypervisor.
>
> I
On Tue, Jul 05, 2022 at 07:11:36PM +0200, Klaus Jensen wrote:
> On Jul 5 22:24, Jinhao Fan wrote:
> > @@ -1374,7 +1374,14 @@ static void nvme_enqueue_req_completion(NvmeCQueue
> > *cq, NvmeRequest *req)
> >
> > QTAILQ_REMOVE(>sq->out_req_list, req, entry);
> >
On Thu, Jun 30, 2022 at 11:22:31AM +0800, Jinhao Fan wrote:
> +static int nvme_init_sq_ioeventfd(NvmeSQueue *sq)
> +{
> +NvmeCtrl *n = sq->ctrl;
> +uint16_t offset = sq->sqid << 3;
> +int ret;
> +
> +ret = event_notifier_init(>notifier, 0);
> +if (ret < 0) {
> +return
On Wed, Jun 29, 2022 at 05:04:25PM +0800, Jinhao Fan wrote:
> Ping~
>
> > @@ -4271,6 +4343,11 @@ static void nvme_init_sq(NvmeSQueue *sq, NvmeCtrl
> > *n, uint64_t dma_addr,
> > if (n->dbbuf_enabled) {
> > sq->db_addr = n->dbbuf_dbs + (sqid << 3);
> > sq->ei_addr =
On Thu, Jun 16, 2022 at 08:34:07PM +0800, Jinhao Fan wrote:
> }
> sq->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, nvme_process_sq, sq);
>
> +if (n->dbbuf_enabled) {
> +sq->db_addr = n->dbbuf_dbs + (sqid << 3);
> +sq->ei_addr = n->dbbuf_eis + (sqid << 3);
> +}
> +
>
ry to being greater than that value. Therefore, the number of MMIO's
> on the doorbell registers is greatly reduced.
Looks good to me, and passes my sanity tests.
Reviewed-by: Keith Busch
On Thu, Jun 16, 2022 at 12:42:49PM +0200, Klaus Jensen wrote:
> On Jun 8 03:28, Niklas Cassel via wrote:
> > Hello there,
> >
> > considering that Linux v5.19-rc1 is out which includes support for
> > NVMe TP4084:
> >
On Tue, Jun 14, 2022 at 03:24:37PM +0800, Jinhao Fan wrote:
> > On Jun 14, 2022, at 5:15 AM, Keith Busch wrote:
> > @@ -6538,9 +6544,25 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr
> > addr, int val)
> >
> > trace_pci_nvme_mmio_
On Sun, Jun 12, 2022 at 07:40:55PM +0800, Jinhao Fan wrote:
>
> > On Jun 10, 2022, at 1:27 AM, Klaus Jensen wrote:
> >
> > I'm ok with following the concensus here, but we all agree that this is
> > a blatant spec violation that ended up manifesting itself down the
> > stack, right?
> >
> >
On Wed, Jun 08, 2022 at 10:55:30PM +0200, Klaus Jensen wrote:
>
> Keith, is this a bug in the kernel? If the code here would expect the
> doorbell buffer to be updated for the admin queue as well, would we
> break?
The admin queue has to be created before db buffer can be set up, so we can't
On Thu, May 12, 2022 at 11:30:55AM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> The internally maintained AEN mask is not cleared on reset. Fix this.
Looks good.
Reviewed-by: Keith Busch
me_dsm_bh() is called which deletes and sets iocb->bh to NULL. When reentry
> returns from nvme_dsm_cb(), metadata deallocation takes place again, and
> results in a null pointer dereference on the iocb->bh:
Nice, thank you for the detailed analysis. Patch looks good.
Reviewed-by: Keith Busch
On Tue, May 17, 2022 at 01:04:56PM +0200, Klaus Jensen wrote:
> >
> > Should we consider this series ready to merge?
> >
>
> Hi Lukasz and Lukasz :)
>
> Yes, I'm queing this up.
FWIW, this looks good to me. I was hoping to give it a test run, but I don't
think I'll get to that for another
On Mon, Apr 25, 2022 at 11:59:30AM +0200, Klaus Jensen wrote:
> The approach is neat and simple, but I don't think it has the intended
> effect. The memory region addr is just left at 0x0, so we just end up
> with mapping that directly into the qsg and in my test setup, this
> basically does DMA
s.
Series looks good.
Reviewed-by: Keith Busch
On Fri, Apr 15, 2022 at 10:27:21PM +0300, Dmitry Tikhov wrote:
> Since there is no else after nvme_dsm_cb invocation, metadata associated
> with non-zero block range is currently zeroed. Also this behaviour leads
> to segfault since we schedule iocb->bh two times. First when entering
> nvme_dsm_cb
On Fri, Mar 04, 2022 at 04:54:07PM +0800, zhenwei pi wrote:
> +smart->u.nvme.temperature = le16_to_cpu(log.temperature);
The 'temperature' offset is not properly aligned, so I think you need to
use an unaligned le accessor like 'stw_le_p()'.
inux kernel[1].
>
> [1]:
> https://lore.kernel.org/linux-nvme/20220201190128.3075065-1-kbu...@kernel.org/
Thanks Klaus, this looks good to me.
Reviewed-by: Keith Busch
On Tue, Feb 22, 2022 at 09:48:06AM +, Stefan Hajnoczi wrote:
> On Mon, 21 Feb 2022 at 12:00, Klaus Jensen wrote:
> >
> > Yes, I'll go ahead as mentor for this.
> >
> > @Keith, if you want to join in, let us know :)
Thank you for setting this up, I would be happy assist with the cause!
> >
Linux kernel[1].
>
> [1]:
> https://lore.kernel.org/linux-nvme/20220201190128.3075065-1-kbu...@kernel.org/
Other than comment on 6/6, series looks good to me.
Reviewed-by: Keith Busch
On Mon, Feb 14, 2022 at 01:30:29PM +0100, Klaus Jensen wrote:
> @@ -384,6 +389,12 @@ static int nvme_ns_check_constraints(NvmeNamespace *ns,
> Error **errp)
> return -1;
> }
>
> +if (ns->params.pif != NVME_PI_GUARD_16 &&
> +ns->params.pif != NVME_PI_GUARD_64) {
> +
zrwa resources, i.e. number of zones that can have a zrwa),
> "zoned.zrwas" (zrwa size in LBAs), "zoned.zrwafg" (granularity in LBAs
> for flushes).
>
> Signed-off-by: Klaus Jensen
Looks good, and will just need a minor update if you choose to take the
feedback from patch 2 onboard.
Reviewed-by: Keith Busch
On Thu, Nov 25, 2021 at 08:37:33AM +0100, Klaus Jensen wrote:
> @@ -295,7 +295,7 @@ static void nvme_assign_zone_state(NvmeNamespace *ns,
> NvmeZone *zone,
> case NVME_ZONE_STATE_READ_ONLY:
> break;
> default:
> -zone->d.za = 0;
> +NVME_ZA_CLEAR_ALL(zone->d.za);
On Thu, Nov 25, 2021 at 08:37:34AM +0100, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Add enumeration for OZCS values.
Looks good.
Reviewed-by: Keith Busch
t; +uint64_tslba;
> +uint32_trsvd12;
> +uint8_t zsa;
> +uint8_t zsflags[3];
This should be just a single uint8_t for zsflags, followed by
'uint8_t rsvd[2]'.
Otherwise, looks good.
Reviewed-by: Keith Busch
d if
that assumption ever changes.
Reviewed-by: Keith Busch
non-memories regions.
Looks good.
Reviewed-by: Keith Busch
On Thu, Dec 16, 2021 at 06:55:09PM +0100, Philippe Mathieu-Daudé wrote:
> dma_buf_read/dma_buf_write() return a MemTxResult type.
> Do not discard it, propagate the DMA error to the caller.
>
> Signed-off-by: Philippe Mathieu-Daudé
Looks good.
Reviewed-by: Keith Busch
On Tue, Nov 16, 2021 at 04:34:39PM +0100, Łukasz Gieryk wrote:
> if (!pci_is_vf(>parent_obj) && n->params.sriov_max_vfs) {
> -pcie_sriov_pf_disable_vfs(>parent_obj);
> +if (rst != NVME_RESET_CONTROLLER) {
> +pcie_sriov_pf_disable_vfs(>parent_obj);
Shouldn't this
second patch changes the default for 'shared' such that namespaces
> are shared by default and will thus by default be attached to hotplugged
> controllers. This adds a compat property for older machine versions and
> updates the documentation to reflect this.
Series looks good.
Reviewed-by: Keith Busch
On Tue, Sep 14, 2021 at 10:37:26PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> Move ZNS related helpers and types into zoned.h. Use a common prefix
> (nvme_zoned or nvme_ns_zoned) for zns related functions.
Just a nitpicks on the naming, you can feel free to ignore.
Since we're within
I really hope hosts weren't
actually trying fused commands on this target, but it's good to confirm.
Reviewed-by: Keith Busch
a host error if
the controller was enabled with invalid queue addresses anyway. The controller
only needs to verify the lower bits are clear, which we do later.
Reviewed-by: Keith Busch
On Fri, Aug 13, 2021 at 03:02:22PM +0530, Naveen wrote:
> +static uint16_t nvme_identify_ns_common(NvmeCtrl *n, NvmeRequest *req)
> +{
> +NvmeIdNs id_ns = {};
> +
> +id_ns.nsfeat |= (0x4 | 0x10);
> +id_ns.dpc = 0x1f;
> +
> +NvmeLBAF lbaf[16] = {
> +[0] = {.ds = 9},
> +
On Wed, Jul 21, 2021 at 09:48:32AM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> The specification uses a set of 32 bit PMRMSCL and PMRMSCU registers to
> make up the 64 bit logical PMRMSC register.
>
> Make it so.
Looks good.
Reviewed-by: Keith Busch
" checks for each register to
enforce correct positioning of the BAR offsets at build time.
Reviewed-by: Keith Busch
> Signed-off-by: Klaus Jensen
> Reviewed-by: Gollu Appalanaidu
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> include/block/nvme.h | 29 +
> +int hal_init()
> +{
> +int retval = -1;
> +switch (GetSidebandInterface()) {
> +case qemu_nvme_mi:
> +retval = qemu_mi_init();
> +break;
> +default:
> +break;
> +}
> +return retval;
> +}
> +
> +int hal_open()
> +{
> +int retval = -1;
> +
On Fri, Jul 09, 2021 at 07:25:45PM +0530, Padmakar Kalghatgi wrote:
> The following commands are tested with nvme-cli by hooking
> to the cid of the vsock as shown above and use the socket
> send/recieve commands to issue the commands and get the response.
Why sockets? Shouldn't mi targets use
.jer...@kernkonzept.com>
>
> Fixes: ca247d35098d ("hw/block/nvme: fix pin-based interrupt behavior")
> Reported-by: Jakub Jermář
> Signed-off-by: Klaus Jensen
Looks good.
Reviewed-by: Keith Busch
igured.
>
> Cc: qemu-sta...@nongnu.org
> Fixes: 75c3c9de961d ("hw/block/nvme: disable PMR at boot up")
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/362
> Signed-off-by: Klaus Jensen
Looks good.
Reviewed-by: Keith Busch
> ---
> hw/nvme/ctrl.c | 4 +++
On Thu, Jun 17, 2021 at 09:06:57PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> This partially reverts commit 98f84f5a4eca5c03e32fff20f246d9b4b96d6422.
>
> Since all "multi aio" commands are now reimplemented to properly track
> the nested aiocbs, we can revert the "hack" that was
ultaneously without tracking the returned
> aiocbs.
Klaus,
THis series looks good to me.
Reviewed-by: Keith Busch
On Thu, Jun 17, 2021 at 12:08:20PM +0200, Klaus Jensen wrote:
> if (cq->tail != cq->head) {
> +if (!pending) {
> +n->cq_pending++;
> +}
You should check cq->irq_enabled before incrementing cq_pending. You
don't want to leave the irq asserted when polled queues
On Sat, Jun 12, 2021 at 01:46:30AM +0200, Heinrich Schuchardt wrote:
> +``eui64``
> + Set the EUI-64 of the namespace. This will be reported as a "IEEE Extended
> + Unique Identifier" descriptor in the Namespace Identification Descriptor
> List.
This needs to match Identify Namespace's EUI64
On Tue, Jun 01, 2021 at 09:07:56PM +0200, Klaus Jensen wrote:
> On Jun 1 11:07, Keith Busch wrote:
> > On Tue, Jun 01, 2021 at 07:41:34PM +0200, Klaus Jensen wrote:
> > > On Jun 1 10:19, Keith Busch wrote:
> > > > On Tue, Jun 01, 2021 at 08:07:48PM +0530, Gollu App
On Tue, Jun 01, 2021 at 07:41:34PM +0200, Klaus Jensen wrote:
> On Jun 1 10:19, Keith Busch wrote:
> > On Tue, Jun 01, 2021 at 08:07:48PM +0530, Gollu Appalanaidu wrote:
> > > NVMe Boot Partitions provides an area that may be read by the host
> > > without initializ
On Tue, Jun 01, 2021 at 08:07:48PM +0530, Gollu Appalanaidu wrote:
> NVMe Boot Partitions provides an area that may be read by the host
> without initializing queues or even enabling the controller. This
> allows various platform initialization code to be stored on the NVMe
> device instead of
On Wed, May 05, 2021 at 06:09:10PM -0500, Eric Blake wrote:
> On 5/5/21 5:07 PM, Philippe Mathieu-Daudé wrote:
> > +Eric
> >
> > On 5/5/21 11:22 PM, Keith Busch wrote:
> >> On Wed, May 05, 2021 at 11:10:31PM +0200, Philippe Mathieu-Daudé wrote:
> >>>
On Wed, May 05, 2021 at 11:10:31PM +0200, Philippe Mathieu-Daudé wrote:
> The compiler isn't clever enough to figure 'SEG_CHUNK_SIZE' is
> a constant! Help it by using a definitions instead.
I don't understand. It's labeled 'const', so any reasonable compiler
will place it in the 'text' segment
On Mon, Apr 19, 2021 at 09:27:47PM +0200, Klaus Jensen wrote:
> From: Klaus Jensen
>
> This series consists of various clean up patches.
>
> The final patch moves nvme emulation from hw/block to hw/nvme.
Series looks good to me.
Reviewed-by: Keith Busch
On Wed, Mar 31, 2021 at 02:54:27PM +0530, Gollu Appalanaidu wrote:
> This is to add support for Device Self Test Command (DST) and
> DST Log Page. Refer NVM Express specification 1.4b section 5.8
> ("Device Self-test command")
Please don't write change logs that just say what you did. I can read
On Fri, Apr 09, 2021 at 01:55:01PM +0200, Klaus Jensen wrote:
> On Apr 9 20:05, Minwoo Im wrote:
> > On 21-04-09 13:14:02, Gollu Appalanaidu wrote:
> > > NSZE is the total size of the namespace in logical blocks. So the max
> > > addressable logical block is NLB minus 1. So your starting logical
On Thu, Apr 08, 2021 at 09:53:13PM +0530, Padmakar Kalghatgi wrote:
> +/*
> + * The first PRP list entry, pointed by PRP2 can contain
> + * offsets. Hence, we need calculate the no of entries in
> + * prp2 based on the offset it has.
> +
ders
Series looks fine.
Reviewed-by: Keith Busch
ew.
Looks good to me.
Reviewed-by: Keith Busch
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