Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> msgsnd has a broadcast mode that sends hypervisor doorbells to all
> threads belonging to the same core as the target. A "subcore" mode
> sends to all or one thread depending on 1LPAR mode.
>
>
Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR
> means
> per-thread or per-core, depending on 1LPAR mode.
>
> Signed-off-by: Nicholas Piggin
> ---
> target/ppc/spr_common.h |
Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> LDBAR, TTR are a Power-specific SPRs. These simple implementations
> are enough for IBM proprietary firmware for now.
>
> Signed-off-by: Nicholas Piggin
> ---
> target/ppc/cpu.h | 2 ++
>
Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers
> that
> can be accessed via these indirect SPRs.
>
> SCRATCH registers only provide storage, but they are used by firmware
>
Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> PTCR is a per-core register.
>
> Signed-off-by: Nicholas Piggin
> ---
> target/ppc/misc_helper.c | 16 ++--
> target/ppc/translate.c | 4
> 2 files changed, 18
Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR
> registers with simple (generic) implementations.
>
> Signed-off-by: Nicholas Piggin
> ---
> target/ppc/cpu_init.c | 12
Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> PPR32 provides access to the upper half of PPR.
>
> Signed-off-by: Nicholas Piggin
> ---
> target/ppc/cpu.h| 1 +
> target/ppc/spr_common.h | 2 ++
> target/ppc/cpu_init.c | 12
Looks like this patch is failing to apply to the current master head?
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> attn is an implementation-specific instruction that on POWER (and G5/
> 970) can be enabled with a HID bit (disabled = illegal), and
> executing
> it
Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> The DECAR SPR is 32-bits width.
>
> Signed-off-by: Nicholas Piggin
> ---
> target/ppc/cpu_init.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/ppc/cpu_init.c
Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> Change the logging not to print to stderr as well, because a
> checkstop is a guest error (or perhaps a simulated machine error)
> rather than a QEMU error, so send it to the log.
>
> Update the
Reviewed-by: Glenn Miles
Thanks,
Glenn
On Tue, 2024-05-21 at 11:30 +1000, Nicholas Piggin wrote:
> checkstop state does not halt the system, interrupts continue to be
> serviced, and other CPUs run. Make it stop the machine with
> qemu_system_guest_panicked.
>
> Signed-off-by: Nicholas Piggin
On Tue, 2024-05-21 at 08:18 +0200, Cédric Le Goater wrote:
> On 5/21/24 08:11, Chalapathi V wrote:
> > On 18-05-2024 01:24, Miles Glenn wrote:
> > > Chalapathi,
> > >
> > > I'm having trouble seeing the benefit of breaking this commit out
> > > from
&
Chalapathi,
I'm having trouble seeing the benefit of breaking this commit out from
patch 1/5. It seems like the two should be merged into a single commit
responsible for adding the PNV SPI Controller model.
-Glenn
On Thu, 2024-05-16 at 11:33 -0500, Chalapathi V wrote:
> In this commit SPI
Reviewed-by: Glenn Miles
-Glenn
On Thu, 2024-05-16 at 11:33 -0500, Chalapathi V wrote:
> In this commit, create SPI controller on p10 chip and connect cs irq.
>
> The QOM tree of spi controller and seeprom are.
> /machine (powernv10-machine)
> /chip[0] (power10_v2.0-pnv-chip)
Reviewed-by: Glenn Miles
-Glenn
On Thu, 2024-05-16 at 11:33 -0500, Chalapathi V wrote:
> Add Microchip's 25CSM04 Serial EEPROM to m25p80. 25CSM04 provides 4
> Mbits
> of Serial EEPROM utilizing the Serial Peripheral Interface (SPI)
> compatible
> bus. The device is organized
Hi Chalapathi,
Looks good. I think I would just shorten the names of the xscom
read/write functions to make things more readable inside the
transaction function.
-Glenn
Reviewed-by: Glenn Miles
> +static uint64_t pnv_spi_seeprom_xscom_addr(uint32_t reg)
> +{
> +return
Hi Chalapathi,
Looks good. Just some suggestions on readability and some
simplifications (see below).
Thanks,
Glenn
On Thu, 2024-05-16 at 11:33 -0500, Chalapathi V wrote:
> SPI controller device model supports a connection to a single SPI
> responder.
> This provide access to SPI seeproms,
Looks good. Thanks for taking care of that for us!
-Glenn
Reviewed-by: Glenn Miles
On Tue, 2024-04-16 at 20:47 +0200, Philippe Mathieu-Daudé wrote:
> One of the biggest change from I2C spec v6 -> v7 is:
>
> • Updated the terms "master/slave" to "controller/target"
>
> Since it follows the
Thanks for doing this, Cédric!
Reviewed-by: Glenn Miles
-Glenn
On Mon, 2024-03-25 at 14:48 +0100, Cédric Le Goater wrote:
> The PCA9552 and PCA9554 devices are both I2C GPIO controllers and the
> PCA9552 also can drive LEDs. Do all the necessary adjustments to move
> the models unde
On Thu, 2024-03-21 at 17:01 +0100, Cédric Le Goater wrote:
> Coverity detected an "Integer handling" issue with the pin value :
>
> In expression "state >> pin", right shifting "state" by more than 7
> bits always yields zero. The shift amount, "pin", is as much as 8.
>
> In practice, this
On Mon, 2024-03-18 at 16:58 +0100, Cédric Le Goater wrote:
Thanks for fixing that!
-Glenn
Reviewed-by: Glenn Miles
> The I2C controller is a subunit of the processor. Make it so and
> avoid
> QEMU crashes.
>
> $ build/qemu-system-ppc64 -S -machine powernv9 -device pnv-i2c
>
On Tue, 2024-03-05 at 07:20 +0100, Cédric Le Goater wrote:
> On 3/4/24 23:32, Paolo Bonzini wrote:
> > On 1/25/24 23:48, Glenn Miles wrote:
> > > Specs are available here:
> > >
> > > https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
> > >
> > > This is a simple model supporting the
On Tue, 2024-02-20 at 10:35 +1000, Nicholas Piggin wrote:
> On Fri Feb 16, 2024 at 3:50 AM AEST, Peter Maydell wrote:
> > On Thu, 15 Feb 2024 at 17:16, Nicholas Piggin
> > wrote:
> > > Calculate the BHRB base from arithmetic on the tcg_env target
> > > ptr.
> > >
> > > Signed-off-by: Nicholas
On Wed, 2023-10-18 at 10:59 -0500, Miles Glenn wrote:
> On Thu, 2023-10-19 at 01:06 +1000, Nicholas Piggin wrote:
> > On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> > > This is a series of patches for adding support for the Branch
> > > History
> >
On Wed, 2023-11-22 at 09:55 +0100, Cédric Le Goater wrote:
> On 11/21/23 20:09, Glenn Miles wrote:
> > Specs are available here:
> >
> > https://www.nxp.com/docs/en/data-sheet/PCA9554_9554A.pdf
> >
> > This is a simple model supporting the basic registers for GPIO
> > mode. The device also
On Tue, 2023-11-21 at 19:36 +0100, Cédric Le Goater wrote:
> On 11/21/23 00:51, Glenn Miles wrote:
> > For power10-rainier, a pca9552 device is used for PCIe slot hotplug
> > power control by the Power Hypervisor code. The code expects that
> > some time after it enables power to a PCIe slot by
On Tue, 2023-11-21 at 19:26 +0100, Cédric Le Goater wrote:
> On 11/21/23 17:36, Miles Glenn wrote:
> > On Tue, 2023-11-21 at 08:29 +0100, Cédric Le Goater wrote:
> > > On 11/21/23 02:33, Nicholas Piggin wrote:
> > > > On Tue Nov 21, 2023 at 9:51 AM AEST, Glenn Miles
On Tue, 2023-11-21 at 07:46 +0100, Cédric Le Goater wrote:
> On 11/21/23 00:51, Glenn Miles wrote:
> > Create a new powernv machine type, powernv10-rainier, that
> > will contain rainier-specific devices.
> >
> > Signed-off-by: Glenn Miles
> > ---
> > hw/ppc/pnv.c | 29
On Tue, 2023-11-21 at 08:29 +0100, Cédric Le Goater wrote:
> On 11/21/23 02:33, Nicholas Piggin wrote:
> > On Tue Nov 21, 2023 at 9:51 AM AEST, Glenn Miles wrote:
> > > Create a new powernv machine type, powernv10-rainier, that
> > > will contain rainier-specific devices.
> >
> > Is the plan to
On Fri, 2023-11-17 at 17:04 +0100, Cédric Le Goater wrote:
> > Well, I was hoping to sweep the pca9554 model under the PowerNV
> > maintainership (like pca9552 is under the BMC aspeed
> > maintainership).
> > I did update the PowerNV list to include it, but perhaps that was
> > presumptuous of me.
On Wed, 2023-11-15 at 23:34 +0100, Cédric Le Goater wrote:
> On 11/15/23 17:37, Miles Glenn wrote:
> > On Wed, 2023-11-15 at 08:28 +0100, Cédric Le Goater wrote:
> > > On 11/14/23 20:56, Glenn Miles wrote:
> > > > The Power Hypervisor code expects to see a pc
On Wed, 2023-11-15 at 08:28 +0100, Cédric Le Goater wrote:
> On 11/14/23 20:56, Glenn Miles wrote:
> > The Power Hypervisor code expects to see a pca9552 device connected
> > to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left-
> > justified address of 0xC6). This is used by
On Tue, 2023-11-14 at 18:55 +0100, Cédric Le Goater wrote:
> On 11/14/23 16:26, Miles Glenn wrote:
> > On Mon, 2023-11-13 at 10:10 +0100, Cédric Le Goater wrote:
> > > On 11/10/23 20:49, Glenn Miles wrote:
> > > > The PNV I2C Controller was clearing the status
On Mon, 2023-11-13 at 10:07 +0100, Cédric Le Goater wrote:
> On 11/10/23 20:49, Glenn Miles wrote:
> > The PNV I2C engines for power9 and power10 were being assigned a
> > base
> > XSCOM address that was off by one I2C engine's address range such
> > that engine 0 had engine 1's address and so on.
On Mon, 2023-11-13 at 10:10 +0100, Cédric Le Goater wrote:
> On 11/10/23 20:49, Glenn Miles wrote:
> > The PNV I2C Controller was clearing the status register
> > after a reset without repopulating the "upper threshold
> > for I2C ports", "Command Complete" and the SCL/SDA input
> > level fields.
On Mon, 2023-11-13 at 10:05 +0100, Cédric Le Goater wrote:
> On 11/10/23 20:49, Glenn Miles wrote:
> > The Power Hypervisor code expects to see a pca9552 device connected
> > to the 3rd PNV I2C engine on port 1 at I2C address 0x63 (or left-
> > justified address of 0xC6). This is used by
On Fri, 2023-11-10 at 11:22 -0600, Glenn Miles wrote:
> This series of patches includes support, tests and fixes for
> adding PCA9552 and PCA9554 I2C devices to the powernv10 chip.
>
> The PCA9552 device is used for PCIe slot hotplug power control
> and monitoring, while the PCA9554 device is
On Thu, 2023-11-09 at 18:15 +0100, Cédric Le Goater wrote:
> Coverity warns that "i2c_bus_busy(i2c->busses[i]) << i" might
> overflow
> because the expression is evaluated using 32-bit arithmetic and then
> used in a context expecting a uint64_t.
>
> While we are at it, introduce a
On Fri, 2023-10-27 at 07:05 +0200, Philippe Mathieu-Daudé wrote:
> On 25/10/23 08:56, Cédric Le Goater wrote:
> > On 10/24/23 23:29, Glenn Miles wrote:
> > > Power9 is supposed to have 4 PIB-connected I2C engines with the
> > > following number of ports on each engine:
> > >
> > > 0: 2
> > >
On Tue, 2023-10-24 at 18:46 +0100, Peter Maydell wrote:
> On Tue, 24 Oct 2023 at 18:40, Glenn Miles
> wrote:
> > Testing of the LED state showed that when the LED polarity was
> > set to GPIO_POLARITY_ACTIVE_LOW and a low logic value was set on
> > the input GPIO of the LED, the LED was being
On Tue, 2023-10-24 at 07:47 +0200, Cédric Le Goater wrote:
> Hello Glenn,
>
> On 10/23/23 18:52, Glenn Miles wrote:
> > Power9 is supposed to have 4 PIB-connected I2C engines with the
> > following number of ports on each engine:
> >
> > 0: 2
> > 1: 13
> > 2: 2
> > 3: 2
> >
On Tue, 2023-10-24 at 10:15 +1030, Andrew Jeffery wrote:
> On Fri, 2023-10-20 at 13:23 -0500, Glenn Miles wrote:
> > The pca9552 INPUT0 and INPUT1 registers are supposed to
> > hold the logical values of the LED pins. A logical 0
> > should be seen in the INPUT0/1 registers for a pin when
> > its
On Tue, 2023-10-24 at 10:13 +1030, Andrew Jeffery wrote:
> On Fri, 2023-10-20 at 13:23 -0500, Glenn Miles wrote:
> > The pca9552 code was updating output GPIO states whenever
> > the pin state was updated even if the state did not change.
> > This commit adds a check so that we only update the
On Tue, 2023-10-24 at 10:04 +1030, Andrew Jeffery wrote:
> On Fri, 2023-10-20 at 11:32 -0500, Miles Glenn wrote:
> > On Fri, 2023-10-20 at 11:42 +0200, Philippe Mathieu-Daudé wrote:
> > > On 20/10/23 04:51, Andrew Jeffery wrote:
> > > > On Thu, 2023-10-19 at
On Fri, 2023-10-20 at 15:18 +1030, Andrew Jeffery wrote:
> On Thu, 2023-10-19 at 15:40 -0500, Glenn Miles wrote:
> > Allow external devices to drive pca9552 input pins by adding
> > input GPIO's to the model. This allows a device to connect
> > its output GPIO's to the pca9552 input GPIO's.
> >
On Fri, 2023-10-20 at 11:42 +0200, Philippe Mathieu-Daudé wrote:
> On 20/10/23 04:51, Andrew Jeffery wrote:
> > On Thu, 2023-10-19 at 15:40 -0500, Glenn Miles wrote:
> > > > The pca9552 INPUT0 and INPUT1 registers are supposed to
> > > > hold the logical values of the LED pins. A logical 0
> > >
On Tue, 2023-10-10 at 22:41 +0200, Cédric Le Goater wrote:
> On 10/10/23 22:35, Miles Glenn wrote:
> > On Tue, 2023-10-10 at 21:31 +0100, Mark Cave-Ayland wrote:
> > > On 10/10/2023 20:52, Glenn Miles wrote:
> > >
> > > > Testing of the pca9552 device
On Thu, 2023-10-19 at 01:06 +1000, Nicholas Piggin wrote:
> On Tue Sep 26, 2023 at 3:43 AM AEST, Glenn Miles wrote:
> > This is a series of patches for adding support for the Branch
> > History
> > Rolling Buffer (BHRB) facility. This was added to the Power ISA
> > starting with version 2.07.
On Tue, 2023-10-17 at 09:01 +0200, Cédric Le Goater wrote:
> On 10/17/23 00:20, Glenn Miles wrote:
> > Upstreams the PowerNV I2C controller model originally
> > authored by Cédric Le Goater with minor changes by
> > myself to split the actual addition of the model from
> > wiring it up to a power
On Fri, 2023-10-13 at 10:58 +0200, Philippe Mathieu-Daudé wrote:
> Hi Glenn, Cédric,
>
> On 12/10/23 22:08, Glenn Miles wrote:
> > From: Cédric Le Goater
> >
> > The more recent IBM power processors have an embedded I2C
> > controller that is accessible by software via the XSCOM
> > address
On Fri, 2023-10-13 at 09:06 +0200, Cédric Le Goater wrote:
> On 10/12/23 22:08, Glenn Miles wrote:
> > From: Cédric Le Goater
> >
> > Wires up three I2C controller instances to the powernv9 chip
> > XSCOM address space.
> >
> > Each controller instance is wired up to a single I2C bus of
> > its
On Fri, 2023-10-13 at 09:04 +0200, Cédric Le Goater wrote:
> On 10/12/23 22:08, Glenn Miles wrote:
> > From: Cédric Le Goater
> >
> > The more recent IBM power processors have an embedded I2C
> > controller that is accessible by software via the XSCOM
> > address space.
> >
> > Each instance of
On Tue, 2023-10-10 at 23:02 +1030, Joel Stanley wrote:
> On Fri, 6 Oct 2023 at 07:23, Glenn Miles
> wrote:
> > Allow external devices to drive pca9552 input pins by adding
> > input GPIO's to the model. This allows a device to connect
> > its output GPIO's to the pca9552 input GPIO's.
> >
> >
On Tue, 2023-10-10 at 22:10 +0200, Cédric Le Goater wrote:
> On 10/10/23 19:19, Glenn Miles wrote:
> > From: Cédric Le Goater
> >
> > The more recent IBM power processors have an embedded I2C
> > controller that is accessible by software via the XSCOM
> > address space.
> >
> > Each instance of
On Tue, 2023-10-10 at 22:14 +0200, Cédric Le Goater wrote:
> On 10/10/23 19:19, Glenn Miles wrote:
> > From: Cédric Le Goater
> >
> > Wires up three I2C controller instances to the powernv9 chip
> > XSCOM address space.
> >
> > Each controller instance is wired up to a single I2C bus of
> > its
On Wed, 2023-10-11 at 16:27 +0200, Cédric Le Goater wrote:
> On 9/27/23 22:32, Glenn Miles wrote:
> > The pca9552 INPUT0 and INPUT1 registers are supposed to
> > hold the logical values of the LED pins. A logical 0
> > should be seen in the INPUT0/1 registers for a pin when
> > its corresponding
On Wed, 2023-10-11 at 19:05 +0200, Cédric Le Goater wrote:
> On 10/5/23 22:41, Glenn Miles wrote:
> > Allow external devices to drive pca9552 input pins by adding
> > input GPIO's to the model. This allows a device to connect
> > its output GPIO's to the pca9552 input GPIO's.
> >
> > In order
On Tue, 2023-10-10 at 21:31 +0100, Mark Cave-Ayland wrote:
> On 10/10/2023 20:52, Glenn Miles wrote:
>
> > Testing of the pca9552 device on the powernv platform
> > showed that the reset method was not being called when
> > an instance of the device was realized. This was causing
> > the
On Tue, 2023-10-10 at 21:58 +0200, Cédric Le Goater wrote:
> On 10/10/23 21:52, Glenn Miles wrote:
> > Testing of the pca9552 device on the powernv platform
> > showed that the reset method was not being called when
> > an instance of the device was realized. This was causing
> > the
On Mon, 2023-10-09 at 22:42 +0200, Cédric Le Goater wrote:
> Hello Glenn,
>
> On 10/9/23 20:05, Glenn Miles wrote:
> > From: Cédric Le Goater
> >
> > Not supported :
> >
> > . 10 bit addresses
> > . multimaster
> > . slave
> >
> > Signed-off-by: Cédric Le Goater
> > Signed-off-by:
On Mon, 2023-10-09 at 23:06 +0200, Cédric Le Goater wrote:
> Hello Glenn,
>
> On 10/5/23 23:10, Glenn Miles wrote:
> > Testing of the pca9552 device on the powernv platform
> > showed that the reset method was not being called when
> > an instance of the device was realized. This was causing
> >
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