Now all decoding has been done before any code generation.
There is no need anymore to save and restore cc_op* and
pc_save but, for the time being, assert that this is indeed
the case.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 12 +++-
1 file changed, 3 insertions
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.h | 3 +
target/i386/tcg/translate.c | 147 +--
target/i386/tcg/decode-new.c.inc | 45 +++---
target/i386/tcg/emit.c.inc | 130 ++-
4 files changed, 166
Just like X86_ENTRYr, X86_ENTRYwr is easily changed to use only T0.
In this case, the motivation is to use it for the MOV instruction
family. The case when you need to preserve the input value is the
odd one, as it is used basically only for BLS* instructions.
Signed-off-by: Paolo Bonzini
These have very simple generators and no need for complex group
decoding. Apart from LAR/LSL which are simplified to use
gen_op_deposit_reg_v and movcond, the code is generally lifted
from translate.c into the generators.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.h | 7
SHLD/SHRD can have 3 register operands - s->T0, s->T1 and either
1 or CL - and therefore decode->op[2] is taken by the low part
of the register being shifted. Pass X86_OP_* to gen_shift_count
from its current callers and hardcode cpu_regs[R_ECX] as the
shift count.
Signed-off-by: Paol
e creation of a useless
temporary. This can be done in the only place where it matters, which is
gen_op_j_ecx.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 41 +++--
1 file changed, 17 insertions(+), 24 deletions(-)
diff --git a/target/i386/tcg/tra
Group them so that it is easier to figure out which two-byte opcodes to
tackle together.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
e used by opcodes in the 0F 3A table
works fine.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 83 +---
target/i386/tcg/decode-new.c.inc | 6 ++-
target/i386/tcg/emit.c.inc | 42
3 files changed, 48 insertions(+), 83 deletions(-)
It is already checked before getting there.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 26 --
1 file changed, 8 insertions(+), 18 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 67f2e792166..ee5ef3ccbc6
I am not sure why I made it use T1. It is a bit more symmetric with
respect to X86_ENTRYwr (which uses T0 for the "w"ritten operand
and T1 for the "r"ead operand), but it is also less flexible because it
does not let you apply zextT0/sextT0.
Signed-off-by: Paolo Bonzini
Use gen_ld_modrm/gen_st_modrm, moving them and gen_shift_flags to the
caller. This way, gen_shiftd_rm_T1 becomes something that the new
decoder can call.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 55 ++---
1 file changed, 14 insertions
This is already partly implemented due to VLDMXCSR and VSTMXCSR; finish
the job.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.h | 7 ++
target/i386/tcg/translate.c | 188 ---
target/i386/tcg/decode-new.c.inc | 48 +++-
target/i386/tcg
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.h | 1 +
target/i386/tcg/decode-new.c.inc | 4 ++--
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index 46a96b220d0..8465717ea21 100644
--- a/target/i386
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 79
target/i386/tcg/decode-new.c.inc | 3 +-
target/i386/tcg/emit.c.inc | 51 +
3 files changed, 53 insertions(+), 80 deletions(-)
diff --git a/target/i386/tcg
of the unification, the gen_lea_modrm() name is now free,
so rename gen_load_ea() to gen_lea_modrm(). This is as good a name
and it makes the changes to translate.c easier to review.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.h | 14 ++-
target/i386/tcg/translate.c | 152
All other control registers are stored plainly in CPUX86State.
Signed-off-by: Paolo Bonzini
---
target/i386/helper.h | 2 +-
target/i386/tcg/sysemu/misc_helper.c | 20 +---
target/i386/tcg/emit.c.inc | 2 +-
3 files changed, 7 insertions(+), 17
Complete implementation of C and D operand types, then the operations
are just MOVs.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 79
target/i386/tcg/decode-new.c.inc | 53 +++--
target/i386/tcg/emit.c.inc | 20
CPUX86State argument would only be used to fetch bytes, but that has to be
done before the generator function is called. So remove it, and all
temptation together with it.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.h | 2 +-
target/i386/tcg/decode-new.c.inc | 4
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 35
target/i386/tcg/decode-new.c.inc | 3 ++-
target/i386/tcg/emit.c.inc | 24 ++
3 files changed, 26 insertions(+), 36 deletions(-)
diff --git a/target/i386/tcg
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.h | 1 +
target/i386/tcg/translate.c | 74
target/i386/tcg/decode-new.c.inc | 51 +++-
target/i386/tcg/emit.c.inc | 82
4 files changed, 132
This is a bit more generic, as it can be applied to MPX as well.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.h | 5 +++--
target/i386/tcg/decode-new.c.inc | 12
target/i386/tcg/emit.c.inc | 3 ++-
3 files changed, 9 insertions(+), 11 deletions(-)
diff
SYSENTER is allowed in VM86 mode, but not in real mode. Split the check
so that PE and !VM86 are covered by separate bits.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.h | 8 ++--
target/i386/tcg/decode-new.c.inc | 9 +++--
2 files changed, 13 insertions(+), 4
Aesthetic change only.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 93
1 file changed, 46 insertions(+), 47 deletions(-)
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 4c567911f41..4e745f10dd8
This makes for easier cpu_cc_* setup, and not using set_cc_op()
should come in handy if QEMU ever implements APX.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 4 ++--
target/i386/tcg/emit.c.inc | 24 +---
2 files changed, 11 insertions(+), 17
tions are both false for CC_OP_EFLAGS, both true for CC_OP_ADCOX,
and one each true for CC_OP_ADCX/ADOX.
The new logic also makes it easy to drop usage of tmp0.
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 9 +++---
target/i386/tcg/emit.c.inc | 61 ++-
-20: move all two-byte opcodes except for 00/01/1A/1B/C7
to new decoder.
Patches 21-25: move decoding of modrm bytes entirely to new decoder,
and cleanup.
Paolo Bonzini (25):
target/i386: remove CPUX86State argument from generator functions
target/i386: rewrite flags writeback for ADCX/ADOX
a number of Intel specific status
bits. Modify kvm_mce_inject to properly generate MCEs on AMD platforms.
Reported-by: William Roche
Signed-off-by: John Allen
Message-ID: <20240603193622.47156-2-john.al...@amd.com>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 2 ++
targe
unconditionally.
Signed-off-by: John Allen
Message-ID: <20240603193622.47156-4-john.al...@amd.com>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 1 +
target/i386/cpu.c | 2 +-
target/i386/kvm/kvm.c | 2 +-
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/targe
DISAS_NORETURN suppresses the work normally done by gen_eob(), and therefore
must be used in special cases only. Document them.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target
and debugging
outside of assertions.
Signed-off-by: Phil Dennis-Jordan
Message-ID: <20240605112556.43193-8-p...@philjordan.eu>
Signed-off-by: Paolo Bonzini
---
include/sysemu/hvf_int.h | 5 +++-
accel/hvf/hvf-all.c | 51 +---
2 files changed, 26 inse
of 2 MiB
Signed-off-by: Michal Privoznik
Reviewed-by: Philippe Mathieu-Daudé
Tested-by: Mario Casquero
Message-ID:
Signed-off-by: Paolo Bonzini
---
include/sysemu/hostmem.h | 2 +-
backends/hostmem-epc.c | 1 +
backends/hostmem-file.c | 1 +
backends/hostmem-memfd.c | 1 +
backends
/qemu-project/qemu/-/issues/2198
Message-ID: <20240606095319.229650-5-mark.cave-ayl...@ilande.co.uk>
Cc: qemu-sta...@nongnu.org
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/tcg/translate.c b/targe
Detect early unsupported MADV_MERGEABLE and MADV_DONTDUMP, and print a clearer
error message that points to the deficiency of the host.
Cc: Michal Privoznik
Signed-off-by: Paolo Bonzini
---
backends/hostmem.c | 16
hw/core/machine.c | 8
2 files changed, 24
From: Xin Li
Allow VMX nested-exception support to be exposed in KVM guests, thus
nested KVM guests can enumerate it.
Tested-by: Shan Kang
Signed-off-by: Xin Li
Message-ID: <20231109072012.8078-6-xin3...@intel.com>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 1 +
target/i386
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/sysemu/bpt_helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/i386/tcg/sysemu/bpt_helper.c
b/target/i386/tcg/sysemu/bpt_helper.c
index c1d5fce250c..b29acf41c38 100644
--- a/target/i386/tcg/sysemu/bpt_helper.c
+++ b/target
OR feature.
Reported-by: William Roche
Reviewed-by: Joao Martins
Signed-off-by: John Allen
Message-ID: <20240603193622.47156-3-john.al...@amd.com>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 4
target/i386/cpu.c | 18 +-
target/i386/kvm/kvm.c | 2 ++
3 f
/xnu/xnu-7195.81.3/bsd/man/man2/madvise.2.auto.html
Signed-off-by: Michal Privoznik
Message-ID:
<00f71753bdeb8c0f049fda05fb63b84bb5502fb3.1717584048.git.mpriv...@redhat.com>
Signed-off-by: Paolo Bonzini
---
meson.build | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
run on older
platforms lacking the new function anyway. The third code path selects
dynamically based on runtime detected availability of the weakly-linked
symbol.
Signed-off-by: Phil Dennis-Jordan
Message-ID: <20240605112556.43193-7-p...@philjordan.eu>
Signed-off-by: Paolo Bonzini
---
8-7-xin3...@intel.com>
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 22 +++
target/i386/kvm/kvm.c | 49 +++
target/i386/machine.c | 28 +
3 files changed, 99 insertions(+)
diff --git a/target/i386/c
quot;
mode that does not use any system packages will only work with Python
3.11+.
Signed-off-by: Paolo Bonzini
---
python/scripts/mkvenv.py | 105 ---
1 file changed, 105 deletions(-)
diff --git a/python/scripts/mkvenv.py b/python/scripts/mkvenv.py
index d
-by: Paolo Bonzini
---
util/osdep.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/osdep.c b/util/osdep.c
index e42f4e8121d..5d23bbfbec4 100644
--- a/util/osdep.c
+++ b/util/osdep.c
@@ -64,7 +64,7 @@ int qemu_madvise(void *addr, size_t len, int advice)
}
return 0
the function return a negative value on error, just
like other error paths do.
Signed-off-by: Michal Privoznik
Reviewed-by: David Hildenbrand
Message-ID:
Signed-off-by: Paolo Bonzini
---
util/osdep.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/util/osdep.c b/util
remains unaltered.
Signed-off-by: Mark Cave-Ayland
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2198
Message-ID: <20240606095319.229650-4-mark.cave-ayl...@ilande.co.uk>
Fixes: cc1d28bdbe0 ("target/i386: move 00-5F opcodes to new decoder",
2024-05-07)
Signed-off-b
under all restrictions. Thus,
to avoid confusion, avoid mentioning specific maximum vCPU number
limitations here.
Suggested-by: Daniel P. Berrangé
Signed-off-by: Zhao Liu
Reviewed-by: Daniel P. Berrangé
Message-ID: <20240606085436.2028900-1-zhao1@intel.com>
Signed-off-by: Paolo B
No semantic change, just simpler control flow.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Paolo Bonzini
---
backends/hostmem.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/backends/hostmem.c b/backends/hostmem.c
index 6da3d7383e3
;
[Fix order of dependencies, add dependencies from LM to FRED. - Paolo]
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.h | 6 ++
target/i386/cpu.c | 14 +-
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c64ef0c1a28..ad357
Otherwise, starting any guest on a non-Linux guests results in
qemu-system-arm: Couldn't set property 'merge' on 'memory-backend-ram': Invalid
argument
Cc: Michal Privoznik
Signed-off-by: Paolo Bonzini
---
hw/core/machine.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
efficient hv_vcpu_run_until exits much more rarely, so a true
"kick" is needed before switching to that.
Signed-off-by: Phil Dennis-Jordan
Message-ID: <20240605112556.43193-6-p...@philjordan.eu>
Signed-off-by: Paolo Bonzini
---
target/i386/hvf/hvf.c | 1 +
1 file changed, 1 in
cpu_x86_update_dr7
to load DR7.
Because cpu_x86_update_dr7 takes a 32-bit argument, check
reserved bits prior to calling cpu_x86_update_dr7, and do the
same for DR6 as well for consistency.
This scenario is tested by the "host_rflags" test in kvm-unit-tests.
Signed-off-by: Paolo Bonzini
-
age, don't silently truncate the serial
number string any more, but just error out if it would be truncated.
Buglink: https://issues.redhat.com/browse/RHEL-3542
Suggested-by: Peter Krempa
Signed-off-by: Kevin Wolf
Message-ID: <20240604161755.63448-1-kw...@redhat.com>
Signed-off-by: Paolo Bonzi
)
Reported-by: Daniel P. Berrangé
Signed-off-by: Zhao Liu
Message-ID: <20240605152549.1795762-1-zhao1@intel.com>
[Include error-printf.c unconditionally. - Paolo]
Signed-off-by: Paolo Bonzini
---
stubs/meson.build | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/stu
From: Xin Li
The CR4.FRED bit, i.e., CR4[32], is no longer a reserved bit when FRED
is exposed to guests, otherwise it is still a reserved bit.
Tested-by: Shan Kang
Signed-off-by: Xin Li
Reviewed-by: Zhao Liu
Message-ID: <20231109072012.8078-3-xin3...@intel.com>
Signed-off-by: Paolo B
to the wording.
Signed-off-by: Paolo Bonzini
---
docs/devel/build-system.rst| 13 ++---
configure | 4
python/scripts/vendor.py | 3 ---
python/wheels/tomli-2.0.1-py3-none-any.whl | Bin 12757 -> 0 bytes
4 files chan
tive; none of this is done by HLT and PAUSE.
Start fixing PAUSE, HLT will follow.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/misc_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
index 8316d42ffcd..ed4cda8001e 100644
--
Use decode.c's support for intercepts, doing the check in TCG-generated
code rather than the helper. This is cleaner because it allows removing
the eip_addend argument to helper_pause(), even though it adds a bit of
bloat for opcode 0x90's new decoding function.
Signed-off-by: Paolo Bonzini
From: Mark Cave-Ayland
Instead of directly implementing the writeback using gen_op_st_v(), use the
existing gen_writeback() function.
Suggested-by: Paolo Bonzini
Signed-off-by: Mark Cave-Ayland
Message-ID: <20240606095319.229650-3-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Paolo B
From: Xin Li
Report secondary vm-exit controls and the VMX controls used to
save/load FRED MSRs.
Tested-by: Shan Kang
Signed-off-by: Xin Li
Message-ID: <20231109072012.8078-5-xin3...@intel.com>
Signed-off-by: Paolo Bonzini
---
scripts/kvm/vmxcap | 12
1 file chang
is unaligned
Paolo Bonzini (16):
target/i386: fix pushed value of EFLAGS.RF
target/i386: fix implementation of ICEBP
target/i386: cleanup HLT helpers
target/i386: cleanup PAUSE helpers
target/i386: implement DR7.GD
target/i386: disable/enable breakpoints on vmentry
Use decode.c's support for intercepts, doing the check in TCG-generated
code rather than the helper. This is cleaner because it allows removing
the eip_addend argument to helper_hlt().
Signed-off-by: Paolo Bonzini
---
target/i386/helper.h | 2 +-
target/i386/tcg/sysemu
nts with quotes from the manual about the tasks performed
by a #VMEXIT.
Another gen_eob() task that is missing in VMRUN is preparing the
HF_INHIBIT_IRQ flag for the next instruction, in this case by loading
it from the VMCB control state.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/sys
When preparing an exception stack frame for a fault exception, the value
pushed for RF is 1. Take that into account. The same should be true
of interrupts for repeated string instructions, but the situation there
is complicated.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/seg_helper.c
-by: Paolo Bonzini
---
target/i386/tcg/sysemu/misc_helper.c | 2 +-
target/i386/tcg/sysemu/seg_helper.c | 17 ++---
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/i386/tcg/sysemu/misc_helper.c
b/target/i386/tcg/sysemu/misc_helper.c
index 093cc2d0f90..7fa0c5a06de
From: Mark Cave-Ayland
This will make subsequent changes a little easier to read.
Signed-off-by: Mark Cave-Ayland
Message-ID: <20240606095319.229650-2-mark.cave-ayl...@ilande.co.uk>
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/emit.c.inc | 6 --
1 file changed, 4 insertions
DR7.GD triggers a #DB exception on any access to debug registers.
The GD bit is cleared so that the #DB handler itself can access
the debug registers.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/sysemu/bpt_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target
ICEBP generates a trap-like exception, while gen_exception() produces
a fault. Resurrect gen_update_eip_next() to implement the desired
semantics.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/helper.h | 1 +
target/i386/tcg/helper-tcg.h | 12
Queued, thanks (with the op->unit assignment removed, to
answer your question).
Paolo
On Thu, Jun 6, 2024 at 6:07 PM Xiaoyao Li wrote:
>
> On 6/6/2024 6:44 AM, Paolo Bonzini wrote:
> > There can be other confidential computing classes that are not derived
> > from sev-common. Avoid aborting when encountering them.
>
> I hit it today when rebasing TDX patch
No semantic change, just simpler control flow.
Signed-off-by: Paolo Bonzini
---
backends/hostmem.c | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git a/backends/hostmem.c b/backends/hostmem.c
index 37be93c8bb3..33baca6a974 100644
--- a/backends/hostmem.c
Detect early unsupported MADV_MERGEABLE and MADV_DONTDUMP, and print a clearer
error message that points to the deficiency of the host.
Cc: Michal Privoznik
Signed-off-by: Paolo Bonzini
---
backends/hostmem.c | 16
hw/core/machine.c | 9 +
2 files changed, 25
Queued, thanks. I added a note to the commit message in the third patch:
By the time the MCE reaches the guest, the overflow has been handled
by the host and has not caused a shutdown, so include the bit
unconditionally.
Advertising of SUCCOR and OVERFLOW_RECOV in KVM would still be
Queued, thanks.
Paolo
On 11/9/23 08:20, Xin Li wrote:
Add VMX FRED controls used to enable save/load of FRED MSRs.
Tested-by: Shan Kang
Signed-off-by: Xin Li
---
scripts/kvm/vmxcap | 3 +++
target/i386/cpu.c | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/scripts/kvm/vmxcap
Queued, thanks.
Thanks for persisting! It sucks that the hv_vcpu_interrupt() API docs
are not clear, but your tests are great. The self-interrupt one is
the case that I was most worried about, and you're covering it.
Sorry for being a pain for nothing, at least retrospectively.
Paolo
to the wording.
Signed-off-by: Paolo Bonzini
---
docs/devel/build-system.rst| 13 ++---
configure | 4
python/scripts/vendor.py | 3 ---
python/wheels/tomli-2.0.1-py3-none-any.whl | Bin 12757 -> 0 bytes
4 files chan
quot;
mode that does not use any system packages will only work with Python
3.11+.
Signed-off-by: Paolo Bonzini
---
python/scripts/mkvenv.py | 105 ---
1 file changed, 105 deletions(-)
diff --git a/python/scripts/mkvenv.py b/python/scripts/mkvenv.py
index d
e isolated mode does not exist yet, this is left for the future
comtemplation.
Paolo
[1] isolated mode probably would benefit from installing distlib instead
of using the pip._vendor.distlib hack; therefore, adding tomli would
not be a huge deal anyway.
Paolo Bonzini (2):
Revert "python: u
On 6/5/24 17:25, Zhao Liu wrote:
Compiling without system, user, tools or guest-agent fails with the
following error message:
./configure --disable-system --disable-user --disable-tools \
--disable-guest-agent
error message:
/usr/bin/ld: libqemuutil.a.p/util_error-report.c.o: in function
Queued, thanks.
Paolo
Queued, thanks.
Paolo
Il gio 6 giu 2024, 05:52 Richard Henderson
ha scritto:
> > SEV_COMMON(object_dynamic_cast()) looks to be twice cast, we can just
> > force to do conversion with pointer type:
> >
> > (SevCommonState *) object_dynamic_cast(OBJECT(cgs), TYPE_SEV_COMMON)
>
> You don't need the explicit cast either,
There can be other confidential computing classes that are not derived
from sev-common. Avoid aborting when encountering them.
Signed-off-by: Paolo Bonzini
---
target/i386/sev.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/sev.c b/target/i386/sev.c
index
This has been the default forever.
Acked-by: Alex Bennée
Signed-off-by: Paolo Bonzini
---
docs/pci_expander_bridge.txt | 2 +-
docs/specs/tpm.rst| 2 +-
tests/avocado/intel_iommu.py | 2 +-
tests/avocado/smmu.py | 2 +-
tests/avocado/tuxrun_baselines.py
i386/sev: Invoke launch_updata_data() for SNP class
Paolo Bonzini (15):
docs, tests: do not specify scsi=off
virtio-blk: remove SCSI passthrough functionality
host/i386: nothing looks at CPUINFO_SSE4
meson: assume x86-64-v2 baseline ISA
host/i386: assume presen
This has been the default forever.
Signed-off-by: Paolo Bonzini
---
docs/pci_expander_bridge.txt | 2 +-
docs/specs/tpm.rst| 2 +-
tests/avocado/intel_iommu.py | 2 +-
tests/avocado/smmu.py | 2 +-
tests/avocado/tuxrun_baselines.py | 2 +-
5 files changed
On Tue, Jun 4, 2024 at 3:49 PM Richard Henderson
wrote:
> Oh, based on the next patch, it would appear that PAUSE does not single-step
> properly
> because it sets EXCP_INTERRUPT, and end-of-insn single-step depends on
> exception_index ==
> -1. I'm thinking of the bottom of cpu_tb_exec().
On Tue, Jun 4, 2024 at 12:59 PM Richard Henderson
wrote:
>
> On 6/4/24 02:18, Paolo Bonzini wrote:
> > Use decode.c's support for intercepts, doing the check in TCG-generated
> > code rather than the helper. This is cleaner because it allows removing
> > the eip_addend
tive; none of this is done by HLT and PAUSE.
Start fixing PAUSE, HLT will follow.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/misc_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
index 8316d42ffcd..ed4cda8001e 100644
--
-by: Paolo Bonzini
---
target/i386/tcg/sysemu/misc_helper.c | 2 +-
target/i386/tcg/sysemu/seg_helper.c | 17 ++---
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/i386/tcg/sysemu/misc_helper.c
b/target/i386/tcg/sysemu/misc_helper.c
index 093cc2d0f90..7fa0c5a06de
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/sysemu/bpt_helper.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/i386/tcg/sysemu/bpt_helper.c
b/target/i386/tcg/sysemu/bpt_helper.c
index c1d5fce250c..b29acf41c38 100644
--- a/target/i386/tcg/sysemu/bpt_helper.c
+++ b/target
DR7.GD triggers a #DB exception on any access to debug registers.
The GD bit is cleared so that the #DB handler itself can access
the debug registers.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/sysemu/bpt_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target
ICEBP generates a trap-like exception, while gen_exception() produces
a fault. Resurrect gen_update_eip_next() to implement the desired
semantics.
Signed-off-by: Paolo Bonzini
---
target/i386/helper.h | 1 +
target/i386/tcg/helper-tcg.h | 3 +++
target/i386/tcg/bpt_helper.c | 6
DISAS_NORETURN suppresses the work normally done by gen_eob(), and therefore
must be used in special cases only. Document them.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/target/i386/tcg/translate.c b/target
cpu_x86_update_dr7
to load DR7.
Because cpu_x86_update_dr7 takes a 32-bit argument, check
reserved bits prior to calling cpu_x86_update_dr7, and do the
same for DR6 as well for consistency.
This scenario is tested by the "host_rflags" test in kvm-unit-tests.
Signed-off-by: Paolo Bonzini
-
nts with quotes from the manual about the tasks performed
by a #VMEXIT.
Another gen_eob() task that is missing in VMRUN is preparing the
HF_INHIBIT_IRQ flag for the next instruction, in this case by loading
it from the VMCB control state.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/sys
When preparing an exception stack frame for a fault exception, the value
pushed for RF is 1. Take that into account. The same should be true
of interrupts for repeated string instructions, but the situation there
is complicated.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/seg_helper.c
Use decode.c's support for intercepts, doing the check in TCG-generated
code rather than the helper. This is cleaner because it allows removing
the eip_addend argument to helper_hlt().
Signed-off-by: Paolo Bonzini
---
target/i386/helper.h | 2 +-
target/i386/tcg/sysemu
Use decode.c's support for intercepts, doing the check in TCG-generated
code rather than the helper. This is cleaner because it allows removing
the eip_addend argument to helper_pause(), even though it adds a bit of
bloat for opcode 0x90's new decoding function.
Signed-off-by: Paolo Bonzini
it has a few more fixes for
failures in kvm-unit-tests debug.flat and svm.flat. Note that
neither of the two completely pass, but the situation is
improved a lot. Comments are added when things are more
complicated and probably deserve their own series.
Paolo
Paolo Bonzini (11):
target/i386: fix
.gu...@amd.com>
Signed-off-by: Paolo Bonzini
---
target/i386/sev.c| 39 +++
target/i386/trace-events | 1 +
2 files changed, 40 insertions(+)
diff --git a/target/i386/sev.c b/target/i386/sev.c
index 43d1c48bd9e..e89b87d2f55 100644
--- a/target/i386/sev.c
-24-pankaj.gu...@amd.com>
Signed-off-by: Paolo Bonzini
---
include/hw/i386/pc.h | 2 +
target/i386/sev.c| 113 ---
2 files changed, 86 insertions(+), 29 deletions(-)
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index c653b8eeb24..ca790
1 - 100 of 46418 matches
Mail list logo
