[PATCH v3] disas/riscv.c: rvv: Add disas support for vector instructions

Tested with https://github.com/ksco/rvv-decoder-tests Expected checkpatch errors for consistency and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: braces {} are necessary for all arms of this statement Signed-off-by: Yang Liu

[PATCH v2] disas/riscv.c: rvv: Add disas support for vector instructions

Tested with https://github.com/ksco/rvv-decoder-tests Expected checkpatch errors for consistency and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: braces {} are necessary for all arms of this statement Signed-off-by: Yang Liu

[PATCH] disas/riscv.c: rvv: Add disas support for vector instructions

Tested with https://github.com/ksco/rvv-decoder-tests Expected checkpatch errors for consistency and brevity reasons: ERROR: line over 90 characters ERROR: trailing statements should be on next line ERROR: braces {} are necessary for all arms of this statement Signed-off-by: Yang Liu

[PATCH 1/2] target/riscv: rvv-1.0: Simplify vfwredsum code

Remove duplicate code by wrapping vfwredsum_vs's OP function. Signed-off-by: Yang Liu --- target/riscv/vector_helper.c | 56 +++- 1 file changed, 10 insertions(+), 46 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index

[PATCH 2/2] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered

Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed to vf[w]redusum_vs. The distinction between ordered and unordered is also more consistent with other instructions, although there is no difference in implementation between the two for QEMU. Signed-off-by: Yang Liu