在 2022/11/15 下午8:10, Philippe Mathieu-Daudé 写道:
On 15/11/22 12:56, Xiaojuan Yang wrote:
Add cfi01 pflash device for LoongArch virt machine
So the subject prefix should be "hw/loongarch/virt:".
Signed-off-by: Xiaojuan Yang
---
hw/loongarch/Kconfig | 1 +
在 2022/10/21 下午5:11, Philippe Mathieu-Daudé 写道:
On 21/10/22 03:53, Xiaojuan Yang wrote:
1. When cpu read or write extioi COREISR reg, it should access
the reg belonged to itself, so the cpu index of 's->coreisr'
is current cpu number. Using MemTxAttrs' requester_id to get
the cpu index.
2. it
在 2022/9/29 上午10:42, Richard Henderson 写道:
On 9/26/22 23:12, Xiaojuan Yang wrote:
In ipi_send function, it should not to set irq before
writing data to dest cpu iocsr space, as the irq will
trigger after data writing.
Signed-off-by: Xiaojuan Yang
---
hw/intc/loongarch_ipi.c | 1 -
1 file
Hi Peter
On 2022/6/28 下午7:05, Peter Maydell wrote:
On Tue, 7 Jun 2022 at 00:34, Richard Henderson
wrote:
From: Xiaojuan Yang
This patch add ls7a rtc device support.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
Reviewed-by: Richard Henderson
Message-Id:
在 2022/5/25 6:41, Richard Henderson 写道:
On 5/24/22 15:32, Richard Henderson wrote:
When the syntax errors are fixed, it does not pass "make check".
When I configure with --enable-debug --enable-sanitizers I get
I got the same error.
The 'make check ' result:
Summary of Failures:
Hi, Richard
在 2022/5/25 6:32, Richard Henderson 写道:
On 5/24/22 01:17, Xiaojuan Yang wrote:
Hi All,
As this series only supports running binary files in ELF format, and
does not depend on BIOS and kernel file. so this series are changed
from RFC to patch vX.
The manual:
-
On 2022/5/19 下午11:24, Richard Henderson wrote:
On 5/19/22 06:04, yangxiaojuan wrote:
On 2022/5/19 上午3:59, Richard Henderson wrote:
On 5/17/22 04:30, Xiaojuan Yang wrote:
+static void ls7a_stop_toymatch(LS7ARtcState *s)
+{
+ int i;
+ uint64_t now;
+
+ now = qemu_clock_get_ms
On 2022/5/19 上午3:59, Richard Henderson wrote:
On 5/17/22 04:30, Xiaojuan Yang wrote:
+static void ls7a_stop_toymatch(LS7ARtcState *s)
+{
+ int i;
+ uint64_t now;
+
+ now = qemu_clock_get_ms(rtc_clock);
+ for (i = 0; i < TIMER_NUMS; i++) {
+ if (s->toy_timer[i].flag) {
+
Hi Richard
On 2022/5/19 上午2:04, Richard Henderson wrote:
+ uint64_t sw_isr[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP][EXTIOI_IRQS
/ 64];
This has not been declared with DECLARE_BITMAP, therefore you will see
a compile-time error when building on an ILP32 (i686) or P64 (win64)
host.
I pointed
On 2022/5/12 上午9:58, maobibo wrote:
在 2022/5/11 22:14, Richard Henderson 写道:
On 5/11/22 02:54, yangxiaojuan wrote:
On 2022/5/10 上午1:56, Richard Henderson wrote:
+ case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
+ index = (offset - EXTIOI_IPMAP_START) >> 2;
+ s-
On 2022/5/10 上午1:56, Richard Henderson wrote:
On 5/9/22 04:38, yangxiaojuan wrote:
You are not considering CSR[0x420][49], which changes the format of
this mapping.
Thanks very much, I will consider the mapping format by read
iocsr[0x420][49] like this:
static uint64_t map_format(void
On 2022/5/10 上午1:56, Richard Henderson wrote:
+ case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
+ index = (offset - EXTIOI_IPMAP_START) >> 2;
+ s->ipmap[index] = val;
+ break;
Do you need to recompute the entire interrupt map when ipmap changes?
Sorry, could you
On 2022/5/10 上午4:29, Richard Henderson wrote:
On 4/29/22 05:06, Xiaojuan Yang wrote:
+ DEFINE_LOONGARCH_CPU_TYPE("Loongson-3A5000", loongarch_3a5000_initfn),
Follow up on the comments against patch 34, and reading the 3A5000
manual, I see
# On-chip integration of four 64-bit quad-launch
On 2022/5/8 上午5:55, Richard Henderson wrote:
On 4/29/22 05:07, Xiaojuan Yang wrote:
+/*
+ * Shift bits and filed mask
+ */
+#define TOY_MON_MASK 0x3f
+#define TOY_DAY_MASK 0x1f
+#define TOY_HOUR_MASK 0x1f
+#define TOY_MIN_MASK 0x3f
+#define TOY_SEC_MASK 0x3f
+#define TOY_MSEC_MASK
On 2022/5/7 下午11:31, Richard Henderson wrote:
+ if (level) {
+ /* if not enable return false */
+ if (((s->enable[enable_index]) & (1 << enable_mask)) == 0) {
+ return;
+ }
+ s->coreisr[cpu][coreisr_index] |= (1 << coreisr_mask);
+
Hi Richard,
On 2022/5/7 下午11:31, Richard Henderson wrote:
On 4/29/22 05:07, Xiaojuan Yang wrote:
+ int ipmap_mask = 0xff << ipmap_offset;
...
+ int cpu_mask = 0xff << ipmap_offset;
These two masks are redundant with
+ ipnum = ((s->ipmap[ipmap_index] & ipmap_mask) >> ipmap_offset)
Hi Richard and Mark,
Could you help us review the patch [1] ?
[1] :
[PATCH v3 34/43] hw/intc: Add LoongArch extioi interrupt
[PATCH v3 38/43] hw/loongarch: Add LoongArch ls7a rtc device support
[PATCH v3 39/43] hw/loongarch: Add LoongArch load elf function.
[PATCH v3 40/43] hw/loongarch: Add
Hi Richard,
On 2022/5/1 上午1:22, Richard Henderson wrote:
On 4/29/22 03:07, Xiaojuan Yang wrote:
+ [LOONGARCH_CSR_CPUID] = {
+ .offset = -1,
+ .flags = CSRFL_READONLY,
+ .readfn = gen_helper_csrrd_cpuid,
+ .writefn = NULL
+ },
The offset should be
Hi Mark,
On 2022/4/26 上午12:27, Mark Cave-Ayland wrote:
On 25/04/2022 10:10, Xiaojuan Yang wrote:
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 +
hw/intc/loongarch_extioi.c |
Hi, Richard
On 2022/4/26 上午6:55, Richard Henderson wrote:
On 4/25/22 02:10, Xiaojuan Yang wrote:
+static void output_r_csr(DisasContext *ctx, arg_r_csr *a,
+ const char *mnemonic)
+{
+ output(ctx, mnemonic, "r%d, %d # %s", a->rd, a->csr,
csr_names[a->csr]);
+}
+
On 2022/4/20 上午1:05, Richard Henderson wrote:
You'd use a store, just like you were already doing in trans_csrwr.
But here's how I'd improve this. For avoidance of doubt, all of this
would go in trans_priviledged.c.inc -- there's no use of csr_offsets[]
outside of that file.
Thanks you
On 2022/4/20 上午1:14, Richard Henderson wrote:
The emulate of PCH_PIC_CLR in qemu LoongArchPCHPIC struct member is
intirr_lo/hi(we devide 64bits reg to two 32bits reg to match the
linux kernel), it will be changed when we config clear reg or handler
irq.
static void
On 2022/4/16 上午9:04, Richard Henderson wrote:
On 4/15/22 02:40, Xiaojuan Yang wrote:
...
+void helper_csr_update(CPULoongArchState *env, target_ulong new_val,
+ target_ulong csr_offset)
+{
+ uint64_t *csr = (void *)env + csr_offset;
+
+ *csr = new_val;
+}
This
On 2022/4/18 下午10:39, Richard Henderson wrote:
On 4/18/22 02:14, yangxiaojuan wrote:
Hi, Richard
On 2022/4/18 上午11:15, Richard Henderson wrote:
On 4/15/22 02:40, Xiaojuan Yang wrote:
+static void pch_pic_update_irq(LoongArchPCHPIC *s, uint32_t mask,
+ int level
On 2022/4/18 下午4:57, Mark Cave-Ayland wrote:
On 18/04/2022 04:48, Richard Henderson wrote:
On 4/15/22 02:40, Xiaojuan Yang wrote:
+ memory_region_init(>mmio[cpu], OBJECT(s),
+ "loongarch_extioi", EXTIOI_SIZE);
+
+ memory_region_init_io(>mmio_nodetype[cpu],
On 2022/4/16 上午9:04, Richard Henderson wrote:
+int cpu_csr_offset(unsigned csr_num);
...
+static const uint64_t csr_offsets[] = {
There's no reason for this array to be uint64_t.
It really should match the function.
Yes, we shoud do this.
If we use 'int', we may get a warning:
Hi, Richard
On 2022/4/18 上午11:15, Richard Henderson wrote:
On 4/15/22 02:40, Xiaojuan Yang wrote:
+static void pch_pic_update_irq(LoongArchPCHPIC *s, uint32_t mask,
+ int level, int hi)
+{
+ uint32_t val, irq;
+
+ if (level == 1) {
+ if (hi) {
+
Hi,
On 2022/3/29 上午5:02, Mark Cave-Ayland wrote:
+static const MemoryRegionOps loongarch_qemu_ops = {
+ .read = loongarch_qemu_read,
+ .write = loongarch_qemu_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 8,
+
On 2022/3/29 上午6:43, Richard Henderson wrote:
On 3/28/22 06:57, Xiaojuan Yang wrote:
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 3 +
hw/intc/loongarch_extioi.c | 408
On 2022/3/29 上午4:19, Richard Henderson wrote:
On 3/28/22 06:57, Xiaojuan Yang wrote:
1.This patch Add loongarch interrupt and exception handle.
2.Rename the user excp to the exccode from the csr defintions.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
On 2022/3/29 上午4:18, Mark Cave-Ayland wrote:
On 28/03/2022 13:57, Xiaojuan Yang wrote:
This patch realize the PCH-PIC interrupt controller.
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
hw/intc/Kconfig | 4 +
hw/intc/loongarch_pch_pic.c | 488
On 2022/3/29 上午4:16, Richard Henderson wrote:
On 3/28/22 06:57, Xiaojuan Yang wrote:
+void helper_idle(CPULoongArchState *env)
+{
+ CPUState *cs = env_cpu(env);
+
+ cs->halted = 1;
+ cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
+ do_raise_exception(env, EXCP_HLT, 0);
+}
Why are
Hi Mark,
On 2022/3/29 上午4:15, Mark Cave-Ayland wrote:
+
+#define TYPE_LOONGARCH_IPI "loongarch_ipi"
+OBJECT_DECLARE_SIMPLE_TYPE(LoongArchIPI, LOONGARCH_IPI)
+
+typedef struct IPICore {
+ uint32_t status;
+ uint32_t en;
+ uint32_t set;
+ uint32_t clear;
+ /* 64bit buf divide into
On 2022/3/29 上午4:12, Richard Henderson wrote:
On 3/28/22 06:57, Xiaojuan Yang wrote:
+static void output_empty(DisasContext *ctx, arg_empty *a,
+ const char *mnemonic)
+{
+}
No, you must still do
output(ctx, mnemonic, "");
+static bool trans_tlbwr(DisasContext
On 2022/3/29 上午3:46, Richard Henderson wrote:
On 3/28/22 06:57, Xiaojuan Yang wrote:
+void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
+ uint64_t value)
+{
+ CPULoongArchState *env = >env;
+ uint64_t now, next;
+
+
On 2022/3/29 上午3:16, Richard Henderson wrote:
On 3/28/22 06:57, Xiaojuan Yang wrote:
+++ b/target/loongarch/cpu.h
@@ -11,6 +11,7 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "hw/registerfields.h"
+#include "cpu-csr.h"
Do you need this include here?
No.
I
On 2022/3/29 上午2:55, Richard Henderson wrote:
On 3/28/22 06:57, Xiaojuan Yang wrote:
+uint64_t helper_iocsr_read(CPULoongArchState *env, target_ulong r_addr,
+ uint32_t size)
+{
+ int cpuid = env_cpu(env)->cpu_index;
+ CPUState *cs = qemu_get_cpu(cpuid);
+
On 2022/3/29 上午2:34, Richard Henderson wrote:
+target_ulong helper_csr_rdq(CPULoongArchState *env, uint64_t csr)
+{
+ LoongArchCPU *cpu;
+ int64_t v;
+
+ switch (csr) {
+ case LOONGARCH_CSR_PGD:
+ if (env->CSR_TLBRERA & 0x1) {
+ v = env->CSR_TLBRBADV;
+ }
Hi Richard.
On 2022/3/29 上午2:13, Richard Henderson wrote:
On 3/28/22 06:57, Xiaojuan Yang wrote:
This series patch add softmmu support for LoongArch.
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
The latest uefi:
* https://github.com/loongson/edk2
*
Ping !!!
On 2022/2/25 下午4:02, Xiaojuan Yang wrote:
This series patch add softmmu support for LoongArch.
The latest kernel:
* https://github.com/loongson/linux/tree/loongarch-next
The latest uefi:
* https://github.com/loongson/edk2
* https://github.com/loongson/edk2-platforms
The
Hi, Mark
On 02/05/2022 09:32 PM, Mark Cave-Ayland wrote:
> On 28/01/2022 03:40, Xiaojuan Yang wrote:
>
>> This series patch add softmmu support for LoongArch.
>> The latest kernel:
>>* https://github.com/loongson/linux/tree/loongarch-next
>> The latest uefi:
>>*
Hi, Mark
在 2022年01月15日 20:52, Mark Cave-Ayland 写道:
> On 08/01/2022 09:13, Xiaojuan Yang wrote:
>
>> This patch introduce vmstate_loongarch_cpu
>>
>> Signed-off-by: Xiaojuan Yang
>> Signed-off-by: Song Gao
>> Reviewed-by: Richard Henderson
>> ---
>> target/loongarch/cpu.c | 3 ++
>>
Hi, Mark
On 01/15/2022 10:11 PM, Mark Cave-Ayland wrote:
> On 08/01/2022 09:13, Xiaojuan Yang wrote:
>
>> This series patch add softmmu support for LoongArch.
>> Base on the linux-user emulation support V14 patch.
>>* https://patchew.org/QEMU/20220106094200.1801206-1-gaos...@loongson.cn/
>>
Hi, Xuerui
Thank you for all you advice, I will modify the target part carefully.
Xiaojuan
On 01/09/2022 05:26 PM, WANG Xuerui wrote:
> Hi Xiaojuan,
>
> I've just finished reviewing the first part (target modifications) as I'm not
> familiar with QEMU device emulation. You may have to
Hi, Mark
On 12/23/2021 06:52 PM, Mark Cave-Ayland wrote:
> On 22/12/2021 08:26, yangxiaojuan wrote:
>
>> Hi, Mark
>>
>> On 12/18/2021 06:02 PM, Mark Cave-Ayland wrote:
>>> On 04/12/2021 12:07, Xiaojuan Yang wrote:
>>>
>>>> 1.Add uart,virtio-
Hi,Mark:
Sorry for the late reply. I just saw the mail after I send the v4 patch. I
sorted the mail into different folders from
the qemu-devel, so I didn't see the mail in time. Sorry again.
Xiaojuan
On 12/23/2021 06:21 PM, Mark Cave-Ayland wrote:
> On 22/12/2021 02:38, yangxiaojuan wr
Hi, Mark
On 12/18/2021 06:02 PM, Mark Cave-Ayland wrote:
> On 04/12/2021 12:07, Xiaojuan Yang wrote:
>
>> 1.Add uart,virtio-net,vga and usb for 3A5000.
>> 2.Add irq set and map for the pci host. Non pci device
>> use irq 0-16, pci device use 16-64.
>> 3.Add some unimplented device to emulate
Hi, Mark
On 12/18/2021 08:33 AM, Mark Cave-Ayland wrote:
> On 04/12/2021 12:07, Xiaojuan Yang wrote:
>
>> This patch realize the PCH-PIC interrupt controller.
>>
>> Signed-off-by: Xiaojuan Yang
>> Signed-off-by: Song Gao
>> ---
>> hw/intc/Kconfig | 4 +
>>
Hi,Mark
On 12/18/2021 07:54 AM, Mark Cave-Ayland wrote:
> On 04/12/2021 12:07, Xiaojuan Yang wrote:
>
>> Loongson-3A5000 support 14 interrupts from 64 - 77(Timer->75 IPI->76)
>> Loongson-3A5000 and ls7a form a legacy model and extended model irq
>> hierarchy.Tcg mode emulate a simplified
Hi, Mark
On 12/18/2021 07:39 AM, Mark Cave-Ayland wrote:
> On 04/12/2021 12:07, Xiaojuan Yang wrote:
>
>> This is a model of the PCIe Host Bridge found on a Loongson-5000
>> processor. It includes a interrupt controller, some interface for
>> pci and nonpci devices. Mainly emulate part of it
thank you!
On 12/14/2021 06:43 AM, Mark Cave-Ayland wrote:
> On 13/12/2021 03:13, yangxiaojuan wrote:
>
>> Ping!
>>
>> Please help review the V3 patch, thank you!
>
> I've been fairly busy recently, but I will try and find some time to look at
> the v3 some
Ping!
Please help review the V3 patch, thank you!
On 12/04/2021 08:06 PM, Xiaojuan Yang wrote:
> This series patch add softmmu support for LoongArch.
> Base on the linux-user emulation support V13 patch.
> *
> https://patchew.org/QEMU/1638610165-15036-1-git-send-email-gaos...@loongson.cn/
>
Hi, Huacai
On 12/06/2021 12:36 PM, chen huacai wrote:
> Hi, Xiaojuan,
>
> On Sat, Dec 4, 2021 at 8:11 PM Xiaojuan Yang wrote:
>>
>> Emulate a 3A5000 board use the new loongarch instruction.
>> 3A5000 belongs to the Loongson3 series processors.
>> The board consists of a 3A5000 cpu model and the
Hi,
On 12/05/2021 01:54 AM, Philippe Mathieu-Daudé wrote:
> On 12/4/21 13:07, Xiaojuan Yang wrote:
>> 1.Add uart,virtio-net,vga and usb for 3A5000.
>> 2.Add irq set and map for the pci host. Non pci device
>> use irq 0-16, pci device use 16-64.
>> 3.Add some unimplented device to emulate guest
Hi Mark,
On 11/11/2021 10:49 PM, Mark Cave-Ayland wrote:
> On 11/11/2021 01:35, Xiaojuan Yang wrote:
>
>> This patch realize the EIOINTC interrupt controller.
>>
>> Signed-off-by: Xiaojuan Yang
>> Signed-off-by: Song Gao
>> ---
>> hw/intc/Kconfig| 3 +
>>
On 11/17/2021 04:22 PM, Richard Henderson wrote:
> On 11/17/21 8:29 AM, yangxiaojuan wrote:
>> On 11/12/2021 02:14 AM, Richard Henderson wrote:
>>> On 11/11/21 2:35 AM, Xiaojuan Yang wrote:
>>>> +static bool trans_tlbwr(DisasContext *ctx, arg_tlbwr *a)
>>
Hi, Richard:
On 11/12/2021 01:43 AM, Richard Henderson wrote:
> On 11/11/21 2:35 AM, Xiaojuan Yang wrote:
>> This includes:
>> - CSRRD
>> - CSRWR
>> - CSRXCHG
>> - IOCSR{RD/WR}.{B/H/W/D}
>
> I think IOCSR should be in a separate patch.
> It's completely unrelated to the other CSRs.
>
>>
Hi, Richard:
On 11/12/2021 02:14 AM, Richard Henderson wrote:
> On 11/11/21 2:35 AM, Xiaojuan Yang wrote:
>> +static bool trans_tlbwr(DisasContext *ctx, arg_tlbwr *a)
>> +{
>> +gen_helper_check_plv(cpu_env);
>> +gen_helper_tlbwr(cpu_env);
>> +tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next
Hi, Richard:
On 11/11/2021 11:53 PM, Richard Henderson wrote:
> On 11/11/21 2:35 AM, Xiaojuan Yang wrote:
>> This patch introduces basic TLB interfaces.
>>
>> Signed-off-by: Xiaojuan Yang
>> Signed-off-by: Song Gao
>> ---
>> target/loongarch/cpu-param.h | 3 +
>> target/loongarch/cpu.c
emulated LS7A and the other is pure virtual). I think we can call them
> "loongson3-ls7a" and "loongson3-virt".
>
> Huacai
Thank you for your advice, I didn't think comprehensively. I will modify in
the next versison.
Thanks,
Xiaojuan
>> +
>> +The vmlinux, ramdisk and uefi binary loongarch_bios.bin can get from :
>> +git clone https://github.com/yangxiaojuan-loongson/qemu-binary
>>
>> - Note.
>>We can get the latest LoongArch documents or LoongArch tools at
>> https://github.com/loongson/
>> --
>> 2.27.0
>>
>>
>
>
Hi Richard,
On 11/11/2021 09:36 PM, Richard Henderson wrote:
> On 11/11/21 2:35 AM, Xiaojuan Yang wrote:
>> +++ b/target/loongarch/cpu.h
>> @@ -369,8 +369,21 @@ enum {
>> EXCP_BREAK,
>> EXCP_INE,
>> EXCP_FPE,
>> -
>> -EXCP_LAST = EXCP_FPE,
>> +EXCP_IPE,
>> +
Hi, Richard,
On 11/11/2021 09:29 PM, Richard Henderson wrote:
> On 11/11/21 2:35 AM, Xiaojuan Yang wrote:
>> +#define LOONGARCH_CSR_MISC 0x3 /* Misc config */
>> +
>
> Missing bitfield definitions for misc.
>
At present, there is no read/write to each field of misc register so it is
Hi, Mark,
On 11/11/2021 10:58 PM, Mark Cave-Ayland wrote:
> On 11/11/2021 01:34, Xiaojuan Yang wrote:
>
>> Sorry only part of the v2 patch succeed. I consulted GNU sysadmin,
>> He said our mail server was getting temporarily banned by fail2ban. Now the
>> ban
>> was removed. I resend the v2
Hi, Richard:
On 10/20/2021 12:19 PM, Richard Henderson wrote:
> On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
>> This includes:
>> - TLBSRCH
>> - TLBRD
>> - TLBWR
>> - TLBFILL
>> - TLBCLR
>> - TLBFLUSH
>> - INVTLB
>>
>> Signed-off-by: Xiaojuan Yang
>> Signed-off-by: Song Gao
>> ---
>>
Hi, Richard:
On 10/20/2021 09:36 AM, Richard Henderson wrote:
> On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
>> +target_ulong helper_csr_rdq(CPULoongArchState *env, uint64_t csr)
>> +{
>> +int64_t v;
>> +
>> +#define CASE_CSR_RDQ(csr)\
>> +case LOONGARCH_CSR_ ## csr: \
>> +
在 2021年10月20日 02:56, Richard Henderson 写道:
> On 10/19/21 12:34 AM, Xiaojuan Yang wrote:
>> ---
>> target/loongarch/README | 134 +++
>> target/loongarch/ramdisk | Bin 0 -> 3077952 bytes
>> target/loongarch/vmlinux | Bin 0 -> 24565536 bytes
>> 3 files
Hi,Bob
Thank you for your advice, I'll try.
Thanks
Xiaojuan, Yang
在 2021年10月22日 08:12, Bob Proulx 写道:
> WANG Xuerui wrote:
>> Song Gao wrote:
>>> Account yangxiaoj...@loongson.cn It seems that she has been
>>> blacklisted. Xiaojuan sent 31 e-mails, which were not displayed
>>> since the
am so sorry. My patch can be abandoned.
I am from loongson. We want to add a new board support to
the community.Later we will submit more code.
thanks
Xiaojuan Yang
On 5/18/21 11:49 PM, Laszlo Ersek wrote:
> On 05/18/21 14:43, Xiaojuan Yang wrote:
>> From: yangxiaojuan
>>
>
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