On Fri, 31 Mar 2023 at 11:09, Edgar E. Iglesias
wrote:
>
>
> On Thu, Mar 23, 2023 at 7:29 PM Chris Rauer wrote:
>>
>> The problem is that the Linux driver expects the master transaction inhibit
>> bit(R_SPICR_MTI) to be set during driver initialization so that it can
>> detect the fifo size but
On Thu, Mar 23, 2023 at 7:29 PM Chris Rauer wrote:
> The problem is that the Linux driver expects the master transaction inhibit
> bit(R_SPICR_MTI) to be set during driver initialization so that it can
> detect the fifo size but QEMU defaults it to zero out of reset. The
> datasheet indicates
Ping to the Xilinx folks, do you want to review this?
thanks
-- PMM
On Thu, 23 Mar 2023 at 18:28, Chris Rauer wrote:
>
> The problem is that the Linux driver expects the master transaction inhibit
> bit(R_SPICR_MTI) to be set during driver initialization so that it can
> detect the fifo size
The problem is that the Linux driver expects the master transaction inhibit
bit(R_SPICR_MTI) to be set during driver initialization so that it can
detect the fifo size but QEMU defaults it to zero out of reset. The
datasheet indicates this bit is active on reset.
See page 25, SPI Control
