09.04.2024 14:02, Paolo Bonzini wrote:
On Tue, Apr 9, 2024 at 12:59 PM Zhao Liu wrote:
Hi Michael & Paolo,
I debugged it manually, and found the problem occurs in tlb_index() with
mmu_idx=5.
For v7.2, the maximum mmu index supported by i386 is 4 (since
NB_MMU_MODES = 5 defined in
On Tue, Apr 9, 2024 at 12:59 PM Zhao Liu wrote:
>
> Hi Michael & Paolo,
>
> On Fri, Apr 05, 2024 at 08:30:43PM +0300, Michael Tokarev wrote:
> > Date: Fri, 5 Apr 2024 20:30:43 +0300
> > From: Michael Tokarev
> > Subject: Re: [PATCH] target/i386:
Hi Michael & Paolo,
On Fri, Apr 05, 2024 at 08:30:43PM +0300, Michael Tokarev wrote:
> Date: Fri, 5 Apr 2024 20:30:43 +0300
> From: Michael Tokarev
> Subject: Re: [PATCH] target/i386: fix direction of "32-bit MMU" test
>
> 01.04.2024 09:02, Michael Tokarev
08.04.2024 23:12, Paolo Bonzini wrote:
Il ven 5 apr 2024, 19:30 Michael Tokarev mailto:m...@tls.msk.ru>> ha scritto:
It sigsegvs in probe_access_internal():
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); -- this one returns
NULL,
and next there's a call
Il ven 5 apr 2024, 19:30 Michael Tokarev ha scritto:
> 01.04.2024 09:02, Michael Tokarev:
>
> > Anyone can guess why this rather trivial and obviously correct patch
> causes segfaults
> > in a few tests in staging-7.2 - when run in tcg mode, namely:
> >
> >pxe-test
> >migration-test
> >
On 5/4/24 19:30, Michael Tokarev wrote:
01.04.2024 09:02, Michael Tokarev:
Anyone can guess why this rather trivial and obviously correct patch
causes segfaults
in a few tests in staging-7.2 - when run in tcg mode, namely:
pxe-test
migration-test
boot-serial-test
bios-tables-test
01.04.2024 09:02, Michael Tokarev:
Anyone can guess why this rather trivial and obviously correct patch causes
segfaults
in a few tests in staging-7.2 - when run in tcg mode, namely:
pxe-test
migration-test
boot-serial-test
bios-tables-test
vmgenid-test
cdrom-test
When
11.03.2024 10:58, Paolo Bonzini wrote:
The low bit of MMU indices for x86 TCG indicates whether the processor is
in 32-bit mode and therefore linear addresses have to be masked to 32 bits.
However, the index was computed incorrectly, leading to possible conflicts
in the TLB for any address above
On 11/03/2024 07:58, Paolo Bonzini wrote:
The low bit of MMU indices for x86 TCG indicates whether the processor is
in 32-bit mode and therefore linear addresses have to be masked to 32 bits.
However, the index was computed incorrectly, leading to possible conflicts
in the TLB for any address
On 3/10/24 21:58, Paolo Bonzini wrote:
The low bit of MMU indices for x86 TCG indicates whether the processor is
in 32-bit mode and therefore linear addresses have to be masked to 32 bits.
However, the index was computed incorrectly, leading to possible conflicts
in the TLB for any address above
The low bit of MMU indices for x86 TCG indicates whether the processor is
in 32-bit mode and therefore linear addresses have to be masked to 32 bits.
However, the index was computed incorrectly, leading to possible conflicts
in the TLB for any address above 4G.
Analyzed-by: Mark Cave-Ayland
11 matches
Mail list logo
