On Thu, Mar 11, 2021 at 11:47 PM Alistair Francis wrote:
>
> On Thu, Mar 11, 2021 at 2:03 AM Dylan Jhong wrote:
> >
> > On Wed, Mar 10, 2021 at 02:15:25PM +0800, Bin Meng wrote:
> > > On Wed, Mar 10, 2021 at 11:36 AM Dylan Jhong wrote:
> > > >
> > > > This provides a RISC-V Board based on
On Thu, Mar 11, 2021 at 2:03 AM Dylan Jhong wrote:
>
> On Wed, Mar 10, 2021 at 02:15:25PM +0800, Bin Meng wrote:
> > On Wed, Mar 10, 2021 at 11:36 AM Dylan Jhong wrote:
> > >
> > > This provides a RISC-V Board based on Andes's AE350 specification.
> > > The following machine is implemented:
> >
On Wed, Mar 10, 2021 at 02:15:25PM +0800, Bin Meng wrote:
> On Wed, Mar 10, 2021 at 11:36 AM Dylan Jhong wrote:
> >
> > This provides a RISC-V Board based on Andes's AE350 specification.
> > The following machine is implemented:
> >
> > - 'andes_ae350'; PLIC, PLICSW, PLMT, 16550a UART, VirtIO
On Wed, Mar 10, 2021 at 11:36 AM Dylan Jhong wrote:
>
> This provides a RISC-V Board based on Andes's AE350 specification.
> The following machine is implemented:
>
> - 'andes_ae350'; PLIC, PLICSW, PLMT, 16550a UART, VirtIO MMIO, device-tree
Is this a virtual target because virtio is added? Or
This provides a RISC-V Board based on Andes's AE350 specification.
The following machine is implemented:
- 'andes_ae350'; PLIC, PLICSW, PLMT, 16550a UART, VirtIO MMIO, device-tree
Signed-off-by: Dylan Jhong
Signed-off-by: Ruinland ChuanTzu Tsai
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default-configs/devices/riscv32-softmmu.mak