On 12/21/21 10:40 PM, Cédric Le Goater wrote:
The PID SPR of the 405 CPU contains the translation ID of the TLB
which is a 8-bit field. Enforce the mask with a store helper.
Cc: Christophe Leroy
Signed-off-by: Cédric Le Goater
---
target/ppc/spr_tcg.h | 1 +
target/ppc/cpu_init.c | 2 +-
The PID SPR of the 405 CPU contains the translation ID of the TLB
which is a 8-bit field. Enforce the mask with a store helper.
Cc: Christophe Leroy
Signed-off-by: Cédric Le Goater
---
target/ppc/spr_tcg.h | 1 +
target/ppc/cpu_init.c | 2 +-
target/ppc/translate.c | 8
3 files
