On 2/7/24 00:23, Peter Maydell wrote:
+++ b/linux-user/aarch64/target_prctl.h
@@ -173,21 +173,22 @@ static abi_long
do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
if (cpu_isar_feature(aa64_mte, cpu)) {
-
On 2/7/24 00:23, Peter Maydell wrote:
On Tue, 6 Feb 2024 at 03:06, Richard Henderson
wrote:
When MTE3 is supported, the kernel maps
PR_MTE_TCF_ASYNC | PR_MTE_TCF_SYNC
to
MTE_CTRL_TCF_ASYMM
and from there to
SCTLR_EL1.TCF0 = 3
This depends on the setting of
On 2/6/24 12:05 AM, Richard Henderson wrote:
When MTE3 is supported, the kernel maps
PR_MTE_TCF_ASYNC | PR_MTE_TCF_SYNC
to
MTE_CTRL_TCF_ASYMM
and from there to
SCTLR_EL1.TCF0 = 3
There is no error reported for setting ASYNC | SYNC when MTE3 is not
supported; the kernel simply selects
On Tue, 6 Feb 2024 at 03:06, Richard Henderson
wrote:
>
> When MTE3 is supported, the kernel maps
> PR_MTE_TCF_ASYNC | PR_MTE_TCF_SYNC
> to
> MTE_CTRL_TCF_ASYMM
> and from there to
> SCTLR_EL1.TCF0 = 3
This depends on the setting of
/sys/devices/system/cpu/cpu/mte_tcf_preferred :
I think
When MTE3 is supported, the kernel maps
PR_MTE_TCF_ASYNC | PR_MTE_TCF_SYNC
to
MTE_CTRL_TCF_ASYMM
and from there to
SCTLR_EL1.TCF0 = 3
There is no error reported for setting ASYNC | SYNC when MTE3 is not
supported; the kernel simply selects the ASYNC behavior of TCF0=2.
Signed-off-by:
