Hi Zhao,
On 8/4/23 04:56, Zhao Liu wrote:
> Hi Babu,
>
> On Thu, Aug 03, 2023 at 03:44:13PM -0500, Moger, Babu wrote:
>> Date: Thu, 3 Aug 2023 15:44:13 -0500
>> From: "Moger, Babu"
>> Subject: Re: [PATCH v3 16/17] i386: Use CPUCacheInfo.share_level to encode
Hi Babu,
On Thu, Aug 03, 2023 at 03:44:13PM -0500, Moger, Babu wrote:
> Date: Thu, 3 Aug 2023 15:44:13 -0500
> From: "Moger, Babu"
> Subject: Re: [PATCH v3 16/17] i386: Use CPUCacheInfo.share_level to encode
> CPUID[0x801D].EAX[bits 25:14]
>
> Hi Zhao,
>
Hi Zhao,
Please copy the thread to k...@vger.kernel.org also. It makes it easier
to browse.
On 8/1/23 05:35, Zhao Liu wrote:
> From: Zhao Liu
>
> CPUID[0x801D].EAX[bits 25:14] is used to represent the cache
> topology for amd CPUs.
Please change this to.
CPUID[0x801D].EAX[bits
From: Zhao Liu
CPUID[0x801D].EAX[bits 25:14] is used to represent the cache
topology for amd CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[0x801D].EAX[bits 25:14].
Signed-off-by: Zhao Liu
