On Wed, Aug 3, 2022 at 9:42 AM Atish Patra wrote:
>
> On Sun, Jul 24, 2022 at 9:39 PM Alistair Francis wrote:
> >
> > On Mon, Jul 25, 2022 at 1:48 PM Dao Lu wrote:
> > >
> > > This patch adds RISC-V Zihintpause support. The extension is set to be
> > > enabled
> > > by default and opcode has
On Sun, Jul 24, 2022 at 9:39 PM Alistair Francis wrote:
>
> On Mon, Jul 25, 2022 at 1:48 PM Dao Lu wrote:
> >
> > This patch adds RISC-V Zihintpause support. The extension is set to be
> > enabled
> > by default and opcode has been added to insn32.decode.
> >
> > Added trans_pause to exit the
On Mon, Jul 25, 2022 at 1:48 PM Dao Lu wrote:
>
> This patch adds RISC-V Zihintpause support. The extension is set to be enabled
> by default and opcode has been added to insn32.decode.
>
> Added trans_pause to exit the TB and return to main loop.
>
> The change can also be found in:
>
This patch adds RISC-V Zihintpause support. The extension is set to be enabled
by default and opcode has been added to insn32.decode.
Added trans_pause to exit the TB and return to main loop.
The change can also be found in:
https://github.com/dlu42/qemu/tree/zihintpause_support_v1
Tested along
