Re: [PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

2022-04-01 Thread Frederic Barrat
On 01/04/2022 03:59, Benjamin Herrenschmidt wrote: This one: #define PHB4_PEC_PCI_REGS_COUNT 0x2 Should be #define PHB4_PEC_PCI_REGS_COUNT 0x3 There is no register at 0x1 though. Patch on the way Fred

Re: [PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

2022-03-31 Thread Benjamin Herrenschmidt
On Thu, 2022-03-31 at 18:51 +0100, Peter Maydell wrote: > > Hi; Coverity has just spotted an error in this old change > (CID 1487176): Oh my this is old ... I don't work for IBM anymore but I found the relevant doc here:

Re: [PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

2022-03-31 Thread Peter Maydell
On Mon, 3 Feb 2020 at 06:11, David Gibson wrote: > > From: Benjamin Herrenschmidt > > These changes introduces models for the PCIe Host Bridge (PHB4) of the > POWER9 processor. It includes the PowerBus logic interface (PBCQ), > IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI

Re: [PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

2020-02-05 Thread Cédric Le Goater
diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index e27efe9a24..354828bf13 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -135,6 +135,8 @@ config XIVE_SPAPR default y depends on PSERIES select XIVE +select PCI +select

Re: [PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

2020-02-05 Thread Laurent Vivier
On 05/02/2020 16:27, Cédric Le Goater wrote: > On 2/5/20 2:26 PM, Laurent Vivier wrote: >> On 03/02/2020 07:11, David Gibson wrote: >>> From: Benjamin Herrenschmidt >>> >>> These changes introduces models for the PCIe Host Bridge (PHB4) of the >>> POWER9 processor. It includes the PowerBus logic

Re: [PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

2020-02-05 Thread Cédric Le Goater
On 2/5/20 2:26 PM, Laurent Vivier wrote: > On 03/02/2020 07:11, David Gibson wrote: >> From: Benjamin Herrenschmidt >> >> These changes introduces models for the PCIe Host Bridge (PHB4) of the >> POWER9 processor. It includes the PowerBus logic interface (PBCQ), >> IOMMU support, a single PCIe

Re: [PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

2020-02-05 Thread Greg Kurz
On Wed, 5 Feb 2020 14:26:41 +0100 Laurent Vivier wrote: > On 03/02/2020 07:11, David Gibson wrote: > > From: Benjamin Herrenschmidt > > > > These changes introduces models for the PCIe Host Bridge (PHB4) of the > > POWER9 processor. It includes the PowerBus logic interface (PBCQ), > > IOMMU

Re: [PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

2020-02-05 Thread Laurent Vivier
On 03/02/2020 07:11, David Gibson wrote: > From: Benjamin Herrenschmidt > > These changes introduces models for the PCIe Host Bridge (PHB4) of the > POWER9 processor. It includes the PowerBus logic interface (PBCQ), > IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI > and LSI

[PULL 19/35] ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge

2020-02-02 Thread David Gibson
From: Benjamin Herrenschmidt These changes introduces models for the PCIe Host Bridge (PHB4) of the POWER9 processor. It includes the PowerBus logic interface (PBCQ), IOMMU support, a single PCIe Gen.4 Root Complex, and support for MSI and LSI interrupt sources as found on a POWER9 system using